Review of SGMII Concepts

The Serial Gigabit Media Independent Interface (SGMII) is a popular Gigabit Ethernet PHY interface, and it holds various advantages over both GMII and RGMII. This article reviews some of the core SGMII concepts with the help of oscilloscope screen shots from our Rohde & Schwarz RTO1044.


This article reviews various SGMII concepts that are important to our Private Island project. We provide oscilloscope screen shots below from our Rohde & Schwarz RTO1044 to help illustrate the concepts.

As shown in the figure below, Private Island relies on an FPGA to interface with three single port SGMII Gigabit Ethernet PHYS. Unlike a typical SoC, the FPGA generates an external interrupt synchronous to specific packet transmit or receive events. The interrupt can also assert on specific octets / special codes within the Ethernet frame (i.e., end of packet). This interrupt flexibility is important for certain security functions and provides a reliable and predictable way to trigger our scope during debug of the SGMII / SERDES bus for both hardware and software debug.

The test setup for the oscilloscope screen shots shown below is the FPGA configured as a transparent bridge between an ISP port and an internal LAN port with specific received events from the ISP port being mirrored onto the TAP port with the assertion of the interrupt line for specific events. Oscilloscope probes are applied to the interrupt line and the SGMII TAP port.

Private Island Block Diagram showing SGMII buses
SGMII Block Diagram

Brief overview of popular PHY Interfaces

  • GMII, which is specified by IEEE 802.3-2015 defines a separate 8-bit bus for transmit and receive data plus several signals to convey additional information between the MAC and PHY. GMII is based on MII, which is defined in Clause 22. In addition to the data buses and control signals, GMII requires two 125 MHz bit clocks: GTX_CLK and RX_CLK
  • RGMII, which was defined by HP, Broadcom, and Marvell, reduces the pin count primarily by utilizing separate 4-bit buses for transmit and receive and both edges of the bit clocks.
  • SGMII, which was defined by Cisco, utilizes two pairs of SERDES / LVDS differential buses to carry transmit and receive data at 1.25 Gbps. Differential clocks are defined but are optional and typically not used. Instead, the clocks are recovered from the data on the differential pairs. The data is encoded using an 8B/10B coding scheme, which is specified in clause 36 of 802.3-2015. The effective bit rate is 8 / 10 * 1.25 Gbps = 1.0 Gbps, as you would expect. The out of band information conveyed by the GMII control signals (TX_EN, TX_ER, RX_ER, and RX_DV) are replaced by special code groups (K values). This enables conveying information such as configuration, line state, and carrier events between the MAC and PHY.

SGMII Hardware Signaling

The SGMII specification provides its own specification for LVDS, which is derived from IEEE 1596.3-1996. The parameters provided in the SGMII specification are defined in the IEEE specification. For the purpose of SGMII hardware signaling, these two specifications are sufficient. PHY vendors often refer to this specification rather than providing their own numbers. Note that LVDS in general is an industry standard, and is defined in EIA/TIA-644A. A great resource for LVDS and differential signaling is the TI / National LVDS Owners Manual.

The figure below provides a very simple schematic of LVDS signaling. The concept being conveyed is that the transmitter drives a small current across a 100 ohm load in the receiver in one of two directions to produce either a positive or negative voltage across the receiver (Vod). This small current is superimposed over a common voltage (Vos), typically 1.2V. The industry standard LVDS specifies a 3.5 mA driver current. The SGMII specification implies it is less since |Vod| max is 400 mV. In practice, most SGMII drivers (e.g., PHYs) support the configuration of multiple drive levels. Note that the aforementioned LVDS Owners Manual provides an excellent schematic in Figure 1-1.

Simplified LVDS Signaling
Simplified LVDS Signaling

The next figure shows an oscilloscope screen shot of an SGMII bus using a 4.5 GHz differential probe (RT-ZD40). The probe tips are placed on the two AC coupling caps of the differential SGMII bus. The yellow signal is the SGMII signal, and the blue square wave is generated from the scope's HW CDR math function. A probe meter function is shown in the lower right. This is a feature / function of the probe and shows that the common mode voltage (Vos) is near 1.2V


The next screen shot shows an SGMII eye diagram with 100 ms persistence enabled. As can be seen in the upper right, the trigger is the built-in HW CDR.

SGMII LVDS Eye Diagram

A Look at SGMII Special Code Groups

Clause 36 of 802.3-2015 defines certain 10-bit values as K values to convey non-data (out of band) information between the MAC and PHY. These K values take the place of the GMII control signals and special encodings of the GMII data bus. For Example, /K27.7/ defines a start of packet on the SGMII bus.

Referring to 802.3 Table 36-2 (valid special code-groups) and the screen shot below, we can see that K27.7 is defined as the bit sequence 001001 0111 (lsb first). This screen shot was taken using two single ended probes and utilizes the 8B/10B protocol decode function equipped with our RTO1044. Note that that when the orange waveform is positive, the signal is a 1 and when the blue waveform is positive the signal is a 0.

The '+' after K27.7 indicates that the 10-bit waveform has a currently positive running disparity. Each code, both special and data, can either have a current positive or negative running disparity, and this indicates the difference of the total number of 1's and 0's on the wire. Refer to 802.3 clause 36.2 and Annex 36B for the details on running disparity and its rules.

Special Code K.27
Special Code K.27

802.3 defines ordered sets (Table 36-3) that consist of one or more code groups, each of which starts with a special code group (K value). For example, /I2/ specifies the IDLE2 line state and is encoded by /K28.5/D16.2/. This waveform continually repeats while the line remains in a powered up idle state, and is shown in the figure below.

  • K28.5-: 001111 1010
  • D16.2+: 100100 0101
IDLE 2 Code Group Repeating
IDLE 2 Code Group

Data and Packets on an SGMII Bus

The next figure shows a captured packet preamble on an SGMII bus. Per 802.3 and, An /S/ code (start of packet delimiter, K27.7) replaces the first octet of the preamble followed by the remaining preamble sequence: 0x55 0x55 0x55 0x55 0x55 0x55 0xD5.

Note in the figure below that the special code groups (K) are shown in blue and the data code groups (D) are shown in yellow.

SGMII Preamble
SGMII Start of Packet

Our last screen shot (for now) shows a complete packet captured after being received from an ISP port (PHY). The FPGA's interrupt line is used to trigger the scope synchronously with the reception of the packet on the TAP port. The scope trace highlights the functionality of the 8B/10B protocol decode feature, showing the full decode results in a table and a search result box looking for the K27.7 special code group, which appears on the SGMII bus 60.46 ns after the interrupt. This certainly gives new meaning to the term packet inspection.

SGMII Start of Packet Search
SGMII Start of Packet Search

We'll continue to update this article as we get closer to the release of our Private Island project to the web...

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