Mind Chasers Inc.
Mind Chasers Inc.

MDIO / MMD Concepts for FPGA Open Source Network Processor

An examination and review of Ethernet Management Bus basics with the aid of oscilloscope screen shots



In the context of the Private Island project, the Management Data Input / Output (MDIO) bus is a two wire, out-of-band interface that connects the FPGA-based Ethernet MAC controllers to managed Ethernet PHYs. The purpose of the bus is configure, control, and obtain status of each PHY.

The Ethernet PHY supported by the project is the Texas Instruments DP83867. This device is considered the MDIO Manageable Device (MMD). There is also some support for the Marvell Alaska PHY, but this isn't being actively maintained.

The MDIO interface is specified in 802.3-2015 22.4.4 and is also referred to as the MII Management Interface (MIIM) or Serial Management Interface (SMI). The FPGA, which contains the MAC devices controlling the MDIO, can be referred to as the Station Management Entity (SME).

An extension to MDIO is specified in IEEE 802.3-2015 section 45. This extension provides additional device register space while retaining compatibility with the existing registers. The DP83867 supports this extended interface.

Scope traces are provided in the figures below and show the decode of the MDIO protocol for both read and write cycles. The decode is listed in order below for a total of 32 clock cycles:

  1. Start Phase: 2'b01
  2. Read: 2'b10 or Write: 2'b01
  3. PHY Address: 5 bits
  4. Register Address: 5 bits
  5. Turn Around Phase: 2 bits
  6. Data phase: 16 bits

The MDIO data line is pulled high through a 2.2K resistor, so it returns to a logical high during idle periods. IEEE defines a preamble of a sequence of 1's at least 32 bits long, but clause permits this requirement to be suppressed. Also the TI DP83867 supports preamble suppression.

The PHY address is 5 bits in length, which supports up to 32 PHYs on a single bus. However, Private Island assumes that each PHY is on its own MIDO data line and communicates with each PHY at address 0.

The MDIO clock (MCLK) is shared between the PHYs, and is currently clocked at 10 MHz. The maximum clock rate supported by the PHYs is 25 MHz.

Figure 1 shows a scope trace of an MDIO read cycle performed by the FPGA at register address 0x3 of the DP83867. This is a fixed PHY Identifier Register, and the PHY returns the expected 0xa231. The yellow signal trace is MDC, and the green signal trace is the MDIO data line.

Figure 1. MDIO Read Cycle

Figure 2 shows a scope trace of an MDIO write cycle performed by the FPGA at register address 0xe. This is the DP83867 ADDAR register and is used to support extended addressing.

MDIO Write
Figure 2. MDIO Write Cycle

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