Mind Chasers Inc.

Private Island

Open Source FPGA Project for Network Security, IoT, & Control

  • Have you ever wanted your very own Gigabit Ethernet MAC controller?
  • How about your own customizable Gigabit / 100 Mbit Ethernet switch?
  • Customizable real-time packet filtering, inspection, and mirroring? You got it!
  • Define the metrics you want and stream them to the host of your choice.
  • Route selected streams to a networked host for application processing.
  • Dozens of I/O available for controller applications
  • It's an FPGA and open source, so the applications are endless.
Private Island Block Diagram
FPGA microcontroller PHY PHY PHY debug expansion PWR Internet InternalNetwork Optional System Controller hide show all


We utilize an FPGA in order to build an open, trustworthy, and extensible foundation for packet processing, IoT, and control (e.g., sensors, motors, etc.)

When we filter certain addresses, ports, and / or protocols, we are able to confirm at the hardware layer that this has been accomplished. This is in stark contrast to off-the-shelf SoC implementations, which require developers & users to make assumptions of multiple layers (often opaque) being free of bugs, back doors, and resident spies / spyware.

The open FPGA-based architecture supports numerous, highly parallel functions implemented at Ethernet line rate (125 MHz x 8-bit). Our Darsena development board, which is Arduino form factor and pin out compatible supports Ethernet connectivity via two on-board Ethernet PHYs, ARM micro controller, and the expansion connector.

Project Goals

  • Strive for modularity and simplicity
  • Support multiple FPGAs using both SGMII and RGMII (Lattice ECP5 is first instance)
  • Limited number of dependencies and only when necessary
  • Enable connecting new modules for new applications
  • Architect with ability to use as a stand alone FPGA
  • Visibility from inside and outside
  • Never compromise the integrity of the data
Private Island FPGA Modular Architecture
development block diagram


Architecture and Code Description for the Private Island System
A high level overview of the usage and configuration of the ECP5UM DCU (PCS/SERDES) for Private Island
Documentation of FPGA'S memory and register interface
A summary / concise reference of ECP5UM features and capabilities as applied to the Private Island project
A quick start guide for working with Darsena, the Private Island development platform
Darsena Hardware Design Specification / Reference Manual

Source Code

You can find source on Github: https://github.com/privateisland/privateisland

Our Development Board: Darsena

  • Arduino form-factor compatible with dozens of I/O for expansion and shield support
  • Lattice ECP5UM FPGA (45K LUTs with integrated PCS/SERDES)
  • Two Texas Instruments DP83867 Gigabit PHYs
  • NXP Kinetis K02 Microcontroller with ARM Cortex M4 core
  • Micron SPI ROM

Let us know if you want one.

Darsena, the Private Island Development Board
development block diagram
[ Page last updated: September 28, 2018 ]
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