diff options
Diffstat (limited to 'boards/darsena')
| -rw-r--r-- | boards/darsena/darsena.sty | 203 | ||||
| -rw-r--r-- | boards/darsena/darsena_v02.lpf | 154 |
2 files changed, 357 insertions, 0 deletions
diff --git a/boards/darsena/darsena.sty b/boards/darsena/darsena.sty new file mode 100644 index 0000000..e45715c --- /dev/null +++ b/boards/darsena/darsena.sty @@ -0,0 +1,203 @@ +<?xml version="1.0" encoding="UTF-8"?> +<!DOCTYPE strategy> +<Strategy version="1.0" predefined="0" description="CmdLineArgs" label="Strategy1"> + <Property name="PROP_BD_CmdLineArgs" value="" time="0"/> + <Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/> + <Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/> + <Property name="PROP_BD_EdfInLibPath" value="" time="0"/> + <Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/> + <Property name="PROP_BD_EdfMemPath" value="" time="0"/> + <Property name="PROP_BD_ParSearchPath" value="" time="0"/> + <Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/> + <Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/> + <Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/> + <Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/> + <Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/> + <Property name="PROP_BIT_CreateBitFile" value="True" time="0"/> + <Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/> + <Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/> + <Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/> + <Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/> + <Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/> + <Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/> + <Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/> + <Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/> + <Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/> + <Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/> + <Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/> + <Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/> + <Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/> + <Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/> + <Property name="PROP_BIT_NoHeader" value="False" time="0"/> + <Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/> + <Property name="PROP_BIT_OutFormatBitGen_REF" value="" time="0"/> + <Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/> + <Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/> + <Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/> + <Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/> + <Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/> + <Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/> + <Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/> + <Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/> + <Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/> + <Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/> + <Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/> + <Property name="PROP_LST_AllowDUPMod" value="False" time="0"/> + <Property name="PROP_LST_CarryChain" value="True" time="0"/> + <Property name="PROP_LST_CarryChainLength" value="0" time="0"/> + <Property name="PROP_LST_CmdLineArgs" value="" time="0"/> + <Property name="PROP_LST_DSPStyle" value="DSP" time="0"/> + <Property name="PROP_LST_DSPUtil" value="100" time="0"/> + <Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/> + <Property name="PROP_LST_DisableDistRam" value="False" time="0"/> + <Property name="PROP_LST_EBRUtil" value="100" time="0"/> + <Property name="PROP_LST_EdfFrequency" value="200" time="0"/> + <Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/> + <Property name="PROP_LST_EdfInLibPath" value="" time="0"/> + <Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/> + <Property name="PROP_LST_EdfMemPath" value="" time="0"/> + <Property name="PROP_LST_FIXGATEDCLKS" value="True" time="0"/> + <Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/> + <Property name="PROP_LST_ForceGSRInfer" value="Auto" time="0"/> + <Property name="PROP_LST_IOInsertion" value="True" time="0"/> + <Property name="PROP_LST_InterFileDump" value="False" time="0"/> + <Property name="PROP_LST_LoopLimit" value="1950" time="0"/> + <Property name="PROP_LST_MaxFanout" value="1000" time="0"/> + <Property name="PROP_LST_MuxStyle" value="Auto" time="0"/> + <Property name="PROP_LST_NumCriticalPaths" value="3" time="0"/> + <Property name="PROP_LST_OptimizeGoal" value="Timing" time="0"/> + <Property name="PROP_LST_PropagatConst" value="True" time="0"/> + <Property name="PROP_LST_RAMStyle" value="Auto" time="0"/> + <Property name="PROP_LST_ROMStyle" value="Auto" time="0"/> + <Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/> + <Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/> + <Property name="PROP_LST_ResourceShare" value="True" time="0"/> + <Property name="PROP_LST_UseIOReg" value="Auto" time="0"/> + <Property name="PROP_LST_UseLPF" value="True" time="0"/> + <Property name="PROP_LST_VHDL2008" value="False" time="0"/> + <Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/> + <Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/> + <Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="True" time="0"/> + <Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="True" time="0"/> + <Property name="PROP_MAPSTA_FullName" value="True" time="0"/> + <Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/> + <Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/> + <Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/> + <Property name="PROP_MAPSTA_RptAsynTimLoop" value="True" time="0"/> + <Property name="PROP_MAPSTA_WordCasePaths" value="5" time="0"/> + <Property name="PROP_MAP_GuideFileMapDes" value="" time="0"/> + <Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/> + <Property name="PROP_MAP_MAPIORegister" value="Auto" time="0"/> + <Property name="PROP_MAP_MAPInferGSR" value="False" time="0"/> + <Property name="PROP_MAP_MapModArgs" value="" time="0"/> + <Property name="PROP_MAP_OvermapDevice" value="False" time="0"/> + <Property name="PROP_MAP_PackLogMapDes" value="" time="0"/> + <Property name="PROP_MAP_RegRetiming" value="False" time="0"/> + <Property name="PROP_MAP_SigCrossRef" value="False" time="0"/> + <Property name="PROP_MAP_SymCrossRef" value="False" time="0"/> + <Property name="PROP_MAP_TimingDriven" value="False" time="0"/> + <Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/> + <Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/> + <Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/> + <Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/> + <Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/> + <Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/> + <Property name="PROP_PARSTA_FullName" value="True" time="0"/> + <Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/> + <Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/> + <Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/> + <Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/> + <Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/> + <Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/> + <Property name="PROP_PAR_CrDlyStFileParDes" value="False" time="0"/> + <Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/> + <Property name="PROP_PAR_EffortParDes" value="5" time="0"/> + <Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/> + <Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/> + <Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/> + <Property name="PROP_PAR_PARModArgs" value="" time="0"/> + <Property name="PROP_PAR_ParGuideRepMatch" value="False" time="0"/> + <Property name="PROP_PAR_ParMatchFact" value="" time="0"/> + <Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/> + <Property name="PROP_PAR_ParNCDGuideFile" value="" time="0"/> + <Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/> + <Property name="PROP_PAR_PlcIterParDes" value="2" time="0"/> + <Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/> + <Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/> + <Property name="PROP_PAR_RemoveDir" value="True" time="0"/> + <Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/> + <Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/> + <Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/> + <Property name="PROP_PAR_RoutingCDP" value="Auto" time="0"/> + <Property name="PROP_PAR_RoutingCDR" value="1" time="0"/> + <Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/> + <Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/> + <Property name="PROP_PAR_StopZero" value="False" time="0"/> + <Property name="PROP_PAR_parHold" value="On" time="0"/> + <Property name="PROP_PAR_parPathBased" value="Off" time="0"/> + <Property name="PROP_PRE_CmdLineArgs" value="" time="0"/> + <Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/> + <Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/> + <Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/> + <Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/> + <Property name="PROP_PRE_EdfFullCase" value="False" time="0"/> + <Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/> + <Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/> + <Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/> + <Property name="PROP_PRE_EdfParaCase" value="False" time="0"/> + <Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/> + <Property name="PROP_PRE_EdfResSharing" value="True" time="0"/> + <Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/> + <Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/> + <Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/> + <Property name="PROP_PRE_VSynComArea" value="False" time="0"/> + <Property name="PROP_PRE_VSynCritcal" value="3" time="0"/> + <Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/> + <Property name="PROP_PRE_VSynFreq" value="200" time="0"/> + <Property name="PROP_PRE_VSynGSR" value="False" time="0"/> + <Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/> + <Property name="PROP_PRE_VSynIOPad" value="False" time="0"/> + <Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/> + <Property name="PROP_PRE_VSynOutPref" value="True" time="0"/> + <Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/> + <Property name="PROP_PRE_VSynRetime" value="True" time="0"/> + <Property name="PROP_PRE_VSynTimSum" value="10" time="0"/> + <Property name="PROP_PRE_VSynTransform" value="True" time="0"/> + <Property name="PROP_PRE_VSyninpd" value="0" time="0"/> + <Property name="PROP_PRE_VSynoutd" value="0" time="0"/> + <Property name="PROP_SYN_ClockConversion" value="True" time="0"/> + <Property name="PROP_SYN_CmdLineArgs" value="" time="0"/> + <Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/> + <Property name="PROP_SYN_EdfArea" value="False" time="0"/> + <Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/> + <Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/> + <Property name="PROP_SYN_EdfFanout" value="1000" time="0"/> + <Property name="PROP_SYN_EdfFrequency" value="125" time="0"/> + <Property name="PROP_SYN_EdfGSR" value="False" time="0"/> + <Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/> + <Property name="PROP_SYN_EdfNumCritPath" value="10" time="0"/> + <Property name="PROP_SYN_EdfNumStartEnd" value="20" time="0"/> + <Property name="PROP_SYN_EdfOutNetForm" value="Verilog" time="0"/> + <Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/> + <Property name="PROP_SYN_EdfResSharing" value="True" time="0"/> + <Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/> + <Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/> + <Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/> + <Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/> + <Property name="PROP_SYN_ExportSetting" value="Yes" time="0"/> + <Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/> + <Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/> + <Property name="PROP_SYN_UseLPF" value="True" time="0"/> + <Property name="PROP_SYN_VHDL2008" value="False" time="0"/> + <Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/> + <Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/> + <Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/> + <Property name="PROP_TIM_ModPreSimDes" value="" time="0"/> + <Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/> + <Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/> + <Property name="PROP_TIM_TimSimGenX" value="False" time="0"/> + <Property name="PROP_TIM_TimSimHierSep" value="" time="0"/> + <Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/> + <Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/> + <Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/> +</Strategy> diff --git a/boards/darsena/darsena_v02.lpf b/boards/darsena/darsena_v02.lpf new file mode 100644 index 0000000..236d392 --- /dev/null +++ b/boards/darsena/darsena_v02.lpf @@ -0,0 +1,154 @@ +rvl_alias "pcs_pclk" "pcs_pclk"; +RVL_ALIAS "refclko" "refclko"; +RVL_ALIAS "refclko" "refclko"; +RVL_ALIAS "refclko" "refclko"; +######################################### +# versa.lpf +######################################### +FREQUENCY 140.000000 MHz ; +FREQUENCY NET "pcs_pclk" 125.000000 MHz PAR_ADJ 12.000000 ; +FREQUENCY NET "clk_10_0" 9.700000 MHz ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BANK 0 VCCIO 3.3 V; +BANK 1 VCCIO 3.3 V; +BANK 2 VCCIO 3.3 V; +BANK 3 VCCIO 3.3 V; +BANK 6 VCCIO 3.3 V; +BANK 7 VCCIO 3.3 V; +BANK 8 VCCIO 3.3 V; +######################################### +# I/O Pin Assignemnts: +######################################### +// Micro +LOCATE COMP "rstn" SITE "F1" ;// GSRN ping +LOCATE COMP "i2c_scl" SITE "B1" ; +LOCATE COMP "i2c_sda" SITE "C1" ; +LOCATE COMP "fpga_spics" SITE "H1" ; +LOCATE COMP "fpga_mclk" SITE "H2" ; +LOCATE COMP "fpga_mosi" SITE "G1" ; +LOCATE COMP "fpga_miso" SITE "F2" ; +LOCATE COMP "fpga_int" SITE "E2" ; +LOCATE COMP "uart_txd" SITE "D2" ; +LOCATE COMP "uart_rxd" SITE "E1" ; +LOCATE COMP "led[0]" SITE "P20" ; +LOCATE COMP "led[1]" SITE "M20" ; +LOCATE COMP "led[2]" SITE "M19" ; +// PHY +LOCATE COMP "phy_mdc" SITE "J1" ; +// PHY0 +LOCATE COMP "phy0_resetn" SITE "K2" ; +LOCATE COMP "phy0_mdio" SITE "L2" ; +LOCATE COMP "phy0_intn" SITE "K1" ; +LOCATE COMP "phy0_gpio[0]" SITE "M1" ; +LOCATE COMP "phy0_gpio[1]" SITE "L1" ; +// PHY1 +LOCATE COMP "phy1_resetn" SITE "N20" ; +LOCATE COMP "phy1_mdio" SITE "U20" ; +LOCATE COMP "phy1_intn" SITE "U19" ; +LOCATE COMP "phy1_gpio[0]" SITE "R20" ; +LOCATE COMP "phy1_gpio[1]" SITE "P19" ; + +// Arduino Expansion +LOCATE COMP "ard_sda" SITE "A19" ; +LOCATE COMP "ard_scl" SITE "B20" ; +LOCATE COMP "ard_rxd1" SITE "A18" ; +LOCATE COMP "ard_rxd2" SITE "A14" ; +LOCATE COMP "ard_rxd3" SITE "A7" ; +LOCATE COMP "ard_txd1" SITE "A17" ; +LOCATE COMP "ard_txd2" SITE "A10" ; +LOCATE COMP "ard_txd3" SITE "A6" ; +LOCATE COMP "pe0" SITE "A5" ; +LOCATE COMP "pe1" SITE "B5" ; +LOCATE COMP "pe3" SITE "B3" ; +LOCATE COMP "pe4" SITE "A4" ; +LOCATE COMP "pe5" SITE "B4" ; +LOCATE COMP "pg5" SITE "A3" ; +LOCATE COMP "ph3" SITE "A2" ; +LOCATE COMP "ph4" SITE "B2" ; + +// PHY2 + +LOCATE COMP "phy2_mdc" SITE "C20" ; +LOCATE COMP "phy2_mdio" SITE "D19" ; +LOCATE COMP "phy2_resetn" SITE "D20" ; + +//LOCATE COMP "pa[0]" SITE "C20" ; +//LOCATE COMP "pa[1]" SITE "D19" ; +//LOCATE COMP "pa[2]" SITE "D20" ; +LOCATE COMP "pa[3]" SITE "E19" ; +LOCATE COMP "pa[4]" SITE "E20" ; +LOCATE COMP "pa[5]" SITE "F19" ; +LOCATE COMP "pa[6]" SITE "F20" ; +LOCATE COMP "pa[7]" SITE "G20" ; +LOCATE COMP "pa[8]" SITE "G19" ; +LOCATE COMP "pa[9]" SITE "H20" ; + + +// V02 +LOCATE COMP "ftdi_tck_txd" SITE "R1" ; +LOCATE COMP "ftdi_tdi_rxd" SITE "T1" ; +LOCATE COMP "fpga_jtag_e" SITE "V1" ; +LOCATE COMP "fpga_gpio" SITE "N1" ; +IOBUF PORT "uart_txd" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "uart_rxd" IO_TYPE=LVCMOS33 ; +IOBUF PORT "i2c_scl" IO_TYPE=LVCMOS33 ; +IOBUF PORT "i2c_sda" IO_TYPE=LVCMOS33 OPENDRAIN=ON DRIVE=16 SLEWRATE=FAST ; +SYSCONFIG CONFIG_IOVOLTAGE=3.3 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=ENABLE SLAVE_PARALLEL_PORT=DISABLE CONFIG_MODE=JTAG BACKGROUND_RECONFIG=OFF ; +VOLTAGE 1.045 V; +USERCODE BIN "00000000000000000000000000000000" ; +BLOCK JTAGPATHS ; +IOBUF PORT "rstn" IO_TYPE=LVCMOS33 ; +IOBUF PORT "phy2_mdc" IO_TYPE=LVCMOS33 ; +IOBUF PORT "fpga_int" IO_TYPE=LVCMOS33 ; +IOBUF PORT "phy2_resetn" IO_TYPE=LVCMOS33 ; +IOBUF PORT "phy0_resetn" IO_TYPE=LVCMOS33 ; +IOBUF PORT "phy1_resetn" IO_TYPE=LVCMOS33 ; +IOBUF PORT "led[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "led[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "led[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "phy2_mdio" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "phy0_mdio" IO_TYPE=LVCMOS33 PULLMODE=UP OPENDRAIN=OFF ; +IOBUF PORT "phy1_mdio" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "ard_sda" IO_TYPE=LVCMOS33 ; +IOBUF PORT "ard_scl" IO_TYPE=LVCMOS33 ; +IOBUF PORT "ard_rxd1" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "ard_rxd2" IO_TYPE=LVCMOS33 ; +IOBUF PORT "ard_rxd3" IO_TYPE=LVCMOS33 ; +IOBUF PORT "ard_scl" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "ard_sda" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "ard_txd1" IO_TYPE=LVCMOS33 ; +IOBUF PORT "ard_txd2" IO_TYPE=LVCMOS33 ; +IOBUF PORT "ard_txd3" IO_TYPE=LVCMOS33 ; +IOBUF PORT "phy_mdc" IO_TYPE=LVCMOS33 ; +IOBUF PORT "fpga_miso" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "pe0" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pe1" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pe3" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pe4" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pe5" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pg5" IO_TYPE=LVCMOS33 ; +IOBUF PORT "ph3" IO_TYPE=LVCMOS33 ; +IOBUF PORT "ph4" IO_TYPE=LVCMOS33 ; + +//IOBUF PORT "pa[0]" IO_TYPE=LVCMOS33 ; +//IOBUF PORT "pa[1]" IO_TYPE=LVCMOS33 ; +//IOBUF PORT "pa[2]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pa[3]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pa[4]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pa[5]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pa[6]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pa[7]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pa[8]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pa[9]" IO_TYPE=LVCMOS33 ; + +# V02 +IOBUF PORT "ftdi_tck_txd" IO_TYPE=LVCMOS33 ; +IOBUF PORT "ftdi_tdi_rxd" IO_TYPE=LVCMOS33 ; +IOBUF PORT "fpga_jtag_e" IO_TYPE=LVCMOS33 ; +IOBUF PORT "fpga_gpio" IO_TYPE=LVCMOS33 ; +IOBUF PORT "phy1_intn" IO_TYPE=LVCMOS33 ; +IOBUF PORT "phy0_intn" IO_TYPE=LVCMOS33 ; +IOBUF PORT "fpga_mclk" IO_TYPE=LVCMOS33 ; +IOBUF PORT "fpga_spics" IO_TYPE=LVCMOS33 ; +IOBUF PORT "fpga_mosi" IO_TYPE=LVCMOS33 ; |
