diff options
Diffstat (limited to 'boards/darsena/darsena_v02.lpf')
| -rw-r--r-- | boards/darsena/darsena_v02.lpf | 154 |
1 files changed, 154 insertions, 0 deletions
diff --git a/boards/darsena/darsena_v02.lpf b/boards/darsena/darsena_v02.lpf new file mode 100644 index 0000000..236d392 --- /dev/null +++ b/boards/darsena/darsena_v02.lpf @@ -0,0 +1,154 @@ +rvl_alias "pcs_pclk" "pcs_pclk"; +RVL_ALIAS "refclko" "refclko"; +RVL_ALIAS "refclko" "refclko"; +RVL_ALIAS "refclko" "refclko"; +######################################### +# versa.lpf +######################################### +FREQUENCY 140.000000 MHz ; +FREQUENCY NET "pcs_pclk" 125.000000 MHz PAR_ADJ 12.000000 ; +FREQUENCY NET "clk_10_0" 9.700000 MHz ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BANK 0 VCCIO 3.3 V; +BANK 1 VCCIO 3.3 V; +BANK 2 VCCIO 3.3 V; +BANK 3 VCCIO 3.3 V; +BANK 6 VCCIO 3.3 V; +BANK 7 VCCIO 3.3 V; +BANK 8 VCCIO 3.3 V; +######################################### +# I/O Pin Assignemnts: +######################################### +// Micro +LOCATE COMP "rstn" SITE "F1" ;// GSRN ping +LOCATE COMP "i2c_scl" SITE "B1" ; +LOCATE COMP "i2c_sda" SITE "C1" ; +LOCATE COMP "fpga_spics" SITE "H1" ; +LOCATE COMP "fpga_mclk" SITE "H2" ; +LOCATE COMP "fpga_mosi" SITE "G1" ; +LOCATE COMP "fpga_miso" SITE "F2" ; +LOCATE COMP "fpga_int" SITE "E2" ; +LOCATE COMP "uart_txd" SITE "D2" ; +LOCATE COMP "uart_rxd" SITE "E1" ; +LOCATE COMP "led[0]" SITE "P20" ; +LOCATE COMP "led[1]" SITE "M20" ; +LOCATE COMP "led[2]" SITE "M19" ; +// PHY +LOCATE COMP "phy_mdc" SITE "J1" ; +// PHY0 +LOCATE COMP "phy0_resetn" SITE "K2" ; +LOCATE COMP "phy0_mdio" SITE "L2" ; +LOCATE COMP "phy0_intn" SITE "K1" ; +LOCATE COMP "phy0_gpio[0]" SITE "M1" ; +LOCATE COMP "phy0_gpio[1]" SITE "L1" ; +// PHY1 +LOCATE COMP "phy1_resetn" SITE "N20" ; +LOCATE COMP "phy1_mdio" SITE "U20" ; +LOCATE COMP "phy1_intn" SITE "U19" ; +LOCATE COMP "phy1_gpio[0]" SITE "R20" ; +LOCATE COMP "phy1_gpio[1]" SITE "P19" ; + +// Arduino Expansion +LOCATE COMP "ard_sda" SITE "A19" ; +LOCATE COMP "ard_scl" SITE "B20" ; +LOCATE COMP "ard_rxd1" SITE "A18" ; +LOCATE COMP "ard_rxd2" SITE "A14" ; +LOCATE COMP "ard_rxd3" SITE "A7" ; +LOCATE COMP "ard_txd1" SITE "A17" ; +LOCATE COMP "ard_txd2" SITE "A10" ; +LOCATE COMP "ard_txd3" SITE "A6" ; +LOCATE COMP "pe0" SITE "A5" ; +LOCATE COMP "pe1" SITE "B5" ; +LOCATE COMP "pe3" SITE "B3" ; +LOCATE COMP "pe4" SITE "A4" ; +LOCATE COMP "pe5" SITE "B4" ; +LOCATE COMP "pg5" SITE "A3" ; +LOCATE COMP "ph3" SITE "A2" ; +LOCATE COMP "ph4" SITE "B2" ; + +// PHY2 + +LOCATE COMP "phy2_mdc" SITE "C20" ; +LOCATE COMP "phy2_mdio" SITE "D19" ; +LOCATE COMP "phy2_resetn" SITE "D20" ; + +//LOCATE COMP "pa[0]" SITE "C20" ; +//LOCATE COMP "pa[1]" SITE "D19" ; +//LOCATE COMP "pa[2]" SITE "D20" ; +LOCATE COMP "pa[3]" SITE "E19" ; +LOCATE COMP "pa[4]" SITE "E20" ; +LOCATE COMP "pa[5]" SITE "F19" ; +LOCATE COMP "pa[6]" SITE "F20" ; +LOCATE COMP "pa[7]" SITE "G20" ; +LOCATE COMP "pa[8]" SITE "G19" ; +LOCATE COMP "pa[9]" SITE "H20" ; + + +// V02 +LOCATE COMP "ftdi_tck_txd" SITE "R1" ; +LOCATE COMP "ftdi_tdi_rxd" SITE "T1" ; +LOCATE COMP "fpga_jtag_e" SITE "V1" ; +LOCATE COMP "fpga_gpio" SITE "N1" ; +IOBUF PORT "uart_txd" PULLMODE=UP IO_TYPE=LVCMOS33 ; +IOBUF PORT "uart_rxd" IO_TYPE=LVCMOS33 ; +IOBUF PORT "i2c_scl" IO_TYPE=LVCMOS33 ; +IOBUF PORT "i2c_sda" IO_TYPE=LVCMOS33 OPENDRAIN=ON DRIVE=16 SLEWRATE=FAST ; +SYSCONFIG CONFIG_IOVOLTAGE=3.3 SLAVE_SPI_PORT=DISABLE MASTER_SPI_PORT=ENABLE SLAVE_PARALLEL_PORT=DISABLE CONFIG_MODE=JTAG BACKGROUND_RECONFIG=OFF ; +VOLTAGE 1.045 V; +USERCODE BIN "00000000000000000000000000000000" ; +BLOCK JTAGPATHS ; +IOBUF PORT "rstn" IO_TYPE=LVCMOS33 ; +IOBUF PORT "phy2_mdc" IO_TYPE=LVCMOS33 ; +IOBUF PORT "fpga_int" IO_TYPE=LVCMOS33 ; +IOBUF PORT "phy2_resetn" IO_TYPE=LVCMOS33 ; +IOBUF PORT "phy0_resetn" IO_TYPE=LVCMOS33 ; +IOBUF PORT "phy1_resetn" IO_TYPE=LVCMOS33 ; +IOBUF PORT "led[2]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "led[1]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "led[0]" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "phy2_mdio" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "phy0_mdio" IO_TYPE=LVCMOS33 PULLMODE=UP OPENDRAIN=OFF ; +IOBUF PORT "phy1_mdio" IO_TYPE=LVCMOS33 PULLMODE=UP ; +IOBUF PORT "ard_sda" IO_TYPE=LVCMOS33 ; +IOBUF PORT "ard_scl" IO_TYPE=LVCMOS33 ; +IOBUF PORT "ard_rxd1" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "ard_rxd2" IO_TYPE=LVCMOS33 ; +IOBUF PORT "ard_rxd3" IO_TYPE=LVCMOS33 ; +IOBUF PORT "ard_scl" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "ard_sda" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "ard_txd1" IO_TYPE=LVCMOS33 ; +IOBUF PORT "ard_txd2" IO_TYPE=LVCMOS33 ; +IOBUF PORT "ard_txd3" IO_TYPE=LVCMOS33 ; +IOBUF PORT "phy_mdc" IO_TYPE=LVCMOS33 ; +IOBUF PORT "fpga_miso" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "pe0" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pe1" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pe3" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pe4" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pe5" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pg5" IO_TYPE=LVCMOS33 ; +IOBUF PORT "ph3" IO_TYPE=LVCMOS33 ; +IOBUF PORT "ph4" IO_TYPE=LVCMOS33 ; + +//IOBUF PORT "pa[0]" IO_TYPE=LVCMOS33 ; +//IOBUF PORT "pa[1]" IO_TYPE=LVCMOS33 ; +//IOBUF PORT "pa[2]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pa[3]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pa[4]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pa[5]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pa[6]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pa[7]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pa[8]" IO_TYPE=LVCMOS33 ; +IOBUF PORT "pa[9]" IO_TYPE=LVCMOS33 ; + +# V02 +IOBUF PORT "ftdi_tck_txd" IO_TYPE=LVCMOS33 ; +IOBUF PORT "ftdi_tdi_rxd" IO_TYPE=LVCMOS33 ; +IOBUF PORT "fpga_jtag_e" IO_TYPE=LVCMOS33 ; +IOBUF PORT "fpga_gpio" IO_TYPE=LVCMOS33 ; +IOBUF PORT "phy1_intn" IO_TYPE=LVCMOS33 ; +IOBUF PORT "phy0_intn" IO_TYPE=LVCMOS33 ; +IOBUF PORT "fpga_mclk" IO_TYPE=LVCMOS33 ; +IOBUF PORT "fpga_spics" IO_TYPE=LVCMOS33 ; +IOBUF PORT "fpga_mosi" IO_TYPE=LVCMOS33 ; |