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-rw-r--r--manufacturer/lattice/ecp5um/privateisland.ldf5
1 files changed, 3 insertions, 2 deletions
diff --git a/manufacturer/lattice/ecp5um/privateisland.ldf b/manufacturer/lattice/ecp5um/privateisland.ldf
index 1968d1b..ede192c 100644
--- a/manufacturer/lattice/ecp5um/privateisland.ldf
+++ b/manufacturer/lattice/ecp5um/privateisland.ldf
@@ -6,12 +6,13 @@
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="darsena">
<Options>
<Option name="HDL type" value="Verilog"/>
- <Option name="include path" value="remote_files/include"/>
+ <Option name="def_top" value="top"/>
+ <Option name="include path" value="../../../source"/>
<Option name="lib" value="work"/>
<Option name="top" value="top"/>
</Options>
<Source name="source/top.v" type="Verilog" type_short="Verilog">
- <Options/>
+ <Options top_module="top"/>
</Source>
<Source name="../../../source/bin_to_ascii.v" type="Verilog" type_short="Verilog">
<Options/>