3 files changed, 53 insertions, 0 deletions
diff --git a/clarity/pcs/refclk0/refclk0.fdc b/clarity/pcs/refclk0/refclk0.fdc
new file mode 100644
index 0000000..6fbcac9
--- /dev/null
+++ b/clarity/pcs/refclk0/refclk0.fdc
@@ -0,0 +1,2 @@
+###==== Start Configuration
+
diff --git a/clarity/pcs/refclk0/refclk0.lpc b/clarity/pcs/refclk0/refclk0.lpc
new file mode 100644
index 0000000..4e2184e
--- /dev/null
+++ b/clarity/pcs/refclk0/refclk0.lpc
@@ -0,0 +1,31 @@
+[Device]
+Family=ecp5um
+OperatingCondition=COM
+Package=CABGA381
+PartName=LFE5UM-45F-8BG381C
+PartType=LFE5UM-45F
+SpeedGrade=8
+Status=P
+[IP]
+CoreName=EXTREF
+CoreRevision=1.1
+CoreStatus=Demo
+CoreType=LPM
+Date=10/17/2017
+ModuleName=refclk0
+ParameterFileVersion=1.0
+SourceFormat=verilog
+Time=18:21:09
+VendorName=Lattice Semiconductor Corporation
+[Parameters]
+Destination=Synplicity
+EDIF=1
+EXTREFDCBIAS=Disabled
+EXTREFTERMRES=50 ohms
+Expression=BusA(0 to 7)
+IO=0
+Order=Big Endian [MSB:LSB]
+VHDL=0
+Verilog=1
+[SYSTEMPNR]
+EXTREF=DCU0
diff --git a/clarity/pcs/refclk0/refclk0.v b/clarity/pcs/refclk0/refclk0.v
new file mode 100644
index 0000000..7fe46e2
--- /dev/null
+++ b/clarity/pcs/refclk0/refclk0.v
@@ -0,0 +1,20 @@
+// Verilog netlist produced by program ASBGen: Ports rev. 2.30, Attr. rev. 2.65
+// Netlist written on Tue Oct 17 18:22:54 2017
+//
+// Verilog Description of module refclk0
+//
+
+`timescale 1ns/1ps
+module refclk0 (refclkp, refclkn, refclko);
+    input refclkp;
+    input refclkn;
+    output refclko;
+    
+    
+    EXTREFB EXTREF0_inst (.REFCLKP(refclkp), .REFCLKN(refclkn), .REFCLKO(refclko)) /* synthesis LOC=EXTREF0 */ ;
+    defparam EXTREF0_inst.REFCK_PWDNB = "0b1";
+    defparam EXTREF0_inst.REFCK_RTERM = "0b1";
+    defparam EXTREF0_inst.REFCK_DCBIAS_EN = "0b0";
+    
+endmodule
+