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Diffstat (limited to 'clarity/pcs/refclk0/refclk0.v')
| -rw-r--r-- | clarity/pcs/refclk0/refclk0.v | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/clarity/pcs/refclk0/refclk0.v b/clarity/pcs/refclk0/refclk0.v new file mode 100644 index 0000000..7fe46e2 --- /dev/null +++ b/clarity/pcs/refclk0/refclk0.v @@ -0,0 +1,20 @@ +// Verilog netlist produced by program ASBGen: Ports rev. 2.30, Attr. rev. 2.65 +// Netlist written on Tue Oct 17 18:22:54 2017 +// +// Verilog Description of module refclk0 +// + +`timescale 1ns/1ps +module refclk0 (refclkp, refclkn, refclko); + input refclkp; + input refclkn; + output refclko; + + + EXTREFB EXTREF0_inst (.REFCLKP(refclkp), .REFCLKN(refclkn), .REFCLKO(refclko)) /* synthesis LOC=EXTREF0 */ ; + defparam EXTREF0_inst.REFCK_PWDNB = "0b1"; + defparam EXTREF0_inst.REFCK_RTERM = "0b1"; + defparam EXTREF0_inst.REFCK_DCBIAS_EN = "0b0"; + +endmodule + |