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authormindchasers <privateisland@mindchasers.com>2020-11-16 13:59:15 -0500
committermindchasers <privateisland@mindchasers.com>2020-11-16 13:59:15 -0500
commitda76ee103bf89c28c7d6027371e4a420ada41932 (patch)
treeaea0c2c1cdd61cbeebf028170943d0a08132b05a /testbenches
parent3e6999c467908663d2539483de82057f587ffbb2 (diff)
project: rename sim folder, update README
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-System Verilog Test Benches
-
-Will be added soon

Highly Recommended Verilog Books