diff options
| author | mindchasers <privateisland@mindchasers.com> | 2020-11-15 23:42:42 -0500 |
|---|---|---|
| committer | mindchasers <privateisland@mindchasers.com> | 2020-11-15 23:42:42 -0500 |
| commit | 3e6999c467908663d2539483de82057f587ffbb2 (patch) | |
| tree | ec10f61e27b36eee8a37f46feb45601243174fc4 /clarity/pcs/sgmii2/sgmii2.lpc | |
| parent | 8e8ce59d8f74e1d3de89e5b2b720039ed32a9768 (diff) | |
ecp5um project: restructure so we can add more devices
Diffstat (limited to 'clarity/pcs/sgmii2/sgmii2.lpc')
| -rw-r--r-- | clarity/pcs/sgmii2/sgmii2.lpc | 97 |
1 files changed, 0 insertions, 97 deletions
diff --git a/clarity/pcs/sgmii2/sgmii2.lpc b/clarity/pcs/sgmii2/sgmii2.lpc deleted file mode 100644 index 291651a..0000000 --- a/clarity/pcs/sgmii2/sgmii2.lpc +++ /dev/null @@ -1,97 +0,0 @@ -[Device] -Family=ecp5um -OperatingCondition=COM -Package=CABGA381 -PartName=LFE5UM-45F-8BG381C -PartType=LFE5UM-45F -SpeedGrade=8 -Status=P -[IP] -CoreName=PCS -CoreRevision=8.2 -CoreStatus=Demo -CoreType=LPM -Date=03/21/2020 -ModuleName=sgmii2 -ParameterFileVersion=1.0 -SourceFormat=verilog -Time=21:49:06 -VendorName=Lattice Semiconductor Corporation -[Parameters] -;ACHARA=0 00H -;ACHARB=0 00H -;ACHARM=0 00H -;RXMCAENABLE=Disabled -CDRLOLACTION=Full Recalibration -CDRLOLRANGE=0 -CDR_MAX_RATE=1.25 -CDR_MULT=10X -CDR_REF_RATE=125.0000 -CH_MODE=Rx and Tx -Destination=Synplicity -EDIF=1 -Expression=BusA(0 to 7) -IO=0 -IO_TYPE=GbE -LEQ=0 -LOOPBACK=Disabled -LOSPORT=Enabled -NUM_CHS=1 -Order=Big Endian [MSB:LSB] -PPORT_RX_RDY=Disabled -PPORT_TX_RDY=Disabled -PROTOCOL=GbE -PWAIT_RX_RDY=3000 -PWAIT_TX_RDY=3000 -RCSRC=Disabled -REFCLK_RATE=125.0000 -RSTSEQSEL=Disabled -RX8B10B=Enabled -RXCOMMAA=1010000011 -RXCOMMAB=0101111100 -RXCOMMAM=1111111111 -RXCOUPLING=AC -RXCTC=Enabled -RXCTCBYTEN=0 00H -RXCTCBYTEN1=0 00H -RXCTCBYTEN2=1 BCH -RXCTCBYTEN3=0 50H -RXCTCMATCHPATTERN=M2-S2 -RXDIFFTERM=50 ohms -RXFIFO_ENABLE=Enabled -RXINVPOL=Non-invert -RXLDR=Off -RXLOSTHRESHOLD=4 -RXLSM=Enabled -RXSC=K28P5 -RXWA=Barrel Shift -RX_DATA_WIDTH=8/10-Bit -RX_FICLK_RATE=125.0000 -RX_LINE_RATE=1.2500 -RX_RATE_DIV=Full Rate -SCIPORT=Enabled -SOFTLOL=Enabled -TX8B10B=Enabled -TXAMPLITUDE=400 -TXDEPOST=Disabled -TXDEPRE=Disabled -TXDIFFTERM=50 ohms -TXFIFO_ENABLE=Enabled -TXINVPOL=Non-invert -TXLDR=Off -TXPLLLOLTHRESHOLD=0 -TXPLLMULT=10X -TX_DATA_WIDTH=8/10-Bit -TX_FICLK_RATE=125.0000 -TX_LINE_RATE=1.2500 -TX_MAX_RATE=1.25 -TX_RATE_DIV=Full Rate -VHDL=0 -Verilog=1 -[FilesGenerated] -sgmii2.pp=pp -sgmii2.sym=sym -sgmii2.tft=tft -sgmii2.txt=pcs_module -[SYSTEMPNR] -LN0=DCU1_CH0 |
