ecp5um project: restructure so we can add more devices

31 files changed, 31 insertions, 263 deletions

diff --git a/clarity/README b/clarity/README
deleted file mode 100644
index 9d47733..0000000
--- a/clarity/README
+++ /dev/null
@@ -1,3 +0,0 @@
-This folder is generated by Clarity with some hand tweaks
-
-See https://mindchasers.com/dev/fpga-pcs-arch and forum posts related to PCS
diff --git a/boards/darsena/darsena.sty b/manufacturer/device/ecp5um/boards/darsena/darsena.sty
index b9a247b..b9a247b 100644
--- a/boards/darsena/darsena.sty
+++ b/manufacturer/device/ecp5um/boards/darsena/darsena.sty
diff --git a/boards/darsena/darsena_v02.lpf b/manufacturer/device/ecp5um/boards/darsena/darsena_v02.lpf
index 98c999b..98c999b 100644
--- a/boards/darsena/darsena_v02.lpf
+++ b/manufacturer/device/ecp5um/boards/darsena/darsena_v02.lpf
diff --git a/boards/darsena/labs.rva b/manufacturer/device/ecp5um/boards/darsena/labs.rva
index 92b5eb8..92b5eb8 100644
--- a/boards/darsena/labs.rva
+++ b/manufacturer/device/ecp5um/boards/darsena/labs.rva
diff --git a/boards/darsena/labs.rvl b/manufacturer/device/ecp5um/boards/darsena/labs.rvl
index ad00f8e..ad00f8e 100644
--- a/boards/darsena/labs.rvl
+++ b/manufacturer/device/ecp5um/boards/darsena/labs.rvl
diff --git a/boards/darsena/labs.rvs b/manufacturer/device/ecp5um/boards/darsena/labs.rvs
index 67553e6..67553e6 100644
--- a/boards/darsena/labs.rvs
+++ b/manufacturer/device/ecp5um/boards/darsena/labs.rvs
diff --git a/clarity/pcs/pcs.sbx b/manufacturer/device/ecp5um/clarity/pcs/pcs.sbx
index d36bdc1..d36bdc1 100644
--- a/clarity/pcs/pcs.sbx
+++ b/manufacturer/device/ecp5um/clarity/pcs/pcs.sbx
diff --git a/clarity/pcs/pcs.v b/manufacturer/device/ecp5um/clarity/pcs/pcs.v
index 8acba47..8acba47 100644
--- a/clarity/pcs/pcs.v
+++ b/manufacturer/device/ecp5um/clarity/pcs/pcs.v
diff --git a/clarity/pcs/pcs_tmpl.v b/manufacturer/device/ecp5um/clarity/pcs/pcs_tmpl.v
index 2250f1a..2250f1a 100644
--- a/clarity/pcs/pcs_tmpl.v
+++ b/manufacturer/device/ecp5um/clarity/pcs/pcs_tmpl.v
diff --git a/clarity/pcs/refclk0/refclk0.fdc b/manufacturer/device/ecp5um/clarity/pcs/refclk0/refclk0.fdc
index 6fbcac9..6fbcac9 100644
--- a/clarity/pcs/refclk0/refclk0.fdc
+++ b/manufacturer/device/ecp5um/clarity/pcs/refclk0/refclk0.fdc
diff --git a/clarity/pcs/refclk0/refclk0.lpc b/manufacturer/device/ecp5um/clarity/pcs/refclk0/refclk0.lpc
index 1894b2d..1894b2d 100644
--- a/clarity/pcs/refclk0/refclk0.lpc
+++ b/manufacturer/device/ecp5um/clarity/pcs/refclk0/refclk0.lpc
diff --git a/clarity/pcs/refclk0/refclk0.v b/manufacturer/device/ecp5um/clarity/pcs/refclk0/refclk0.v
index edeb81f..edeb81f 100644
--- a/clarity/pcs/refclk0/refclk0.v
+++ b/manufacturer/device/ecp5um/clarity/pcs/refclk0/refclk0.v
diff --git a/clarity/pcs/sgmii0/sgmii0.fdc b/manufacturer/device/ecp5um/clarity/pcs/sgmii0/sgmii0.fdc
index 6fbcac9..6fbcac9 100644
--- a/clarity/pcs/sgmii0/sgmii0.fdc
+++ b/manufacturer/device/ecp5um/clarity/pcs/sgmii0/sgmii0.fdc
diff --git a/clarity/pcs/sgmii0/sgmii0.lpc b/manufacturer/device/ecp5um/clarity/pcs/sgmii0/sgmii0.lpc
index 5c06b05..5c06b05 100644
--- a/clarity/pcs/sgmii0/sgmii0.lpc
+++ b/manufacturer/device/ecp5um/clarity/pcs/sgmii0/sgmii0.lpc
diff --git a/clarity/pcs/sgmii0/sgmii0.v b/manufacturer/device/ecp5um/clarity/pcs/sgmii0/sgmii0.v
index 8cbf73e..8cbf73e 100644
--- a/clarity/pcs/sgmii0/sgmii0.v
+++ b/manufacturer/device/ecp5um/clarity/pcs/sgmii0/sgmii0.v
diff --git a/clarity/pcs/sgmii0/sgmii0_softlogic.v b/manufacturer/device/ecp5um/clarity/pcs/sgmii0/sgmii0_softlogic.v
index 74972ff..74972ff 100644
--- a/clarity/pcs/sgmii0/sgmii0_softlogic.v
+++ b/manufacturer/device/ecp5um/clarity/pcs/sgmii0/sgmii0_softlogic.v
diff --git a/clarity/pcs/sgmii1/sgmii1.fdc b/manufacturer/device/ecp5um/clarity/pcs/sgmii1/sgmii1.fdc
index 6fbcac9..6fbcac9 100644
--- a/clarity/pcs/sgmii1/sgmii1.fdc
+++ b/manufacturer/device/ecp5um/clarity/pcs/sgmii1/sgmii1.fdc
diff --git a/clarity/pcs/sgmii1/sgmii1.lpc b/manufacturer/device/ecp5um/clarity/pcs/sgmii1/sgmii1.lpc
index 007e691..007e691 100644
--- a/clarity/pcs/sgmii1/sgmii1.lpc
+++ b/manufacturer/device/ecp5um/clarity/pcs/sgmii1/sgmii1.lpc
diff --git a/clarity/pcs/sgmii1/sgmii1.v b/manufacturer/device/ecp5um/clarity/pcs/sgmii1/sgmii1.v
index dbb36df..dbb36df 100644
--- a/clarity/pcs/sgmii1/sgmii1.v
+++ b/manufacturer/device/ecp5um/clarity/pcs/sgmii1/sgmii1.v
diff --git a/clarity/pcs/sgmii2/sgmii2.fdc b/manufacturer/device/ecp5um/clarity/pcs/sgmii2/sgmii2.fdc
index 6fbcac9..6fbcac9 100644
--- a/clarity/pcs/sgmii2/sgmii2.fdc
+++ b/manufacturer/device/ecp5um/clarity/pcs/sgmii2/sgmii2.fdc
diff --git a/clarity/pcs/sgmii2/sgmii2.lpc b/manufacturer/device/ecp5um/clarity/pcs/sgmii2/sgmii2.lpc
index 291651a..291651a 100644
--- a/clarity/pcs/sgmii2/sgmii2.lpc
+++ b/manufacturer/device/ecp5um/clarity/pcs/sgmii2/sgmii2.lpc
diff --git a/clarity/pcs/sgmii2/sgmii2.v b/manufacturer/device/ecp5um/clarity/pcs/sgmii2/sgmii2.v
index acc9184..acc9184 100644
--- a/clarity/pcs/sgmii2/sgmii2.v
+++ b/manufacturer/device/ecp5um/clarity/pcs/sgmii2/sgmii2.v
diff --git a/clarity/pcs/sgmii2/sgmii2_softlogic.v b/manufacturer/device/ecp5um/clarity/pcs/sgmii2/sgmii2_softlogic.v
index 5346253..5346253 100644
--- a/clarity/pcs/sgmii2/sgmii2_softlogic.v
+++ b/manufacturer/device/ecp5um/clarity/pcs/sgmii2/sgmii2_softlogic.v
diff --git a/clarity/pcs/sgmii3/sgmii3.fdc b/manufacturer/device/ecp5um/clarity/pcs/sgmii3/sgmii3.fdc
index 6fbcac9..6fbcac9 100644
--- a/clarity/pcs/sgmii3/sgmii3.fdc
+++ b/manufacturer/device/ecp5um/clarity/pcs/sgmii3/sgmii3.fdc
diff --git a/clarity/pcs/sgmii3/sgmii3.lpc b/manufacturer/device/ecp5um/clarity/pcs/sgmii3/sgmii3.lpc
index 53e7c43..53e7c43 100644
--- a/clarity/pcs/sgmii3/sgmii3.lpc
+++ b/manufacturer/device/ecp5um/clarity/pcs/sgmii3/sgmii3.lpc
diff --git a/clarity/pcs/sgmii3/sgmii3.v b/manufacturer/device/ecp5um/clarity/pcs/sgmii3/sgmii3.v
index fc55bf8..fc55bf8 100644
--- a/clarity/pcs/sgmii3/sgmii3.v
+++ b/manufacturer/device/ecp5um/clarity/pcs/sgmii3/sgmii3.v
diff --git a/privateisland.ldf b/manufacturer/device/ecp5um/privateisland.ldf
index b6a15d3..b167227 100644
--- a/privateisland.ldf
+++ b/manufacturer/device/ecp5um/privateisland.ldf
@@ -6,91 +6,93 @@
     <Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="darsena">
         <Options>
             <Option name="HDL type" value="Verilog"/>
-            <Option name="def_top" value="top"/>
             <Option name="include path" value="remote_files/include"/>
             <Option name="lib" value="work"/>
             <Option name="top" value="top"/>
         </Options>
-        <Source name="source/bin_to_ascii.v" type="Verilog" type_short="Verilog">
+        <Source name="../../../source/top.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
-        <Source name="source/cam.v" type="Verilog" type_short="Verilog">
+        <Source name="../../../source/bin_to_ascii.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
-        <Source name="source/clk_gen.v" type="Verilog" type_short="Verilog">
+        <Source name="../../../source/cam.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
-        <Source name="source/controller.v" type="Verilog" type_short="Verilog">
+        <Source name="../../../source/clk_gen.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
-        <Source name="source/definitions.v" type="Verilog" type_short="Verilog">
+        <Source name="../../../source/controller.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
-        <Source name="source/dpram.v" type="Verilog" type_short="Verilog">
+        <Source name="../../../source/definitions.v" type="Verilog" type_short="Verilog" excluded="TRUE">
             <Options/>
         </Source>
-        <Source name="source/drop_fifo.v" type="Verilog" type_short="Verilog">
+        <Source name="../../../source/dpram.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
-        <Source name="source/drop2_fifo.v" type="Verilog" type_short="Verilog">
+        <Source name="../../../source/drop_fifo.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
-        <Source name="source/ethernet_params.v" type="Verilog" type_short="Verilog" excluded="TRUE">
+        <Source name="../../../source/drop2_fifo.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
-        <Source name="source/fcs.v" type="Verilog" type_short="Verilog">
+        <Source name="../../../source/ethernet_params.v" type="Verilog" type_short="Verilog" excluded="TRUE">
             <Options/>
         </Source>
-        <Source name="source/half_fifo.v" type="Verilog" type_short="Verilog">
+        <Source name="../../../source/fcs.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
-        <Source name="source/i2c.v" type="Verilog" type_short="Verilog">
+        <Source name="../../../source/half_fifo.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
-        <Source name="source/ipv4.v" type="Verilog" type_short="Verilog">
+        <Source name="../../../source/i2c.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
-        <Source name="source/interrupts.v" type="Verilog" type_short="Verilog">
+        <Source name="../../../source/interrupts.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
-        <Source name="source/mac.v" type="Verilog" type_short="Verilog">
+        <Source name="../../../source/ipv4.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
-        <Source name="source/metrics.v" type="Verilog" type_short="Verilog">
+        <Source name="../../../source/link_timer.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
-        <Source name="source/mdio_cont.v" type="Verilog" type_short="Verilog">
+        <Source name="../../../source/mac.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
-        <Source name="source/mdio.v" type="Verilog" type_short="Verilog">
+        <Source name="../../../source/mdio.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
-        <Source name="source/mdio_data_ti.v" type="Verilog" type_short="Verilog">
+        <Source name="../../../source/mdio_cont.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
-        <Source name="source/pkt_filter.v" type="Verilog" type_short="Verilog">
+        <Source name="../../../source/mdio_data_ti.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
-        <Source name="source/sgmii_params.v" type="Verilog" type_short="Verilog" excluded="TRUE">
+        <Source name="../../../source/metrics.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
-        <Source name="source/spi.v" type="Verilog" type_short="Verilog">
+        <Source name="../../../source/pkt_filter.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
-        <Source name="source/switch.v" type="Verilog" type_short="Verilog">
+        <Source name="../../../source/sgmii_params.v" type="Verilog" type_short="Verilog" excluded="TRUE">
             <Options/>
         </Source>
-        <Source name="source/sync_fifo.v" type="Verilog" type_short="Verilog">
+        <Source name="../../../source/spi.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
-        <Source name="source/sync2_fifo.v" type="Verilog" type_short="Verilog">
+        <Source name="../../../source/switch.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
-        <Source name="source/sync4_fifo.v" type="Verilog" type_short="Verilog">
+        <Source name="../../../source/sync_fifo.v" type="Verilog" type_short="Verilog">
             <Options/>
         </Source>
-        <Source name="source/top.v" type="Verilog" type_short="Verilog">
-            <Options top_module="top"/>
+        <Source name="../../../source/sync4_fifo.v" type="Verilog" type_short="Verilog">
+            <Options/>
+        </Source>
+        <Source name="../../../source/sync2_fifo.v" type="Verilog" type_short="Verilog">
+            <Options/>
         </Source>
         <Source name="clarity/pcs/pcs.sbx" type="sbx" type_short="SBX">
             <Options/>
@@ -119,9 +121,6 @@
         <Source name="clarity/pcs/sgmii3/sgmii3.v" type="Verilog" type_short="Verilog" excluded="TRUE">
             <Options/>
         </Source>
-        <Source name="../../../lscc/diamond/3.10_x64/synpbase/lib/lucent/ecp5um.v" type="Verilog" type_short="Verilog" excluded="TRUE">
-            <Options/>
-        </Source>
         <Source name="boards/darsena/darsena_v02.lpf" type="Logic Preference" type_short="LPF">
             <Options/>
         </Source>
diff --git a/programming/local_background.xcf b/manufacturer/device/ecp5um/programming/local_background.xcf
index 7a92104..7a92104 100644
--- a/programming/local_background.xcf
+++ b/manufacturer/device/ecp5um/programming/local_background.xcf
diff --git a/programming/local_jtag.xcf b/manufacturer/device/ecp5um/programming/local_jtag.xcf
index 5fde840..5fde840 100644
--- a/programming/local_jtag.xcf
+++ b/manufacturer/device/ecp5um/programming/local_jtag.xcf
diff --git a/programming/read_device_status.xcf b/manufacturer/device/ecp5um/programming/read_device_status.xcf
index 21c70e3..21c70e3 100644
--- a/programming/read_device_status.xcf
+++ b/manufacturer/device/ecp5um/programming/read_device_status.xcf
diff --git a/source/pcs.v b/source/pcs.v
deleted file mode 100644
index 8722887..0000000
--- a/source/pcs.v
+++ /dev/null
@@ -1,228 +0,0 @@
-/* synthesis translate_off*/
-`define SBP_SIMULATION
-/* synthesis translate_on*/
-`ifndef SBP_SIMULATION
-`define SBP_SYNTHESIS
-`endif
-
-//
-// Verific Verilog Description of module pcs
-//
-module pcs (sgmii0_rx_cv_err, sgmii0_rx_disp_err, sgmii0_rx_k, sgmii0_rxdata, 
-            sgmii0_sci_addr, sgmii0_sci_rddata, sgmii0_sci_wrdata, sgmii0_tx_disp_correct, 
-            sgmii0_tx_k, sgmii0_txdata, sgmii0_xmit, sgmii1_rx_cv_err, 
-            sgmii1_rx_disp_err, sgmii1_rx_k, sgmii1_rxdata, sgmii1_tx_disp_correct, 
-            sgmii1_tx_k, sgmii1_txdata, sgmii1_xmit, sgmii2_rx_cv_err, 
-            sgmii2_rx_disp_err, sgmii2_rx_k, sgmii2_rxdata, sgmii2_sci_addr, 
-            sgmii2_sci_rddata, sgmii2_sci_wrdata, sgmii2_tx_disp_correct, 
-            sgmii2_tx_k, sgmii2_txdata, sgmii2_xmit, refclk0_refclkn, 
-            refclk0_refclkp, sgmii0_ctc_del_s, sgmii0_ctc_ins_s, sgmii0_ctc_orun_s, 
-            sgmii0_ctc_urun_s, sgmii0_cyawstn, sgmii0_hdinn, sgmii0_hdinp, 
-            sgmii0_hdoutn, sgmii0_hdoutp, sgmii0_lsm_status_s, sgmii0_rst_dual_c, 
-            sgmii0_rx_cdr_lol_s, sgmii0_rx_los_low_s, sgmii0_rx_pcs_rst_c, 
-            sgmii0_rx_pwrup_c, sgmii0_rx_serdes_rst_c, sgmii0_sci_en, 
-            sgmii0_sci_en_dual, sgmii0_sci_int, sgmii0_sci_rd, sgmii0_sci_sel, 
-            sgmii0_sci_sel_dual, sgmii0_sci_wrn, sgmii0_serdes_rst_dual_c, 
-            sgmii0_signal_detect_c, sgmii0_tx_pclk, sgmii0_tx_pcs_rst_c, 
-            sgmii0_tx_pwrup_c, sgmii0_tx_serdes_rst_c, sgmii0_txi_clk, sgmii0_pll_lol, 
-            sgmii1_ctc_del_s, sgmii1_ctc_ins_s, sgmii1_ctc_orun_s, sgmii1_ctc_urun_s, 
-            sgmii1_hdinn, sgmii1_hdinp, sgmii1_hdoutn, sgmii1_hdoutp, 
-            sgmii1_lsm_status_s, sgmii1_rst_dual_c, 
-            sgmii1_rx_cdr_lol_s, sgmii1_rx_los_low_s, sgmii1_rx_pcs_rst_c, 
-            sgmii1_rx_pwrup_c, sgmii1_rx_serdes_rst_c,  
-            sgmii1_serdes_pdb, sgmii1_serdes_rst_dual_c, sgmii1_signal_detect_c, 
-            sgmii1_tx_pclk, sgmii1_tx_pcs_rst_c, sgmii1_tx_pwrup_c, sgmii1_tx_serdes_rst_c, 
-            sgmii1_txi_clk, sgmii2_ctc_del_s, sgmii2_ctc_ins_s, sgmii2_ctc_orun_s, 
-            sgmii2_ctc_urun_s, sgmii2_cyawstn, sgmii2_hdinn, sgmii2_hdinp, 
-            sgmii2_hdoutn, sgmii2_hdoutp, sgmii2_lsm_status_s, sgmii2_pll_lol, 
-            sgmii2_rst_dual_c, sgmii2_rx_cdr_lol_s, sgmii2_rx_los_low_s, 
-            sgmii2_rx_pcs_rst_c, sgmii2_rx_pwrup_c, sgmii2_rx_serdes_rst_c, 
-            sgmii2_sci_en, sgmii2_sci_en_dual, sgmii2_sci_int, sgmii2_sci_rd, 
-            sgmii2_sci_sel, sgmii2_sci_sel_dual, sgmii2_sci_wrn, sgmii2_serdes_pdb, 
-            sgmii2_serdes_rst_dual_c, sgmii2_signal_detect_c, sgmii2_tx_pclk, 
-            sgmii2_tx_pcs_rst_c, sgmii2_tx_pwrup_c, sgmii2_tx_serdes_rst_c, 
-            sgmii2_txi_clk, refclk0_refclko) /* synthesis sbp_module=true */ ;
-    output [0:0]sgmii0_rx_cv_err;
-    output [0:0]sgmii0_rx_disp_err;
-    output [0:0]sgmii0_rx_k;
-    output [7:0]sgmii0_rxdata;
-    input [5:0]sgmii0_sci_addr;
-    output [7:0]sgmii0_sci_rddata;
-    input [7:0]sgmii0_sci_wrdata;
-    input [0:0]sgmii0_tx_disp_correct;
-    input [0:0]sgmii0_tx_k;
-    input [7:0]sgmii0_txdata;
-    input [0:0]sgmii0_xmit;
-    output [0:0]sgmii1_rx_cv_err;
-    output [0:0]sgmii1_rx_disp_err;
-    output [0:0]sgmii1_rx_k;
-    output [7:0]sgmii1_rxdata;
-    input [0:0]sgmii1_tx_disp_correct;
-    input [0:0]sgmii1_tx_k;
-    input [7:0]sgmii1_txdata;
-    input [0:0]sgmii1_xmit;
-    output [0:0]sgmii2_rx_cv_err;
-    output [0:0]sgmii2_rx_disp_err;
-    output [0:0]sgmii2_rx_k;
-    output [7:0]sgmii2_rxdata;
-    input [5:0]sgmii2_sci_addr;
-    output [7:0]sgmii2_sci_rddata;
-    input [7:0]sgmii2_sci_wrdata;
-    input [0:0]sgmii2_tx_disp_correct;
-    input [0:0]sgmii2_tx_k;
-    input [7:0]sgmii2_txdata;
-    input [0:0]sgmii2_xmit;
-    input refclk0_refclkn;
-    input refclk0_refclkp;
-    output sgmii0_ctc_del_s;
-    output sgmii0_ctc_ins_s;
-    output sgmii0_ctc_orun_s;
-    output sgmii0_ctc_urun_s;
-    input sgmii0_cyawstn;
-    input sgmii0_hdinn;
-    input sgmii0_hdinp;
-    output sgmii0_hdoutn;
-    output sgmii0_hdoutp;
-    output sgmii0_lsm_status_s;
-    input sgmii0_rst_dual_c;
-    output sgmii0_rx_cdr_lol_s;
-    output sgmii0_rx_los_low_s;
-    input sgmii0_rx_pcs_rst_c;
-    input sgmii0_rx_pwrup_c;
-    input sgmii0_rx_serdes_rst_c;
-    input sgmii0_sci_en;
-    input sgmii0_sci_en_dual;
-    output sgmii0_sci_int;
-    input sgmii0_sci_rd;
-    input sgmii0_sci_sel;
-    input sgmii0_sci_sel_dual;
-    input sgmii0_sci_wrn;
-    input sgmii0_serdes_rst_dual_c;
-    input sgmii0_signal_detect_c;
-    output sgmii0_tx_pclk;
-    input sgmii0_tx_pcs_rst_c;
-    input sgmii0_tx_pwrup_c;
-    input sgmii0_tx_serdes_rst_c;
-    input sgmii0_txi_clk;
-	output sgmii0_pll_lol;
-    output sgmii1_ctc_del_s;
-    output sgmii1_ctc_ins_s;
-    output sgmii1_ctc_orun_s;
-    output sgmii1_ctc_urun_s;
-    input sgmii1_hdinn;
-    input sgmii1_hdinp;
-    output sgmii1_hdoutn;
-    output sgmii1_hdoutp;
-    output sgmii1_lsm_status_s;
-    input sgmii1_rst_dual_c;
-    output sgmii1_rx_cdr_lol_s;
-    output sgmii1_rx_los_low_s;
-    input sgmii1_rx_pcs_rst_c;
-    input sgmii1_rx_pwrup_c;
-    input sgmii1_rx_serdes_rst_c;
-    input sgmii1_serdes_pdb;
-    input sgmii1_serdes_rst_dual_c;
-    input sgmii1_signal_detect_c;
-    output sgmii1_tx_pclk;
-    input sgmii1_tx_pcs_rst_c;
-    input sgmii1_tx_pwrup_c;
-    input sgmii1_tx_serdes_rst_c;
-    input sgmii1_txi_clk;
-    output sgmii2_ctc_del_s;
-    output sgmii2_ctc_ins_s;
-    output sgmii2_ctc_orun_s;
-    output sgmii2_ctc_urun_s;
-    input sgmii2_cyawstn;
-    input sgmii2_hdinn;
-    input sgmii2_hdinp;
-    output sgmii2_hdoutn;
-    output sgmii2_hdoutp;
-    output sgmii2_lsm_status_s;
-    output sgmii2_pll_lol;
-    input sgmii2_rst_dual_c;
-    output sgmii2_rx_cdr_lol_s;
-    output sgmii2_rx_los_low_s;
-    input sgmii2_rx_pcs_rst_c;
-    input sgmii2_rx_pwrup_c;
-    input sgmii2_rx_serdes_rst_c;
-    input sgmii2_sci_en;
-    input sgmii2_sci_en_dual;
-    output sgmii2_sci_int;
-    input sgmii2_sci_rd;
-    input sgmii2_sci_sel;
-    input sgmii2_sci_sel_dual;
-    input sgmii2_sci_wrn;
-    input sgmii2_serdes_pdb;
-    input sgmii2_serdes_rst_dual_c;
-    input sgmii2_signal_detect_c;
-    output sgmii2_tx_pclk;
-    input sgmii2_tx_pcs_rst_c;
-    input sgmii2_tx_pwrup_c;
-    input sgmii2_tx_serdes_rst_c;
-    input sgmii2_txi_clk;
-	output refclk0_refclko;
-    
-    
-    wire sli_rst_wire0, sli_rst_wire2;
-    
-    assign sli_rst_wire0 = sgmii0_serdes_rst_dual_c ||  sgmii0_tx_serdes_rst_c ||  (!sgmii1_serdes_pdb) ||  (!sgmii0_tx_pwrup_c) ||  (!sgmii1_tx_pwrup_c);
-    assign sli_rst_wire2 = sgmii2_serdes_rst_dual_c ||  sgmii2_tx_serdes_rst_c ||  (!sgmii2_serdes_pdb) ||  (!sgmii2_tx_pwrup_c);
-    refclk0 refclk0_inst (.refclkn(refclk0_refclkn), .refclko(refclk0_refclko), 
-            .refclkp(refclk0_refclkp));
-    sgmii0 sgmii0_inst (.rx_cv_err({sgmii0_rx_cv_err}), .rx_disp_err({sgmii0_rx_disp_err}), 
-           .rx_k({sgmii0_rx_k}), .rxdata({sgmii0_rxdata}), .sci_addr({sgmii0_sci_addr}), 
-           .sci_rddata({sgmii0_sci_rddata}), .sci_wrdata({sgmii0_sci_wrdata}), 
-           .tx_disp_correct({sgmii0_tx_disp_correct}), .tx_k({sgmii0_tx_k}), 
-           .txdata({sgmii0_txdata}), .xmit({sgmii0_xmit}), .ctc_del_s(sgmii0_ctc_del_s), 
-           .ctc_ins_s(sgmii0_ctc_ins_s), .ctc_orun_s(sgmii0_ctc_orun_s), 
-           .ctc_urun_s(sgmii0_ctc_urun_s), .cyawstn(sgmii0_cyawstn), .hdinn(sgmii0_hdinn), 
-           .hdinp(sgmii0_hdinp), .hdoutn(sgmii0_hdoutn), .hdoutp(sgmii0_hdoutp), 
-           .lsm_status_s(sgmii0_lsm_status_s), .pll_refclki(refclk0_refclko), 
-           .rst_dual_c(sgmii0_rst_dual_c), .rx_cdr_lol_s(sgmii0_rx_cdr_lol_s), 
-           .rx_los_low_s(sgmii0_rx_los_low_s), .rx_pcs_rst_c(sgmii0_rx_pcs_rst_c), 
-           .rx_pwrup_c(sgmii0_rx_pwrup_c), .rx_serdes_rst_c(sgmii0_rx_serdes_rst_c), 
-           .rxrefclk(refclk0_refclko), .sci_en(sgmii0_sci_en), .sci_en_dual(sgmii0_sci_en_dual), 
-           .sci_int(sgmii0_sci_int), .sci_rd(sgmii0_sci_rd), .sci_sel(sgmii0_sci_sel), 
-           .sci_sel_dual(sgmii0_sci_sel_dual), .sci_wrn(sgmii0_sci_wrn), 
-           .serdes_pdb(sgmii1_serdes_pdb), .serdes_rst_dual_c(sgmii0_serdes_rst_dual_c), 
-           .signal_detect_c(sgmii0_signal_detect_c), .sli_rst(sli_rst_wire0), 
-           .tx_pclk(sgmii0_tx_pclk), .tx_pcs_rst_c(sgmii0_tx_pcs_rst_c), 
-           .tx_pwrup_c(sgmii0_tx_pwrup_c), .tx_serdes_rst_c(sgmii0_tx_serdes_rst_c), 
-           .txi_clk(sgmii0_txi_clk), .pll_lol(sgmii0_pll_lol));
-    sgmii1 sgmii1_inst (.rx_cv_err({sgmii1_rx_cv_err}), .rx_disp_err({sgmii1_rx_disp_err}), 
-           .rx_k({sgmii1_rx_k}), .rxdata({sgmii1_rxdata}), .tx_disp_correct({sgmii1_tx_disp_correct}), 
-           .tx_k({sgmii1_tx_k}), .txdata({sgmii1_txdata}), .xmit({sgmii1_xmit}), 
-           .ctc_del_s(sgmii1_ctc_del_s), .ctc_ins_s(sgmii1_ctc_ins_s), .ctc_orun_s(sgmii1_ctc_orun_s), 
-           .ctc_urun_s(sgmii1_ctc_urun_s), .hdinn(sgmii1_hdinn), .hdinp(sgmii1_hdinp), 
-           .hdoutn(sgmii1_hdoutn), .hdoutp(sgmii1_hdoutp), .lsm_status_s(sgmii1_lsm_status_s), 
-           .pll_refclki(refclk0_refclko), .rst_dual_c(sgmii1_rst_dual_c), 
-           .rx_cdr_lol_s(sgmii1_rx_cdr_lol_s), .rx_los_low_s(sgmii1_rx_los_low_s), 
-           .rx_pcs_rst_c(sgmii1_rx_pcs_rst_c), .rx_pwrup_c(sgmii1_rx_pwrup_c), 
-           .rx_serdes_rst_c(sgmii1_rx_serdes_rst_c), .rxrefclk(refclk0_refclko), 
-           .serdes_pdb(sgmii1_serdes_pdb), .serdes_rst_dual_c(sgmii1_serdes_rst_dual_c), 
-           .signal_detect_c(sgmii1_signal_detect_c), .tx_pclk(sgmii1_tx_pclk), 
-           .tx_pcs_rst_c(sgmii1_tx_pcs_rst_c), .tx_pwrup_c(sgmii1_tx_pwrup_c), 
-           .tx_serdes_rst_c(sgmii1_tx_serdes_rst_c), .txi_clk(sgmii1_txi_clk));
-    sgmii2 sgmii2_inst (.rx_cv_err({sgmii2_rx_cv_err}), .rx_disp_err({sgmii2_rx_disp_err}), 
-           .rx_k({sgmii2_rx_k}), .rxdata({sgmii2_rxdata}), .sci_addr({sgmii2_sci_addr}), 
-           .sci_rddata({sgmii2_sci_rddata}), .sci_wrdata({sgmii2_sci_wrdata}), 
-           .tx_disp_correct({sgmii2_tx_disp_correct}), .tx_k({sgmii2_tx_k}), 
-           .txdata({sgmii2_txdata}), .xmit({sgmii2_xmit}), .ctc_del_s(sgmii2_ctc_del_s), 
-           .ctc_ins_s(sgmii2_ctc_ins_s), .ctc_orun_s(sgmii2_ctc_orun_s), 
-           .ctc_urun_s(sgmii2_ctc_urun_s), .cyawstn(sgmii2_cyawstn), .hdinn(sgmii2_hdinn), 
-           .hdinp(sgmii2_hdinp), .hdoutn(sgmii2_hdoutn), .hdoutp(sgmii2_hdoutp), 
-           .lsm_status_s(sgmii2_lsm_status_s), .pll_lol(sgmii2_pll_lol), 
-           .pll_refclki(refclk0_refclko), .rst_dual_c(sgmii2_rst_dual_c), 
-           .rx_cdr_lol_s(sgmii2_rx_cdr_lol_s), .rx_los_low_s(sgmii2_rx_los_low_s), 
-           .rx_pcs_rst_c(sgmii2_rx_pcs_rst_c), .rx_pwrup_c(sgmii2_rx_pwrup_c), 
-           .rx_serdes_rst_c(sgmii2_rx_serdes_rst_c), .rxrefclk(refclk0_refclko), 
-           .sci_en(sgmii2_sci_en), .sci_en_dual(sgmii2_sci_en_dual), .sci_int(sgmii2_sci_int), 
-           .sci_rd(sgmii2_sci_rd), .sci_sel(sgmii2_sci_sel), .sci_sel_dual(sgmii2_sci_sel_dual), 
-           .sci_wrn(sgmii2_sci_wrn), .serdes_pdb(sgmii2_serdes_pdb), .serdes_rst_dual_c(sgmii2_serdes_rst_dual_c), 
-           .signal_detect_c(sgmii2_signal_detect_c), .sli_rst(sli_rst_wire2), 
-           .tx_pclk(sgmii2_tx_pclk), .tx_pcs_rst_c(sgmii2_tx_pcs_rst_c), 
-           .tx_pwrup_c(sgmii2_tx_pwrup_c), .tx_serdes_rst_c(sgmii2_tx_serdes_rst_c), 
-           .txi_clk(sgmii2_txi_clk));
-    
-endmodule
-