diff options
| author | mindchasers <privateisland@mindchasers.com> | 2020-11-15 23:42:42 -0500 |
|---|---|---|
| committer | mindchasers <privateisland@mindchasers.com> | 2020-11-15 23:42:42 -0500 |
| commit | 3e6999c467908663d2539483de82057f587ffbb2 (patch) | |
| tree | ec10f61e27b36eee8a37f46feb45601243174fc4 /clarity/pcs/refclk0/refclk0.v | |
| parent | 8e8ce59d8f74e1d3de89e5b2b720039ed32a9768 (diff) | |
ecp5um project: restructure so we can add more devices
Diffstat (limited to 'clarity/pcs/refclk0/refclk0.v')
| -rw-r--r-- | clarity/pcs/refclk0/refclk0.v | 20 |
1 files changed, 0 insertions, 20 deletions
diff --git a/clarity/pcs/refclk0/refclk0.v b/clarity/pcs/refclk0/refclk0.v deleted file mode 100644 index edeb81f..0000000 --- a/clarity/pcs/refclk0/refclk0.v +++ /dev/null @@ -1,20 +0,0 @@ -// Verilog netlist produced by program ASBGen: Ports rev. 2.30, Attr. rev. 2.65 -// Netlist written on Fri Mar 06 20:20:57 2020 -// -// Verilog Description of module refclk0 -// - -`timescale 1ns/1ps -module refclk0 (refclkp, refclkn, refclko); - input refclkp; - input refclkn; - output refclko; - - - EXTREFB EXTREF0_inst (.REFCLKP(refclkp), .REFCLKN(refclkn), .REFCLKO(refclko)) /* synthesis LOC=EXTREF0 */ ; - defparam EXTREF0_inst.REFCK_PWDNB = "0b1"; - defparam EXTREF0_inst.REFCK_RTERM = "0b1"; - defparam EXTREF0_inst.REFCK_DCBIAS_EN = "0b0"; - -endmodule - |
