Mind Chasers Inc.
Mind Chasers Inc.

Private Island: Open Source, FPGA-based Network Processor


We utilize an FPGA for networking in order to build an open, trustworthy, and extensible foundation for packet processing, IoT, and control (e.g., sensors, motors, etc.)

When the FPGA filters certain addresses, ports, and / or protocols, we are able to confirm at the hardware layer that this has been accomplished. This is in stark contrast to off-the-shelf SoC implementations, which require developers & users to make assumptions of multiple layers (typically opaque) being free of bugs, back doors, and resident spies / spyware.

The open FPGA-based architecture supports numerous, highly parallel functions implemented at Ethernet line rate (125 MHz x 8-bit). Our Darsena development board, which is Arduino form factor and pin out compatible supports Ethernet connectivity via two on-board Gigabit Ethernet PHYs and integrates an ARM micro controller, debuggers, and also offers expansion via Arduino-style connectors.

Private Island Conceptual Block Diagram
Private Island System Concept

Gigabit / 100 Mbit Ethernet switch

Real-time packet filtering, inspection, and mirroring

Gigabit Ethernet MAC controller for external micro controller

Customizable metrics. Stream them to the host of your choice.

Dozens of expansion I/O

It's an FPGA and open source, so the applications are endless.

The figure below shows a block diagram of the FPGA Verilog modules comprising a typical Private Island instantiation. Note that the SERDES/PCS functionality is currently provided by a hard macrocell inside the Latthce ECP5UM. The receive (rx) path is into the soft Ethernet switch, and the transmit path is out of the switch.

You can find the source for Private Island on Github: https://github.com/privateisland/privateisland

development block diagram
Private Island FPGA Modular Architecture

Project Goals

Strive for modularity and simplicity

Support multiple FPGAs using both SGMII and RGMII (Lattice ECP5 is first instance)

Limited number of dependencies and only when necessary

Enable connecting new modules for new applications

Deterministic packet visibility from inside and outside the FPGA

Never compromise the integrity of the data

Help Wanted

Private Island is an open source project, so you're very much encouraged to jump in and make contributions in areas that interest you most. If you're planning work, we would love to exchange ideas with you to coordinate the work and reduce duplication of effort.

We're currently working in the following areas and plan commits early in 2019:

  • General clean up and more documentation (both high level concept and specification)
  • State machines dedicated for Layer 3 and 4 processing
  • Functional test benches for packet processing modules
  • Define and set course for embedded machine learning
  • Clean up and commit ARMv7 M4 micro controller code base
  • Define Python API / library framework for remote host processor and commit skeleton library

In addition to the above, we also need help in the following areas:

  • Experiment and Validate with Open Source Toolchain (details coming)
  • Support of OpenOCD on Windows using OpenOCD's master branch
  • Code validation (FPGA Verilog) for pull requests
  • Functional test bench and RTL for ECP5 SERDES block
  • Port to other FPGAs, PHYs, and support RGMII (Please consider us for building the hardware models)

Our Development Board: Darsena

  • Arduino form-factor compatible with dozens of I/O for expansion and shield support
  • Lattice ECP5UM FPGA (45K LUTs with integrated PCS/SERDES)
  • Two Texas Instruments DP83867 Gigabit PHYs
  • NXP Kinetis K02 Microcontroller with ARM Cortex M4 core
  • Micron SPI ROM

Our Darsena development board customers will receive a one year license for the Lattice Diamond IDE. This package enables developer to synthesize, map, place & route, program, analyze, and debug the Private Island source code.

If you're interested in being a Darsena early adopter (working with pre-release hardware), please send us an email or fill in the form below.

development block diagram

The figure below shows the Lattice Diamond IDE with the Physical Viewer window enabled. This viewer shows the routing of an instantiation of Private Island with one of the wires of the Ethernet rx_data bus highlighted.

Diamond IDE showing Physical Viewer
Lattice Diamond IDE showing Physical Viewer

The next figure shows the Lattice Diamond Reveal Analyzer active with a trace of the Ethernet receive path. This gives new meaning to the concept of packet inspection and enables developers to see packets within their FPGA as it traverses their device.

Diamond IDE showing Physical Viewer
Lattice Diamond Reveal Logic Analyzer

Related Documentation

Architecture and Code Description for the Private Island System
A high level overview of the usage and configuration of the ECP5UM DCU (PCS/SERDES) for Private Island Open Source Project
Documentation of FPGA'S memory and register interface
A summary and concise reference of ECP5UM features and capabilities as applied to the Private Island open source project
A quick start guide for working with Darsena, the Private Island development platform
Board Walkthrough and Circuit Description [DRAFT]
[ Page last updated: December 31, 2018 ]
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If you have a question about Private Island and whether it can be used for your application, then please post it on our forum.

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