diff options
Diffstat (limited to 'manufacturer/lattice/ecp5um/source')
| -rw-r--r-- | manufacturer/lattice/ecp5um/source/ecp5um.v | 2105 | ||||
| -rw-r--r-- | manufacturer/lattice/ecp5um/source/top.v | 2361 |
2 files changed, 4466 insertions, 0 deletions
diff --git a/manufacturer/lattice/ecp5um/source/ecp5um.v b/manufacturer/lattice/ecp5um/source/ecp5um.v new file mode 100644 index 0000000..de563c2 --- /dev/null +++ b/manufacturer/lattice/ecp5um/source/ecp5um.v @@ -0,0 +1,2105 @@ +// -------------------------------------------------------------------- +// >>>>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<< +// -------------------------------------------------------------------- +// Copyright (c) 2002-2012 by Lattice Semiconductor Corporation +// -------------------------------------------------------------------- +// +// +// Lattice Semiconductor Corporation +// 5555 NE Moore Court +// Hillsboro, OR 97214 +// U.S.A +// +// TEL: 1-800-Lattice (USA and Canada) +// 408-826-6000 (other locations) +// +// web: http://www.latticesemi.com/ +// email: techsupport@latticesemi.com +// +// -------------------------------------------------------------------- +// +// Header files for ECP5U family +// +// -------------------------------------------------------------------- + +module AND2 (A, B, Z); //synthesis syn_black_box syn_lib_cell=1 + input A ; + input B ; + output Z ; +endmodule + +module AND3 (A, B, C, Z); //synthesis syn_black_box syn_lib_cell=1 + input A ; + input B ; + input C ; + output Z ; +endmodule + +module AND4 (A, B, C, D, Z); //synthesis syn_black_box syn_lib_cell=1 + input A ; + input B ; + input C ; + input D ; + output Z ; +endmodule + +module AND5 (A, B, C, D, E, Z); //synthesis syn_black_box syn_lib_cell=1 + input A ; + input B ; + input C ; + input D ; + input E ; + output Z ; +endmodule + +module BB (I, T, O, B); //synthesis syn_black_box syn_lib_cell=1 black_box_pad_pin="B" + input I ; + input T ; + output O ; + inout B ; +endmodule + +module BBPD (I, T, O, B); //synthesis syn_black_box syn_lib_cell=1 black_box_pad_pin="B" + input I ; + input T ; + output O; + inout B ; +endmodule + +module BBPU (I, T, O, B); //synthesis syn_black_box syn_lib_cell=1 black_box_pad_pin="B" + input I ; + input T ; + output O; + inout B ; +endmodule + +module CCU2C ( + CIN, + A0, B0, C0, D0, + A1, B1, C1, D1, + S0, S1, COUT +); //synthesis syn_black_box syn_lib_cell=1 syn_unconnected_inputs = "CIN" + + input CIN; + input A0, B0, C0, D0; + input A1, B1, C1, D1; + output S0, S1, COUT; + parameter [15:0] INIT0 = 16'h0000; + parameter [15:0] INIT1 = 16'h0000; + parameter INJECT1_0 = "YES"; + parameter INJECT1_1 = "YES"; +endmodule + + +module FD1P3AX (D, SP, CK, Q); //synthesis syn_black_box syn_lib_cell=1 + parameter GSR = "ENABLED"; + input D ; + input SP ; + input CK ; + output Q ; +endmodule + +module FD1P3AY (D, SP, CK, Q); //synthesis syn_black_box syn_lib_cell=1 + parameter GSR = "ENABLED"; + input D ; + input SP ; + input CK ; + output Q ; +endmodule + +module FD1P3BX (D, SP, CK, PD, Q); //synthesis syn_black_box syn_lib_cell=1 + parameter GSR = "ENABLED"; + input D ; + input SP ; + input CK ; + input PD ; + output Q ; +endmodule + +module FD1P3DX (D, SP, CK, CD, Q); //synthesis syn_black_box syn_lib_cell=1 + parameter GSR = "ENABLED"; + input D ; + input SP ; + input CK ; + input CD ; + output Q ; +endmodule + +module FD1P3IX (D, SP, CK, CD, Q); //synthesis syn_black_box syn_lib_cell=1 + parameter GSR = "ENABLED"; + input D ; + input SP ; + input CK ; + input CD ; + output Q ; +endmodule + +module FD1P3JX (D, SP, CK, PD, Q); //synthesis syn_black_box syn_lib_cell=1 + parameter GSR = "ENABLED"; + input D ; + input SP ; + input CK ; + input PD ; + output Q ; +endmodule + +module FD1S3AX (D, CK, Q); //synthesis syn_black_box syn_lib_cell=1 + parameter GSR = "ENABLED"; + input D ; + input CK ; + output Q ; +endmodule + +module FD1S3AY (D, CK, Q); //synthesis syn_black_box syn_lib_cell=1 + parameter GSR = "ENABLED"; + input D ; + input CK ; + output Q ; +endmodule + +module FD1S3BX (D, CK, PD, Q); //synthesis syn_black_box syn_lib_cell=1 + parameter GSR = "ENABLED"; + input D ; + input CK ; + input PD ; + output Q ; +endmodule + +module FD1S3DX (D, CK, CD, Q); //synthesis syn_black_box syn_lib_cell=1 + parameter GSR = "ENABLED"; + input D ; + input CK ; + input CD ; + output Q ; +endmodule + +module FD1S3IX (D, CK, CD, Q); //synthesis syn_black_box syn_lib_cell=1 + parameter GSR = "ENABLED"; + input D ; + input CK ; + input CD ; + output Q ; +endmodule + +module FD1S3JX (D, CK, PD, Q); //synthesis syn_black_box syn_lib_cell=1 + parameter GSR = "ENABLED"; + input D ; + input CK ; + input PD ; + output Q ; +endmodule + +module FL1P3AY (D1, D0, SP, CK, SD, Q); //synthesis syn_black_box syn_lib_cell=1 + parameter GSR = "ENABLED"; + input D1 ; + input D0 ; + input SP ; + input CK ; + input SD ; + output Q ; +endmodule + +module FL1P3AZ (D1, D0, SP, CK, SD, Q); //synthesis syn_black_box syn_lib_cell=1 + parameter GSR = "ENABLED"; + input D1 ; + input D0 ; + input SP ; + input CK ; + input SD ; + output Q ; +endmodule + +module FL1P3BX (D1, D0, SP, CK, SD, PD, Q); //synthesis syn_black_box syn_lib_cell=1 + parameter GSR = "ENABLED"; + input D1 ; + input D0 ; + input SP ; + input CK ; + input SD ; + input PD ; + output Q ; +endmodule + +module FL1P3DX (D1, D0, SP, CK, SD, CD, Q); //synthesis syn_black_box syn_lib_cell=1 + parameter GSR = "ENABLED"; + input D1 ; + input D0 ; + input SP ; + input CK ; + input SD ; + input CD ; + output Q ; +endmodule + +module FL1P3IY (D1, D0, SP, CK, SD, CD, Q); //synthesis syn_black_box syn_lib_cell=1 + parameter GSR = "ENABLED"; + input D1 ; + input D0 ; + input SP ; + input CK ; + input SD ; + input CD ; + output Q ; +endmodule + +module FL1P3JY (D1, D0, SP, CK, SD, PD, Q); //synthesis syn_black_box syn_lib_cell=1 + parameter GSR = "ENABLED"; + input D1 ; + input D0 ; + input SP ; + input CK ; + input SD ; + input PD ; + output Q ; +endmodule + +module FL1S3AX (D1, D0, CK, SD, Q); //synthesis syn_black_box syn_lib_cell=1 + parameter GSR = "ENABLED"; + input D1; + input D0; + input CK; + input SD; + output Q; +endmodule + +module FL1S3AY (D1, D0, CK, SD, Q); //synthesis syn_black_box syn_lib_cell=1 + parameter GSR = "ENABLED"; + input D1; + input D0; + input CK; + input SD; + output Q; +endmodule + +module GSR (GSR); //synthesis syn_black_box syn_lib_cell=1 syn_noprune=1 + input GSR ; +endmodule + +module IB (I, O); //synthesis syn_black_box syn_lib_cell=1 black_box_pad_pin="I" + input I ; + output O ; +endmodule + +module IBPD (I, O); //synthesis syn_black_box syn_lib_cell=1 black_box_pad_pin="I" + input I ; + output O ; +endmodule + +module IBPU (I, O); //synthesis syn_black_box syn_lib_cell=1 black_box_pad_pin="I" + input I; + output O; +endmodule + +module IFS1P3BX (D, SP, SCLK, PD, Q); //synthesis syn_black_box syn_lib_cell=1 + parameter GSR = "ENABLED"; + input D; + input SP; + input SCLK; + input PD; + output Q; +endmodule + +module IFS1P3DX (D, SP, SCLK, CD, Q); //synthesis syn_black_box syn_lib_cell=1 + parameter GSR = "ENABLED"; + input D; + input SP; + input SCLK; + input CD; + output Q; +endmodule + +module IFS1P3IX (D, SP, SCLK, CD, Q); //synthesis syn_black_box syn_lib_cell=1 + parameter GSR = "ENABLED"; + input D; + input SP; + input SCLK; + input CD; + output Q; +endmodule + +module IFS1P3JX (D, SP, SCLK, PD, Q); //synthesis syn_black_box syn_lib_cell=1 + parameter GSR = "ENABLED"; + input D; + input SP; + input SCLK; + input PD; + output Q; +endmodule + +module IFS1S1B (D, SCLK, PD, Q); //synthesis syn_black_box syn_lib_cell=1 + parameter GSR = "ENABLED"; + input D; + input SCLK; + input PD; + output Q; +endmodule + +module IFS1S1D (D, SCLK, CD, Q); //synthesis syn_black_box syn_lib_cell=1 + parameter GSR = "ENABLED"; + input D; + input SCLK; + input CD; + output Q; +endmodule + +module IFS1S1I (D, SCLK, CD, Q); //synthesis syn_black_box syn_lib_cell=1 + parameter GSR = "ENABLED"; + input D; + input SCLK; + input CD; + output Q; +endmodule + +module IFS1S1J (D, SCLK, PD, Q); //synthesis syn_black_box syn_lib_cell=1 + parameter GSR = "ENABLED"; + input D; + input SCLK; + input PD; + output Q; +endmodule + +module ILVDS (A, AN, Z); //synthesis syn_black_box syn_lib_cell=1 black_box_pad_pin="A,AN" + input A; + input AN; + output Z; +endmodule + +module INV (A, Z); //synthesis syn_black_box syn_lib_cell=1 + input A; + output Z; +endmodule + +module L6MUX21 (D0, D1, SD, Z); //synthesis syn_black_box syn_lib_cell=1 + input D0; + input D1; + input SD; + output Z; +endmodule + +module LUT4 (A, B, C, D, Z); //synthesis syn_black_box syn_lib_cell=1 + parameter [15:0] init = 16'h0000 ; + input A ; + input B ; + input C ; + input D ; + output Z ; +endmodule + +module LUT5 (Z, A, B, C, D, E); //synthesis syn_black_box syn_lib_cell=1 + parameter [31:0] init = 32'h00000000 ; + input A ; + input B ; + input C ; + input D ; + input E ; + output Z ; +endmodule + +module LUT6 (Z, A, B, C, D, E, F); //synthesis syn_black_box syn_lib_cell=1 + parameter [63:0] init = 64'h0000000000000000 ; + input A ; + input B ; + input C ; + input D ; + input E ; + input F ; + output Z ; +endmodule + +module LUT7 (Z, A, B, C, D, E, F, G); //synthesis syn_black_box syn_lib_cell=1 + parameter [127:0] init = 128'h00000000000000000000000000000000 ; + input A ; + input B ; + input C ; + input D ; + input E ; + input F ; + input G ; + output Z ; +endmodule + +module LUT8 (Z, A, B, C, D, E, F, G, H); //synthesis syn_black_box syn_lib_cell=1 + parameter [255:0] init = 256'h0000000000000000000000000000000000000000000000000000000000000000; + input A ; + input B ; + input C ; + input D ; + input E ; + input F ; + input G ; + input H ; + output Z ; +endmodule + +module MUX161 (D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0, SD4, SD3, SD2, SD1, Z); //synthesis syn_black_box syn_lib_cell=1 + input D15; + input D14; + input D13; + input D12; + input D11; + input D10; + input D9; + input D8; + input D7; + input D6; + input D5; + input D4; + input D3; + input D2; + input D1; + input D0; + input SD4; + input SD3; + input SD2; + input SD1; + output Z; +endmodule + +module MUX21 (D1, D0, SD, Z); //synthesis syn_black_box syn_lib_cell=1 + input D1; + input D0; + input SD; + output Z; +endmodule + +module MUX321 (D31, D30, D29, D28, D27, D26, D25, D24, D23, D22, D21, D20, D19, D18, D17, D16, D15, D14, D13, D12, D11, D10, D9, D8, D7, D6, D5, D4, D3, D2, D1, D0, SD5, SD4, SD3, SD2, SD1, Z); //synthesis syn_black_box syn_lib_cell=1 + input D31; + input D30; + input D29; + input D28; + input D27; + input D26; + input D25; + input D24; + input D23; + input D22; + input D21; + input D20; + input D19; + input D18; + input D17; + input D16; + input D15; + input D14; + input D13; + input D12; + input D11; + input D10; + input D9; + input D8; + input D7; + input D6; + input D5; + input D4; + input D3; + input D2; + input D1; + input D0; + input SD5; + input SD4; + input SD3; + input SD2; + input SD1; + output Z; +endmodule + +module MUX41 (D3, D2, D1, D0, SD2, SD1, Z); //synthesis syn_black_box syn_lib_cell=1 + input D3 ; + input D2 ; + input D1 ; + input D0 ; + input SD2 ; + input SD1 ; + output Z ; +endmodule + +module MUX81 (D7, D6, D5, D4, D3, D2, D1, D0, SD3, SD2, SD1, Z); //synthesis syn_black_box syn_lib_cell=1 + input D7 ; + input D6 ; + input D5 ; + input D4 ; + input D3 ; + input D2 ; + input D1 ; + input D0 ; + input SD3 ; + input SD2 ; + input SD1 ; + output Z ; +endmodule + +module ND2 (A, B, Z); //synthesis syn_black_box syn_lib_cell=1 + input A ; + input B ; + output Z ; +endmodule + +module ND3 (A, B, C, Z); //synthesis syn_black_box syn_lib_cell=1 + input A ; + input B ; + input C ; + output Z ; +endmodule + +module ND4 (A, B, C, D, Z); //synthesis syn_black_box syn_lib_cell=1 + input A ; + input B ; + input C ; + input D ; + output Z ; +endmodule + +module ND5 (A, B, C, D, E, Z); //synthesis syn_black_box syn_lib_cell=1 + input A ; + input B ; + input C ; + input D ; + input E ; + output Z ; +endmodule + +module NR2 (A, B, Z); //synthesis syn_black_box syn_lib_cell=1 + input A ; + input B ; + output Z ; +endmodule + +module NR3 (A, B, C, Z); //synthesis syn_black_box syn_lib_cell=1 + input A ; + input B ; + input C ; + output Z ; +endmodule + +module NR4 (A, B, C, D, Z); //synthesis syn_black_box syn_lib_cell=1 + input A ; + input B ; + input C ; + input D ; + output Z ; +endmodule + +module NR5 (A, B, C, D, E, Z); //synthesis syn_black_box syn_lib_cell=1 + input A ; + input B ; + input C ; + input D ; + input E ; + output Z ; +endmodule + +module OB (I, O); //synthesis syn_black_box syn_lib_cell=1 black_box_pad_pin="O" + input I ; + output O ; +endmodule + +module OBCO (I, OT, OC); //synthesis syn_black_box syn_lib_cell=1 black_box_pad_pin="OT,OC" + input I ; + output OT ; + output OC ; +endmodule + +module OBZ (I, T, O); //synthesis syn_black_box syn_lib_cell=1 black_box_pad_pin="O" + input I ; + input T ; + output O ; +endmodule + +module OBZPU (I, T, O); //synthesis syn_black_box syn_lib_cell=1 black_box_pad_pin="O" + input I ; + input T ; + output O ; +endmodule + +module OFS1P3BX (D, SP, SCLK, PD, Q); //synthesis syn_black_box syn_lib_cell=1 + parameter GSR = "ENABLED"; + input D ; + input SP ; + input SCLK ; + input PD ; + output Q ; +endmodule + +module OFS1P3DX (D, SP, SCLK, CD, Q); //synthesis syn_black_box syn_lib_cell=1 + parameter GSR = "ENABLED"; + input D ; + input SP ; + input SCLK ; + input CD ; + output Q ; +endmodule + +module OFS1P3IX (D, SP, SCLK, CD, Q); //synthesis syn_black_box syn_lib_cell=1 + parameter GSR = "ENABLED"; + input D ; + input SP ; + input SCLK ; + input CD ; + output Q ; +endmodule + +module OFS1P3JX (D, SP, SCLK, PD, Q); //synthesis syn_black_box syn_lib_cell=1 + parameter GSR = "ENABLED"; + input D ; + input SP ; + input SCLK ; + input PD ; + output Q ; +endmodule + +module OLVDS (A, Z, ZN); //synthesis syn_black_box syn_lib_cell=1 black_box_pad_pin="Z,ZN" + input A; + output Z; + output ZN; +endmodule + +module OR2 (A, B, Z); //synthesis syn_black_box syn_lib_cell=1 + input A ; + input B ; + output Z ; +endmodule + +module OR3 (A, B, C, Z); //synthesis syn_black_box syn_lib_cell=1 + input A ; + input B ; + input C ; + output Z ; +endmodule + +module OR4 (A, B, C, D, Z); //synthesis syn_black_box syn_lib_cell=1 + input A ; + input B ; + input C ; + input D ; + output Z ; +endmodule + +module OR5 (A, B, C, D, E, Z); //synthesis syn_black_box syn_lib_cell=1 + input A ; + input B ; + input C ; + input D ; + input E ; + output Z ; +endmodule + +module PFUMX (ALUT, BLUT, C0, Z); //synthesis syn_black_box syn_lib_cell=1 + input ALUT ; + input BLUT ; + input C0 ; + output Z ; +endmodule + +module PUR (PUR)/* synthesis syn_black_box syn_lib_cell=1 syn_noprune=1 */; + parameter RST_PULSE = 1; + input PUR; +endmodule + +module ROM128X1A (AD6, AD5, AD4, AD3, AD2, AD1, AD0, DO0); //synthesis syn_black_box syn_lib_cell=1 + parameter [127:0] initval = 128'h00000000000000000000000000000000; + input AD6 ; + input AD5 ; + input AD4 ; + input AD3 ; + input AD2 ; + input AD1 ; + input AD0 ; + output DO0 ; +endmodule + +module ROM16X1A (AD3, AD2, AD1, AD0, DO0); //synthesis syn_black_box syn_lib_cell=1 + parameter [15:0] initval = 16'h0000; + input AD3 ; + input AD2 ; + input AD1 ; + input AD0 ; + output DO0 ; +endmodule + +module ROM256X1A (AD7, AD6, AD5, AD4, AD3, AD2, AD1, AD0, DO0); //synthesis syn_black_box syn_lib_cell=1 + parameter [255:0] initval = 256'h0000000000000000000000000000000000000000000000000000000000000000; + input AD7 ; + input AD6 ; + input AD5 ; + input AD4 ; + input AD3 ; + input AD2 ; + input AD1 ; + input AD0 ; + output DO0 ; +endmodule + +module ROM32X1A (AD4, AD3, AD2, AD1, AD0, DO0); //synthesis syn_black_box syn_lib_cell=1 + parameter [31:0] initval = 32'h00000000; + input AD4 ; + input AD3 ; + input AD2 ; + input AD1 ; + input AD0 ; + output DO0 ; +endmodule + +module ROM64X1A (AD5, AD4, AD3, AD2, AD1, AD0, DO0); //synthesis syn_black_box syn_lib_cell=1 + parameter [63:0] initval = 64'h0000000000000000; + input AD5 ; + input AD4 ; + input AD3 ; + input AD2 ; + input AD1 ; + input AD0 ; + output DO0 ; +endmodule + +module SGSR (GSR, CLK); //synthesis syn_black_box syn_lib_cell=1 syn_noprune=1 + input GSR, CLK; +endmodule + +module VHI (Z); //synthesis syn_black_box syn_lib_cell=1 + output Z ; +endmodule + +module VLO (Z); //synthesis syn_black_box syn_lib_cell=1 + output Z ; +endmodule + +module XNOR2 (A, B, Z); //synthesis syn_black_box syn_lib_cell=1 + input A ; + input B ; + output Z; +endmodule + +module XNOR3 (A, B, C, Z); //synthesis syn_black_box syn_lib_cell=1 + input A ; + input B ; + input C ; + output Z; +endmodule + +module XNOR4 (A, B, C, D, Z); //synthesis syn_black_box syn_lib_cell=1 + input A ; + input B ; + input C ; + input D ; + output Z; +endmodule + +module XNOR5 (A, B, C, D, E, Z); //synthesis syn_black_box syn_lib_cell=1 + input A ; + input B ; + input C ; + input D ; + input E ; + output Z; +endmodule + +module XOR11 (A, B, C, D, E, F, G, H, I, J, K, Z); //synthesis syn_black_box syn_lib_cell=1 + input A ; + input B ; + input C ; + input D ; + input E ; + input F ; + input G ; + input H ; + input I ; + input J ; + input K ; + output Z; +endmodule + +module XOR2 (A, B, Z); //synthesis syn_black_box syn_lib_cell=1 + input A ; + input B ; + output Z; +endmodule + +module XOR21 (A, B, C, D, E, F, G, H, I, J, K, L, M, N, O, P, Q, R, S, T, U, Z); //synthesis syn_black_box syn_lib_cell=1 + input A ; + input B ; + input C ; + input D ; + input E ; + input F ; + input G ; + input H ; + input I ; + input J ; + input K ; + input L ; + input M ; + input N ; + input O ; + input P ; + input Q ; + input R ; + input S ; + input T ; + input U ; + output Z ; +endmodule + +module XOR3 (A, B, C, Z); //synthesis syn_black_box syn_lib_cell=1 + input A ; + input B ; + input C ; + output Z; +endmodule + +module XOR4 (A, B, C, D, Z); //synthesis syn_black_box syn_lib_cell=1 + input A ; + input B ; + input C ; + input D ; + output Z; +endmodule + +module XOR5 (A, B, C, D, E, Z); //synthesis syn_black_box syn_lib_cell=1 + input A ; + input B ; + input C ; + input D ; + input E ; + output Z; +endmodule +// End of Basic Elements + +module DP16KD ( +input DIA17, DIA16, DIA15, DIA14, DIA13, DIA12, DIA11, DIA10, DIA9, + DIA8, DIA7, DIA6, DIA5, DIA4, DIA3, DIA2, DIA1, DIA0, + ADA13, ADA12, ADA11, ADA10, ADA9, ADA8, ADA7, ADA6, ADA5, + ADA4, ADA3, ADA2, ADA1, ADA0, + CEA, OCEA, CLKA, WEA, CSA2, CSA1, CSA0, RSTA, + DIB17, DIB16, DIB15, DIB14, DIB13, DIB12, DIB11, DIB10, DIB9, + DIB8, DIB7, DIB6, DIB5, DIB4, DIB3, DIB2, DIB1, DIB0, + ADB13, ADB12, ADB11, ADB10, ADB9, ADB8, ADB7, ADB6, ADB5, + ADB4, ADB3, ADB2, ADB1, ADB0, + CEB, OCEB, CLKB, WEB, CSB2, CSB1, CSB0, RSTB, +output DOA17, DOA16, DOA15, DOA14, DOA13, DOA12, DOA11, DOA10, DOA9, + DOA8, DOA7, DOA6, DOA5, DOA4, DOA3, DOA2, DOA1, DOA0, + DOB17, DOB16, DOB15, DOB14, DOB13, DOB12, DOB11, DOB10, DOB9, + DOB8, DOB7, DOB6, DOB5, DOB4, DOB3, DOB2, DOB1, DOB0 ); //synthesis syn_black_box syn_lib_cell=1 +parameter DATA_WIDTH_A = 18; +parameter DATA_WIDTH_B = 18; +parameter REGMODE_A = "NOREG"; +parameter REGMODE_B = "NOREG"; +parameter RESETMODE = "SYNC"; +parameter ASYNC_RESET_RELEASE = "SYNC"; +parameter WRITEMODE_A = "NORMAL"; +parameter WRITEMODE_B = "NORMAL"; +parameter CSDECODE_A = "0b000"; +parameter CSDECODE_B = "0b000"; +parameter GSR = "ENABLED"; +parameter INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_20 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_21 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_22 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_23 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_24 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_25 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_26 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_27 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_28 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_29 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_2A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_2B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_2C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_2D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_2E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_2F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_30 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_31 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_32 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_33 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_34 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_35 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_36 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_37 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_38 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_39 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_3A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_3B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_3C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_3D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_3E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_3F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INIT_DATA = "STATIC"; +endmodule + +module PDPW16KD ( +input DI35, DI34, DI33, DI32, DI31, DI30, DI29, DI28, DI27, + DI26, DI25, DI24, DI23, DI22, DI21, DI20, DI19, DI18, + DI17, DI16, DI15, DI14, DI13, DI12, DI11, DI10, DI9, + DI8, DI7, DI6, DI5, DI4, DI3, DI2, DI1, DI0, + ADW8, ADW7, ADW6, ADW5, ADW4, ADW3, ADW2, ADW1, ADW0, + BE3, BE2, BE1, BE0, + CEW, CLKW, CSW2, CSW1, CSW0, + ADR13, ADR12, ADR11, ADR10, ADR9, ADR8, ADR7, ADR6, ADR5, + ADR4, ADR3, ADR2, ADR1, ADR0, + CER, OCER, CLKR, CSR2, CSR1, CSR0, RST, +output DO35, DO34, DO33, DO32, DO31, DO30, DO29, DO28, DO27, + DO26, DO25, DO24, DO23, DO22, DO21, DO20, DO19, DO18, + DO17, DO16, DO15, DO14, DO13, DO12, DO11, DO10, DO9, + DO8, DO7, DO6, DO5, DO4, DO3, DO2, DO1, DO0 ); //synthesis syn_black_box syn_lib_cell=1 +parameter DATA_WIDTH_W = 36; +parameter DATA_WIDTH_R = 36; +parameter GSR = "ENABLED"; +parameter REGMODE = "NOREG"; +parameter RESETMODE = "SYNC"; +parameter ASYNC_RESET_RELEASE = "SYNC"; +parameter CSDECODE_W = "0b000"; +parameter CSDECODE_R = "0b000"; +parameter INITVAL_00 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_01 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_02 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_03 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_04 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_05 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_06 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_07 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_08 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_09 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_0A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_0B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_0C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_0D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_0E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_0F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_10 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_11 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_12 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_13 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_14 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_15 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_16 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_17 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_18 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_19 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_1A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_1B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_1C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_1D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_1E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_1F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_20 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_21 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_22 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_23 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_24 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_25 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_26 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_27 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_28 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_29 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_2A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_2B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_2C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_2D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_2E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_2F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_30 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_31 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_32 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_33 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_34 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_35 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_36 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_37 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_38 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_39 = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_3A = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_3B = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_3C = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_3D = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_3E = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INITVAL_3F = "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"; +parameter INIT_DATA = "STATIC"; +endmodule + +module DPR16X4C ( +input DI3, DI2, DI1, DI0, WAD3,WAD2,WAD1,WAD0, WCK, WRE, +input RAD3,RAD2,RAD1,RAD0, +output DO3, DO2, DO1, DO0 ); //synthesis syn_black_box syn_lib_cell=1 +parameter initval = "0x0000000000000000"; +endmodule + +module SPR16X4C ( +input DI3, DI2, DI1, DI0, AD3, AD2, AD1, AD0, CK, WRE, +output DO3, DO2, DO1, DO0 ); //synthesis syn_black_box syn_lib_cell=1 +parameter initval = "0x0000000000000000"; +endmodule + +module LVDSOB ( +input D, +input E, +output Q ); //synthesis syn_black_box syn_lib_cell=1 +endmodule + +module IMIPI ( +input A, AN, HSSEL, +output OHSOLS1, OLS0 ); //synthesis syn_black_box syn_lib_cell=1 black_box_pad_pin="A,AN" +endmodule + +module MULT9X9C ( +input A8,A7,A6,A5,A4,A3,A2,A1,A0, +input B8,B7,B6,B5,B4,B3,B2,B1,B0, +input SIGNEDA, SIGNEDB, SOURCEA, SOURCEB, +input CLK3,CLK2,CLK1,CLK0,CE3,CE2,CE1,CE0,RST3,RST2,RST1,RST0, +input SRIA8,SRIA7,SRIA6,SRIA5,SRIA4,SRIA3,SRIA2,SRIA1,SRIA0, +input SRIB8,SRIB7,SRIB6,SRIB5,SRIB4,SRIB3,SRIB2,SRIB1,SRIB0, +output SROA8,SROA7,SROA6,SROA5,SROA4,SROA3,SROA2,SROA1,SROA0, +output SROB8,SROB7,SROB6,SROB5,SROB4,SROB3,SROB2,SROB1,SROB0, +output ROA8,ROA7,ROA6,ROA5,ROA4,ROA3,ROA2,ROA1,ROA0, +output ROB8,ROB7,ROB6,ROB5,ROB4,ROB3,ROB2,ROB1,ROB0, +output P17,P16,P15,P14,P13,P12,P11,P10,P9,P8,P7,P6,P5,P4,P3,P2,P1,P0, +output SIGNEDP ); //synthesis syn_black_box syn_lib_cell=1 +parameter REG_INPUTA_CLK = "NONE"; +parameter REG_INPUTA_CE = "CE0"; +parameter REG_INPUTA_RST = "RST0"; +parameter REG_INPUTB_CLK = "NONE"; +parameter REG_INPUTB_CE = "CE0"; +parameter REG_INPUTB_RST = "RST0"; +parameter REG_PIPELINE_CLK = "NONE"; +parameter REG_PIPELINE_CE = "CE0"; +parameter REG_PIPELINE_RST = "RST0"; +parameter REG_OUTPUT_CLK = "NONE"; +parameter REG_OUTPUT_CE = "CE0"; +parameter REG_OUTPUT_RST = "RST0"; +parameter GSR = "ENABLED"; +parameter CAS_MATCH_REG = "FALSE"; +parameter MULT_BYPASS = "DISABLED"; +parameter RESETMODE = "SYNC"; +endmodule + +module MULT9X9D ( +input A8,A7,A6,A5,A4,A3,A2,A1,A0, +input B8,B7,B6,B5,B4,B3,B2,B1,B0, +input C8,C7,C6,C5,C4,C3,C2,C1,C0, +input SIGNEDA, SIGNEDB, SOURCEA, SOURCEB, +input CLK3,CLK2,CLK1,CLK0,CE3,CE2,CE1,CE0,RST3,RST2,RST1,RST0, +input SRIA8,SRIA7,SRIA6,SRIA5,SRIA4,SRIA3,SRIA2,SRIA1,SRIA0, +input SRIB8,SRIB7,SRIB6,SRIB5,SRIB4,SRIB3,SRIB2,SRIB1,SRIB0, +output SROA8,SROA7,SROA6,SROA5,SROA4,SROA3,SROA2,SROA1,SROA0, +output SROB8,SROB7,SROB6,SROB5,SROB4,SROB3,SROB2,SROB1,SROB0, +output ROA8,ROA7,ROA6,ROA5,ROA4,ROA3,ROA2,ROA1,ROA0, +output ROB8,ROB7,ROB6,ROB5,ROB4,ROB3,ROB2,ROB1,ROB0, +output ROC8,ROC7,ROC6,ROC5,ROC4,ROC3,ROC2,ROC1,ROC0, +output P17,P16,P15,P14,P13,P12,P11,P10,P9,P8,P7,P6,P5,P4,P3,P2,P1,P0, +output SIGNEDP ); //synthesis syn_black_box syn_lib_cell=1 +parameter REG_INPUTA_CLK = "NONE"; +parameter REG_INPUTA_CE = "CE0"; +parameter REG_INPUTA_RST = "RST0"; +parameter REG_INPUTB_CLK = "NONE"; +parameter REG_INPUTB_CE = "CE0"; +parameter REG_INPUTB_RST = "RST0"; +parameter REG_INPUTC_CLK = "NONE"; +parameter REG_INPUTC_CE = "CE0"; +parameter REG_INPUTC_RST = "RST0"; +parameter REG_PIPELINE_CLK = "NONE"; +parameter REG_PIPELINE_CE = "CE0"; +parameter REG_PIPELINE_RST = "RST0"; +parameter REG_OUTPUT_CLK = "NONE"; +parameter REG_OUTPUT_CE = "CE0"; +parameter REG_OUTPUT_RST = "RST0"; +parameter CLK0_DIV = "ENABLED"; +parameter CLK1_DIV = "ENABLED"; +parameter CLK2_DIV = "ENABLED"; +parameter CLK3_DIV = "ENABLED"; +parameter HIGHSPEED_CLK = "NONE"; +parameter GSR = "ENABLED"; +parameter CAS_MATCH_REG = "FALSE"; +parameter SOURCEB_MODE = "B_SHIFT"; +parameter MULT_BYPASS = "DISABLED"; +parameter RESETMODE = "SYNC"; +endmodule + +module MULT18X18C ( +input A17,A16,A15,A14,A13,A12,A11,A10,A9,A8,A7,A6,A5,A4,A3,A2,A1,A0, +input B17,B16,B15,B14,B13,B12,B11,B10,B9,B8,B7,B6,B5,B4,B3,B2,B1,B0, +input SIGNEDA, SIGNEDB, SOURCEA, SOURCEB, +input CLK3,CLK2,CLK1,CLK0,CE3,CE2,CE1,CE0,RST3,RST2,RST1,RST0, +input SRIA17,SRIA16,SRIA15,SRIA14,SRIA13,SRIA12,SRIA11,SRIA10,SRIA9, +input SRIA8,SRIA7,SRIA6,SRIA5,SRIA4,SRIA3,SRIA2,SRIA1,SRIA0, +input SRIB17,SRIB16,SRIB15,SRIB14,SRIB13,SRIB12,SRIB11,SRIB10,SRIB9, +input SRIB8,SRIB7,SRIB6,SRIB5,SRIB4,SRIB3,SRIB2,SRIB1,SRIB0, +output SROA17,SROA16,SROA15,SROA14,SROA13,SROA12,SROA11,SROA10,SROA9, +output SROA8,SROA7,SROA6,SROA5,SROA4,SROA3,SROA2,SROA1,SROA0, +output SROB17,SROB16,SROB15,SROB14,SROB13,SROB12,SROB11,SROB10,SROB9, +output SROB8,SROB7,SROB6,SROB5,SROB4,SROB3,SROB2,SROB1,SROB0, +output ROA17,ROA16,ROA15,ROA14,ROA13,ROA12,ROA11,ROA10,ROA9, +output ROA8,ROA7,ROA6,ROA5,ROA4,ROA3,ROA2,ROA1,ROA0, +output ROB17,ROB16,ROB15,ROB14,ROB13,ROB12,ROB11,ROB10,ROB9, +output ROB8,ROB7,ROB6,ROB5,ROB4,ROB3,ROB2,ROB1,ROB0, +output P35,P34,P33,P32,P31,P30,P29,P28,P27,P26,P25,P24,P23,P22,P21,P20,P19,P18, +output P17,P16,P15,P14,P13,P12,P11,P10,P9,P8,P7,P6,P5,P4,P3,P2,P1,P0, +output SIGNEDP ); //synthesis syn_black_box syn_lib_cell=1 +parameter REG_INPUTA_CLK = "NONE"; +parameter REG_INPUTA_CE = "CE0"; +parameter REG_INPUTA_RST = "RST0"; +parameter REG_INPUTB_CLK = "NONE"; +parameter REG_INPUTB_CE = "CE0"; +parameter REG_INPUTB_RST = "RST0"; +parameter REG_PIPELINE_CLK = "NONE"; +parameter REG_PIPELINE_CE = "CE0"; +parameter REG_PIPELINE_RST = "RST0"; +parameter REG_OUTPUT_CLK = "NONE"; +parameter REG_OUTPUT_CE = "CE0"; +parameter REG_OUTPUT_RST = "RST0"; +parameter CAS_MATCH_REG = "FALSE"; +parameter MULT_BYPASS = "DISABLED"; +parameter GSR = "ENABLED"; +parameter RESETMODE = "SYNC"; +endmodule + +module MULT18X18D ( +input A17,A16,A15,A14,A13,A12,A11,A10,A9,A8,A7,A6,A5,A4,A3,A2,A1,A0, +input B17,B16,B15,B14,B13,B12,B11,B10,B9,B8,B7,B6,B5,B4,B3,B2,B1,B0, +input C17,C16,C15,C14,C13,C12,C11,C10,C9,C8,C7,C6,C5,C4,C3,C2,C1,C0, +input SIGNEDA, SIGNEDB, SOURCEA, SOURCEB, +input CLK3,CLK2,CLK1,CLK0,CE3,CE2,CE1,CE0,RST3,RST2,RST1,RST0, +input SRIA17,SRIA16,SRIA15,SRIA14,SRIA13,SRIA12,SRIA11,SRIA10,SRIA9, +input SRIA8,SRIA7,SRIA6,SRIA5,SRIA4,SRIA3,SRIA2,SRIA1,SRIA0, +input SRIB17,SRIB16,SRIB15,SRIB14,SRIB13,SRIB12,SRIB11,SRIB10,SRIB9, +input SRIB8,SRIB7,SRIB6,SRIB5,SRIB4,SRIB3,SRIB2,SRIB1,SRIB0, +output SROA17,SROA16,SROA15,SROA14,SROA13,SROA12,SROA11,SROA10,SROA9, +output SROA8,SROA7,SROA6,SROA5,SROA4,SROA3,SROA2,SROA1,SROA0, +output SROB17,SROB16,SROB15,SROB14,SROB13,SROB12,SROB11,SROB10,SROB9, +output SROB8,SROB7,SROB6,SROB5,SROB4,SROB3,SROB2,SROB1,SROB0, +output ROA17,ROA16,ROA15,ROA14,ROA13,ROA12,ROA11,ROA10,ROA9, +output ROA8,ROA7,ROA6,ROA5,ROA4,ROA3,ROA2,ROA1,ROA0, +output ROB17,ROB16,ROB15,ROB14,ROB13,ROB12,ROB11,ROB10,ROB9, +output ROB8,ROB7,ROB6,ROB5,ROB4,ROB3,ROB2,ROB1,ROB0, +output ROC17,ROC16,ROC15,ROC14,ROC13,ROC12,ROC11,ROC10,ROC9, +output ROC8,ROC7,ROC6,ROC5,ROC4,ROC3,ROC2,ROC1,ROC0, +output P35,P34,P33,P32,P31,P30,P29,P28,P27,P26,P25,P24,P23,P22,P21,P20,P19,P18, +output P17,P16,P15,P14,P13,P12,P11,P10,P9,P8,P7,P6,P5,P4,P3,P2,P1,P0, +output SIGNEDP ); //synthesis syn_black_box syn_lib_cell=1 +parameter REG_INPUTA_CLK = "NONE"; +parameter REG_INPUTA_CE = "CE0"; +parameter REG_INPUTA_RST = "RST0"; +parameter REG_INPUTB_CLK = "NONE"; +parameter REG_INPUTB_CE = "CE0"; +parameter REG_INPUTB_RST = "RST0"; +parameter REG_INPUTC_CLK = "NONE"; +parameter REG_INPUTC_CE = "CE0"; +parameter REG_INPUTC_RST = "RST0"; +parameter REG_PIPELINE_CLK = "NONE"; +parameter REG_PIPELINE_CE = "CE0"; +parameter REG_PIPELINE_RST = "RST0"; +parameter REG_OUTPUT_CLK = "NONE"; +parameter REG_OUTPUT_CE = "CE0"; +parameter REG_OUTPUT_RST = "RST0"; +parameter CLK0_DIV = "ENABLED"; +parameter CLK1_DIV = "ENABLED"; +parameter CLK2_DIV = "ENABLED"; +parameter CLK3_DIV = "ENABLED"; +parameter HIGHSPEED_CLK = "NONE"; +parameter GSR = "ENABLED"; +parameter CAS_MATCH_REG = "FALSE"; +parameter SOURCEB_MODE = "B_SHIFT"; +parameter MULT_BYPASS = "DISABLED"; +parameter RESETMODE = "SYNC"; +endmodule + +module ALU24A ( +input CE3,CE2,CE1,CE0,CLK3,CLK2,CLK1,CLK0,RST3,RST2,RST1,RST0,SIGNEDIA,SIGNEDIB, +input MA17,MA16,MA15,MA14,MA13,MA12,MA11,MA10,MA9,MA8,MA7,MA6,MA5,MA4,MA3,MA2,MA1,MA0, +input MB17,MB16,MB15,MB14,MB13,MB12,MB11,MB10,MB9,MB8,MB7,MB6,MB5,MB4,MB3,MB2,MB1,MB0, +input CIN23,CIN22,CIN21,CIN20,CIN19,CIN18,CIN17,CIN16,CIN15,CIN14, +input CIN13,CIN12,CIN11,CIN10,CIN9,CIN8,CIN7,CIN6,CIN5,CIN4,CIN3,CIN2,CIN1,CIN0, +input OPADDNSUB, OPCINSEL, +output R23,R22,R21,R20,R19,R18, +output R17,R16,R15,R14,R13,R12,R11,R10,R9,R8,R7,R6,R5,R4,R3,R2,R1,R0 ); //synthesis syn_black_box syn_lib_cell=1 +parameter REG_OUTPUT_CLK = "NONE"; +parameter REG_OUTPUT_CE = "CE0"; +parameter REG_OUTPUT_RST = "RST0"; +parameter REG_OPCODE_0_CLK = "NONE"; +parameter REG_OPCODE_0_CE = "CE0"; +parameter REG_OPCODE_0_RST = "RST0"; +parameter REG_OPCODE_1_CLK = "NONE"; +parameter REG_OPCODE_1_CE = "CE0"; +parameter REG_OPCODE_1_RST = "RST0"; +parameter GSR = "ENABLED"; +parameter RESETMODE = "SYNC"; +endmodule + +module ALU54A ( +input CE3,CE2,CE1,CE0,CLK3,CLK2,CLK1,CLK0,RST3,RST2,RST1,RST0,SIGNEDIA,SIGNEDIB,SIGNEDCIN, +input A35,A34,A33,A32,A31,A30,A29,A28,A27,A26,A25,A24,A23,A22,A21,A20,A19,A18, +input A17,A16,A15,A14,A13,A12,A11,A10,A9,A8,A7,A6,A5,A4,A3,A2,A1,A0, +input B35,B34,B33,B32,B31,B30,B29,B28,B27,B26,B25,B24,B23,B22,B21,B20,B19,B18, +input B17,B16,B15,B14,B13,B12,B11,B10,B9,B8,B7,B6,B5,B4,B3,B2,B1,B0, +input C53,C52,C51,C50,C49,C48,C47,C46,C45,C44,C43,C42,C41,C40,C39,C38,C37,C36, +input C35,C34,C33,C32,C31,C30,C29,C28,C27,C26,C25,C24,C23,C22,C21,C20,C19,C18, +input C17,C16,C15,C14,C13,C12,C11,C10,C9,C8,C7,C6,C5,C4,C3,C2,C1,C0, +input MA35,MA34,MA33,MA32,MA31,MA30,MA29,MA28,MA27,MA26,MA25,MA24,MA23,MA22,MA21,MA20,MA19,MA18, +input MA17,MA16,MA15,MA14,MA13,MA12,MA11,MA10,MA9,MA8,MA7,MA6,MA5,MA4,MA3,MA2,MA1,MA0, +input MB35,MB34,MB33,MB32,MB31,MB30,MB29,MB28,MB27,MB26,MB25,MB24,MB23,MB22,MB21,MB20,MB19,MB18, +input MB17,MB16,MB15,MB14,MB13,MB12,MB11,MB10,MB9,MB8,MB7,MB6,MB5,MB4,MB3,MB2,MB1,MB0, +input CIN53,CIN52,CIN51,CIN50,CIN49,CIN48,CIN47,CIN46,CIN45,CIN44,CIN43,CIN42,CIN41,CIN40,CIN39, +input CIN38,CIN37,CIN36,CIN35,CIN34,CIN33,CIN32,CIN31,CIN30,CIN29,CIN28, +input CIN27,CIN26,CIN25,CIN24,CIN23,CIN22,CIN21,CIN20,CIN19,CIN18,CIN17,CIN16,CIN15,CIN14, +input CIN13,CIN12,CIN11,CIN10,CIN9,CIN8,CIN7,CIN6,CIN5,CIN4,CIN3,CIN2,CIN1,CIN0, +input OP10,OP9,OP8,OP7,OP6,OP5,OP4,OP3,OP2,OP1,OP0, +output R53,R52,R51,R50,R49,R48,R47,R46,R45,R44,R43,R42,R41,R40,R39,R38,R37,R36, +output R35,R34,R33,R32,R31,R30,R29,R28,R27,R26,R25,R24,R23,R22,R21,R20,R19,R18, +output R17,R16,R15,R14,R13,R12,R11,R10,R9,R8,R7,R6,R5,R4,R3,R2,R1,R0, +output EQZ,EQZM,EQOM,EQPAT,EQPATB,OVER,UNDER,OVERUNDER, +output SIGNEDR ); //synthesis syn_black_box syn_lib_cell=1 +parameter REG_INPUTC0_CLK = "NONE"; // C[26:0] +parameter REG_INPUTC0_CE = "CE0"; // C[26:0] +parameter REG_INPUTC0_RST = "RST0"; // C[26:0] +parameter REG_INPUTC1_CLK = "NONE"; // C[53:27] +parameter REG_INPUTC1_CE = "CE0"; // C[53:27] +parameter REG_INPUTC1_RST = "RST0"; // C[53:27] +parameter REG_OPCODEOP0_0_CLK = "NONE"; // Input reg of OPCODE oper[0] +parameter REG_OPCODEOP0_0_CE = "CE0"; // Input reg of OPCODE oper[3:0] +parameter REG_OPCODEOP0_0_RST = "RST0"; // Input reg of OPCODE oper[3:0] +parameter REG_OPCODEOP1_0_CLK = "NONE"; // Input reg of OPCODE oper [3:1] +parameter REG_OPCODEOP0_1_CLK = "NONE"; // Pipeline reg of OPCODE oper[0] +parameter REG_OPCODEOP0_1_CE = "CE0"; // Pipeline reg of OPCODE oper[3:0] +parameter REG_OPCODEOP0_1_RST = "RST0"; // Pipeline reg of OPCODE oper[3:0] +parameter REG_OPCODEOP1_1_CLK = "NONE"; // Pipeline reg of OPCODE oper[3:1] +parameter REG_OPCODEIN_0_CLK = "NONE"; // Input reg of OPCODE InA[1:0], InB[1:0] and InC[2:0] +parameter REG_OPCODEIN_0_CE = "CE0"; // Input reg of OPCODE InA[1:0], InB[1:0] and InC[2:0] +parameter REG_OPCODEIN_0_RST = "RST0"; // Input reg of OPCODE InA[1:0], InB[1:0] and InC[2:0] +parameter REG_OPCODEIN_1_CLK = "NONE"; // Pipeline reg of OPCODE InA[1:0], InB[1:0] and InC[2:0] +parameter REG_OPCODEIN_1_CE = "CE0"; // Pipeline reg of OPCODE InA[1:0], InB[1:0] and InC[2:0] +parameter REG_OPCODEIN_1_RST = "RST0"; // Pipeline reg of OPCODE InA[1:0], InB[1:0] and InC[2:0] +parameter REG_OUTPUT0_CLK = "NONE"; +parameter REG_OUTPUT0_CE = "CE0"; +parameter REG_OUTPUT0_RST = "RST0"; +parameter REG_OUTPUT1_CLK = "NONE"; +parameter REG_OUTPUT1_CE = "CE0"; +parameter REG_OUTPUT1_RST = "RST0"; +parameter REG_FLAG_CLK = "NONE"; +parameter REG_FLAG_CE = "CE0"; +parameter REG_FLAG_RST = "RST0"; +parameter MCPAT_SOURCE = "STATIC"; +parameter MASKPAT_SOURCE = "STATIC"; +parameter MASK01 = "0x00000000000000"; +parameter MCPAT = "0x00000000000000"; +parameter MASKPAT = "0x00000000000000"; +parameter RNDPAT = "0x00000000000000"; +parameter GSR = "ENABLED"; +parameter RESETMODE = "SYNC"; +parameter MULT9_MODE = "DISABLED"; +parameter FORCE_ZERO_BARREL_SHIFT = "DISABLED"; +parameter LEGACY = "DISABLED"; +endmodule + +module ALU24B ( +input CE3,CE2,CE1,CE0,CLK3,CLK2,CLK1,CLK0,RST3,RST2,RST1,RST0,SIGNEDIA,SIGNEDIB, +input MA17,MA16,MA15,MA14,MA13,MA12,MA11,MA10,MA9,MA8,MA7,MA6,MA5,MA4,MA3,MA2,MA1,MA0, +input MB17,MB16,MB15,MB14,MB13,MB12,MB11,MB10,MB9,MB8,MB7,MB6,MB5,MB4,MB3,MB2,MB1,MB0, +input CFB23,CFB22,CFB21,CFB20,CFB19,CFB18,CFB17,CFB16,CFB15,CFB14, +input CFB13,CFB12,CFB11,CFB10,CFB9,CFB8,CFB7,CFB6,CFB5,CFB4,CFB3,CFB2,CFB1,CFB0, +input CIN23,CIN22,CIN21,CIN20,CIN19,CIN18,CIN17,CIN16,CIN15,CIN14, +input CIN13,CIN12,CIN11,CIN10,CIN9,CIN8,CIN7,CIN6,CIN5,CIN4,CIN3,CIN2,CIN1,CIN0, +input OPADDNSUB, OPCINSEL, +output R23,R22,R21,R20,R19,R18, +output R17,R16,R15,R14,R13,R12,R11,R10,R9,R8,R7,R6,R5,R4,R3,R2,R1,R0, +output CO23,CO22,CO21,CO20,CO19,CO18, +output CO17,CO16,CO15,CO14,CO13,CO12,CO11,CO10,CO9,CO8,CO7,CO6,CO5,CO4,CO3,CO2,CO1,CO0 ); //synthesis syn_black_box syn_lib_cell=1 +parameter REG_OUTPUT_CLK = "NONE"; +parameter REG_OUTPUT_CE = "CE0"; +parameter REG_OUTPUT_RST = "RST0"; +parameter REG_OPCODE_0_CLK = "NONE"; +parameter REG_OPCODE_0_CE = "CE0"; +parameter REG_OPCODE_0_RST = "RST0"; +parameter REG_OPCODE_1_CLK = "NONE"; +parameter REG_OPCODE_1_CE = "CE0"; +parameter REG_OPCODE_1_RST = "RST0"; +parameter REG_INPUTCFB_CLK = "NONE"; +parameter REG_INPUTCFB_CE = "CE0"; +parameter REG_INPUTCFB_RST = "RST0"; +parameter CLK0_DIV = "ENABLED"; +parameter CLK1_DIV = "ENABLED"; +parameter CLK2_DIV = "ENABLED"; +parameter CLK3_DIV = "ENABLED"; +parameter GSR = "ENABLED"; +parameter RESETMODE = "SYNC"; +endmodule + +module ALU54B ( +input CE3,CE2,CE1,CE0,CLK3,CLK2,CLK1,CLK0,RST3,RST2,RST1,RST0,SIGNEDIA,SIGNEDIB,SIGNEDCIN, +input A35,A34,A33,A32,A31,A30,A29,A28,A27,A26,A25,A24,A23,A22,A21,A20,A19,A18, +input A17,A16,A15,A14,A13,A12,A11,A10,A9,A8,A7,A6,A5,A4,A3,A2,A1,A0, +input B35,B34,B33,B32,B31,B30,B29,B28,B27,B26,B25,B24,B23,B22,B21,B20,B19,B18, +input B17,B16,B15,B14,B13,B12,B11,B10,B9,B8,B7,B6,B5,B4,B3,B2,B1,B0, +input C53,C52,C51,C50,C49,C48,C47,C46,C45,C44,C43,C42,C41,C40,C39,C38,C37,C36, +input C35,C34,C33,C32,C31,C30,C29,C28,C27,C26,C25,C24,C23,C22,C21,C20,C19,C18, +input C17,C16,C15,C14,C13,C12,C11,C10,C9,C8,C7,C6,C5,C4,C3,C2,C1,C0, +input CFB53,CFB52,CFB51,CFB50,CFB49,CFB48,CFB47,CFB46,CFB45,CFB44,CFB43,CFB42,CFB41, +input CFB40,CFB39,CFB38,CFB37,CFB36,CFB35,CFB34,CFB33,CFB32,CFB31,CFB30,CFB29,CFB28, +input CFB27,CFB26,CFB25,CFB24,CFB23,CFB22,CFB21,CFB20,CFB19,CFB18,CFB17,CFB16,CFB15, +input CFB14,CFB13,CFB12,CFB11,CFB10,CFB9,CFB8,CFB7,CFB6,CFB5,CFB4,CFB3,CFB2,CFB1,CFB0, +input MA35,MA34,MA33,MA32,MA31,MA30,MA29,MA28,MA27,MA26,MA25,MA24,MA23,MA22,MA21,MA20,MA19,MA18, +input MA17,MA16,MA15,MA14,MA13,MA12,MA11,MA10,MA9,MA8,MA7,MA6,MA5,MA4,MA3,MA2,MA1,MA0, +input MB35,MB34,MB33,MB32,MB31,MB30,MB29,MB28,MB27,MB26,MB25,MB24,MB23,MB22,MB21,MB20,MB19,MB18, +input MB17,MB16,MB15,MB14,MB13,MB12,MB11,MB10,MB9,MB8,MB7,MB6,MB5,MB4,MB3,MB2,MB1,MB0, +input CIN53,CIN52,CIN51,CIN50,CIN49,CIN48,CIN47,CIN46,CIN45,CIN44,CIN43,CIN42,CIN41, +input CIN40,CIN39,CIN38,CIN37,CIN36,CIN35,CIN34,CIN33,CIN32,CIN31,CIN30,CIN29,CIN28, +input CIN27,CIN26,CIN25,CIN24,CIN23,CIN22,CIN21,CIN20,CIN19,CIN18,CIN17,CIN16,CIN15, +input CIN14,CIN13,CIN12,CIN11,CIN10,CIN9,CIN8,CIN7,CIN6,CIN5,CIN4,CIN3,CIN2,CIN1,CIN0, +input OP10,OP9,OP8,OP7,OP6,OP5,OP4,OP3,OP2,OP1,OP0, +output R53,R52,R51,R50,R49,R48,R47,R46,R45,R44,R43,R42,R41,R40,R39,R38,R37,R36, +output R35,R34,R33,R32,R31,R30,R29,R28,R27,R26,R25,R24,R23,R22,R21,R20,R19,R18, +output R17,R16,R15,R14,R13,R12,R11,R10,R9,R8,R7,R6,R5,R4,R3,R2,R1,R0, +output CO53,CO52,CO51,CO50,CO49,CO48,CO47,CO46,CO45,CO44,CO43,CO42,CO41,CO40,CO39,CO38,CO37,CO36, +output CO35,CO34,CO33,CO32,CO31,CO30,CO29,CO28,CO27,CO26,CO25,CO24,CO23,CO22,CO21,CO20,CO19,CO18, +output CO17,CO16,CO15,CO14,CO13,CO12,CO11,CO10,CO9,CO8,CO7,CO6,CO5,CO4,CO3,CO2,CO1,CO0, +output EQZ,EQZM,EQOM,EQPAT,EQPATB,OVER,UNDER,OVERUNDER, +output SIGNEDR ); //synthesis syn_black_box syn_lib_cell=1 +parameter REG_INPUTC0_CLK = "NONE"; // C[26:0] +parameter REG_INPUTC0_CE = "CE0"; // C[26:0] +parameter REG_INPUTC0_RST = "RST0"; // C[26:0] +parameter REG_INPUTC1_CLK = "NONE"; // C[53:27] +parameter REG_INPUTC1_CE = "CE0"; // C[53:27] +parameter REG_INPUTC1_RST = "RST0"; // C[53:27] +parameter REG_OPCODEOP0_0_CLK = "NONE"; // Input reg of OPCODE oper[0] +parameter REG_OPCODEOP0_0_CE = "CE0"; // Input reg of OPCODE oper[3:0] +parameter REG_OPCODEOP0_0_RST = "RST0"; // Input reg of OPCODE oper[3:0] +parameter REG_OPCODEOP1_0_CLK = "NONE"; // Input reg of OPCODE oper [3:1] +parameter REG_OPCODEOP0_1_CLK = "NONE"; // Pipeline reg of OPCODE oper[0] +parameter REG_OPCODEOP0_1_CE = "CE0"; // Pipeline reg of OPCODE oper[3:0] +parameter REG_OPCODEOP0_1_RST = "RST0"; // Pipeline reg of OPCODE oper[3:0] +parameter REG_OPCODEOP1_1_CLK = "NONE"; // Pipeline reg of OPCODE oper[3:1] +parameter REG_OPCODEIN_0_CLK = "NONE"; // Input reg of OPCODE InA[1:0], InB[1:0] and InC[2:0] +parameter REG_OPCODEIN_0_CE = "CE0"; // Input reg of OPCODE InA[1:0], InB[1:0] and InC[2:0] +parameter REG_OPCODEIN_0_RST = "RST0"; // Input reg of OPCODE InA[1:0], InB[1:0] and InC[2:0] +parameter REG_OPCODEIN_1_CLK = "NONE"; // Pipeline reg of OPCODE InA[1:0], InB[1:0] and InC[2:0] +parameter REG_OPCODEIN_1_CE = "CE0"; // Pipeline reg of OPCODE InA[1:0], InB[1:0] and InC[2:0] +parameter REG_OPCODEIN_1_RST = "RST0"; // Pipeline reg of OPCODE InA[1:0], InB[1:0] and InC[2:0] +parameter REG_OUTPUT0_CLK = "NONE"; +parameter REG_OUTPUT0_CE = "CE0"; +parameter REG_OUTPUT0_RST = "RST0"; +parameter REG_OUTPUT1_CLK = "NONE"; +parameter REG_OUTPUT1_CE = "CE0"; +parameter REG_OUTPUT1_RST = "RST0"; +parameter REG_FLAG_CLK = "NONE"; +parameter REG_FLAG_CE = "CE0"; +parameter REG_FLAG_RST = "RST0"; +parameter MCPAT_SOURCE = "STATIC"; +parameter MASKPAT_SOURCE = "STATIC"; +parameter MASK01 = "0x00000000000000"; +parameter REG_INPUTCFB_CLK = "NONE"; +parameter REG_INPUTCFB_CE = "CE0"; +parameter REG_INPUTCFB_RST = "RST0"; +parameter CLK0_DIV = "ENABLED"; +parameter CLK1_DIV = "ENABLED"; +parameter CLK2_DIV = "ENABLED"; +parameter CLK3_DIV = "ENABLED"; +parameter MCPAT = "0x00000000000000"; +parameter MASKPAT = "0x00000000000000"; +parameter RNDPAT = "0x00000000000000"; +parameter GSR = "ENABLED"; +parameter RESETMODE = "SYNC"; +parameter MULT9_MODE = "DISABLED"; +parameter FORCE_ZERO_BARREL_SHIFT = "DISABLED"; +parameter LEGACY = "DISABLED"; +endmodule + +module PRADD9A ( +input PA8,PA7,PA6,PA5,PA4,PA3,PA2,PA1,PA0, +input PB8,PB7,PB6,PB5,PB4,PB3,PB2,PB1,PB0, +input SRIA8,SRIA7,SRIA6,SRIA5,SRIA4,SRIA3,SRIA2,SRIA1,SRIA0, +input SRIB8,SRIB7,SRIB6,SRIB5,SRIB4,SRIB3,SRIB2,SRIB1,SRIB0, +input C8,C7,C6,C5,C4,C3,C2,C1,C0, +input SOURCEA,OPPRE, +input CLK3,CLK2,CLK1,CLK0, +input CE3,CE2,CE1,CE0, +input RST3,RST2,RST1,RST0, +output SROA8,SROA7,SROA6,SROA5,SROA4,SROA3,SROA2,SROA1,SROA0, +output SROB8,SROB7,SROB6,SROB5,SROB4,SROB3,SROB2,SROB1,SROB0, +output PO8,PO7,PO6,PO5,PO4,PO3,PO2,PO1,PO0 ); //synthesis syn_black_box syn_lib_cell=1 +parameter REG_INPUTA_CLK = "NONE"; +parameter REG_INPUTA_CE = "CE0"; +parameter REG_INPUTA_RST = "RST0"; +parameter REG_INPUTB_CLK = "NONE"; +parameter REG_INPUTB_CE = "CE0"; +parameter REG_INPUTB_RST = "RST0"; +parameter REG_INPUTC_CLK = "NONE"; +parameter REG_INPUTC_CE = "CE0"; +parameter REG_INPUTC_RST = "RST0"; +parameter REG_OPPRE_CLK = "NONE"; +parameter REG_OPPRE_CE = "CE0"; +parameter REG_OPPRE_RST = "RST0"; +parameter CLK0_DIV = "ENABLED"; +parameter CLK1_DIV = "ENABLED"; +parameter CLK2_DIV = "ENABLED"; +parameter CLK3_DIV = "ENABLED"; +parameter HIGHSPEED_CLK = "NONE"; +parameter GSR = "ENABLED"; +parameter CAS_MATCH_REG = "FALSE"; +parameter SOURCEA_MODE = "A_SHIFT"; +parameter SOURCEB_MODE = "SHIFT"; +parameter FB_MUX = "SHIFT"; +parameter RESETMODE = "SYNC"; +parameter SYMMETRY_MODE = "DIRECT"; +endmodule + +module PRADD18A ( +input PA17,PA16,PA15,PA14,PA13,PA12,PA11,PA10,PA9,PA8,PA7,PA6, + PA5,PA4,PA3,PA2,PA1,PA0, +input PB17,PB16,PB15,PB14,PB13,PB12,PB11,PB10,PB9,PB8,PB7,PB6, + PB5,PB4,PB3,PB2,PB1,PB0, +input SRIA17,SRIA16,SRIA15,SRIA14,SRIA13,SRIA12,SRIA11,SRIA10,SRIA9,SRIA8,SRIA7,SRIA6, + SRIA5,SRIA4,SRIA3,SRIA2,SRIA1,SRIA0, +input SRIB17,SRIB16,SRIB15,SRIB14,SRIB13,SRIB12,SRIB11,SRIB10,SRIB9,SRIB8,SRIB7,SRIB6, + SRIB5,SRIB4,SRIB3,SRIB2,SRIB1,SRIB0, +input C17,C16,C15,C14,C13,C12,C11,C10,C9,C8,C7,C6,C5,C4,C3,C2,C1,C0, +input SOURCEA,OPPRE, +input CLK3,CLK2,CLK1,CLK0, +input CE3,CE2,CE1,CE0, +input RST3,RST2,RST1,RST0, +output SROA17,SROA16,SROA15,SROA14,SROA13,SROA12,SROA11,SROA10,SROA9,SROA8,SROA7,SROA6, + SROA5,SROA4,SROA3,SROA2,SROA1,SROA0, +output SROB17,SROB16,SROB15,SROB14,SROB13,SROB12,SROB11,SROB10,SROB9,SROB8,SROB7,SROB6, + SROB5,SROB4,SROB3,SROB2,SROB1,SROB0, +output PO17,PO16,PO15,PO14,PO13,PO12,PO11,PO10,PO9,PO8,PO7,PO6, + PO5,PO4,PO3,PO2,PO1,PO0 ); //synthesis syn_black_box syn_lib_cell=1 +parameter REG_INPUTA_CLK = "NONE"; +parameter REG_INPUTA_CE = "CE0"; +parameter REG_INPUTA_RST = "RST0"; +parameter REG_INPUTB_CLK = "NONE"; +parameter REG_INPUTB_CE = "CE0"; +parameter REG_INPUTB_RST = "RST0"; +parameter REG_INPUTC_CLK = "NONE"; +parameter REG_INPUTC_CE = "CE0"; +parameter REG_INPUTC_RST = "RST0"; +parameter REG_OPPRE_CLK = "NONE"; +parameter REG_OPPRE_CE = "CE0"; +parameter REG_OPPRE_RST = "RST0"; +parameter CLK0_DIV = "ENABLED"; +parameter CLK1_DIV = "ENABLED"; +parameter CLK2_DIV = "ENABLED"; +parameter CLK3_DIV = "ENABLED"; +parameter HIGHSPEED_CLK = "NONE"; +parameter GSR = "ENABLED"; +parameter CAS_MATCH_REG = "FALSE"; +parameter SOURCEA_MODE = "A_SHIFT"; +parameter SOURCEB_MODE = "SHIFT"; +parameter FB_MUX = "SHIFT"; +parameter RESETMODE = "SYNC"; +parameter SYMMETRY_MODE = "DIRECT"; +endmodule + +module BCINRD ( +input INRDENI ); //synthesis syn_black_box syn_lib_cell=1 syn_noprune=1 +parameter BANKID=2; +endmodule + +module BCLVDSOB ( +input LVDSENI ); //synthesis syn_black_box syn_lib_cell=1 syn_noprune=1 +parameter BANKID=2; +endmodule + +module INRDB ( +input D, +input E, +output Q ); //synthesis syn_black_box syn_lib_cell=1 +endmodule + +module CLKDIVF ( +input CLKI, RST, ALIGNWD, +output CDIVX ); //synthesis syn_black_box syn_lib_cell=1 +parameter GSR = "DISABLED"; +parameter DIV = "2.0"; +endmodule + +module PCSCLKDIV ( +input CLKI, RST, SEL2, SEL1, SEL0, +output CDIV1, CDIVX ); //synthesis syn_black_box syn_lib_cell=1 +parameter GSR = "DISABLED"; +endmodule + +module DCSC ( +input CLK1, CLK0, SEL1, SEL0, MODESEL, +output DCSOUT ); //synthesis syn_black_box syn_lib_cell=1 +parameter DCSMODE = "POS"; +endmodule + +module DCCA ( +input CLKI, CE, +output CLKO ); //synthesis syn_black_box syn_lib_cell=1 +endmodule + +module ECLKSYNCB ( +input ECLKI, STOP, +output ECLKO ); //synthesis syn_black_box syn_lib_cell=1 +endmodule + +module ECLKBRIDGECS ( +input CLK0, CLK1, SEL, +output ECSOUT ); //synthesis syn_black_box syn_lib_cell=1 +endmodule + +module PLLREFCS ( +input CLK0,CLK1,SEL, +output PLLCSOUT ); //synthesis syn_black_box syn_lib_cell=1 +endmodule + +module DELAYF ( +input A, LOADN, MOVE, DIRECTION, +output Z, CFLAG ); //synthesis syn_black_box syn_lib_cell=1 +parameter DEL_MODE = "USER_DEFINED"; +parameter DEL_VALUE = 0; +endmodule + +module DELAYG ( +input A, +output Z ); //synthesis syn_black_box syn_lib_cell=1 +parameter DEL_MODE = "USER_DEFINED"; +parameter DEL_VALUE = 0; +endmodule + +module START ( +input STARTCLK ); //synthesis syn_black_box syn_lib_cell=1 syn_noprune=1 +endmodule + +module USRMCLK ( +input USRMCLKI, USRMCLKTS ); //synthesis syn_black_box syn_lib_cell=1 syn_noprune=1 +endmodule + +module DQSBUFM ( +input DQSI,READ1,READ0,READCLKSEL2,READCLKSEL1,READCLKSEL0,DDRDEL,ECLK,SCLK, RST, +input DYNDELAY7, DYNDELAY6, DYNDELAY5, DYNDELAY4, DYNDELAY3, DYNDELAY2, DYNDELAY1, DYNDELAY0, +input PAUSE,RDLOADN,RDMOVE,RDDIRECTION,WRLOADN,WRMOVE,WRDIRECTION, +output DQSR90,DQSW,DQSW270,RDPNTR2,RDPNTR1,RDPNTR0,WRPNTR2,WRPNTR1,WRPNTR0, +output DATAVALID, BURSTDET,RDCFLAG,WRCFLAG ); //synthesis syn_black_box syn_lib_cell=1 +parameter DQS_LI_DEL_VAL = 4; +parameter DQS_LI_DEL_ADJ = "FACTORYONLY"; +parameter DQS_LO_DEL_VAL = 0; +parameter DQS_LO_DEL_ADJ = "FACTORYONLY"; +parameter GSR = "ENABLED"; +endmodule + +module DDRDLLA ( +input CLK, RST, UDDCNTLN, FREEZE, +output DDRDEL, LOCK, +output DCNTL7,DCNTL6,DCNTL5,DCNTL4,DCNTL3,DCNTL2,DCNTL1,DCNTL0 ); //synthesis syn_black_box syn_lib_cell=1 +parameter FORCE_MAX_DELAY = "NO"; +parameter GSR = "ENABLED"; +endmodule + +module DLLDELD ( +input A, DDRDEL,LOADN,MOVE,DIRECTION, +output Z, CFLAG ); //synthesis syn_black_box syn_lib_cell=1 +endmodule + +module IDDRX1F ( +input D, SCLK, RST, +output Q0, Q1 ); //synthesis syn_black_box syn_lib_cell=1 +parameter GSR = "ENABLED"; +endmodule + +module IDDRX2F ( +input D, SCLK, ECLK, RST, ALIGNWD, +output Q3, Q2, Q1, Q0 ); //synthesis syn_black_box syn_lib_cell=1 +parameter GSR = "ENABLED"; +endmodule + +module IDDR71B ( +input D, SCLK,ECLK,RST,ALIGNWD, +output Q6,Q5,Q4,Q3,Q2,Q1,Q0 ); //synthesis syn_black_box syn_lib_cell=1 +parameter GSR = "ENABLED"; +endmodule + +module IDDRX2DQA ( +input SCLK,ECLK,DQSR90,D,RST, +input RDPNTR2,RDPNTR1,RDPNTR0,WRPNTR2,WRPNTR1,WRPNTR0, +output Q3,Q2,Q1,Q0,QWL ); //synthesis syn_black_box syn_lib_cell=1 +parameter GSR = "ENABLED"; +endmodule + +module ODDRX1F ( +input SCLK, RST, D0, D1, +output Q ); //synthesis syn_black_box syn_lib_cell=1 +parameter GSR = "ENABLED"; +endmodule + +module ODDRX2F ( +input SCLK,ECLK,RST,D3,D2,D1,D0, +output Q ); //synthesis syn_black_box syn_lib_cell=1 +parameter GSR = "ENABLED"; +endmodule + +module ODDR71B ( +input SCLK,ECLK,RST,D6,D5,D4,D3,D2,D1,D0, +output Q ); //synthesis syn_black_box syn_lib_cell=1 +parameter GSR = "ENABLED"; +endmodule + +module OSHX2A ( +input D1,D0,SCLK,ECLK,RST, +output Q ); //synthesis syn_black_box syn_lib_cell=1 +parameter GSR = "ENABLED"; +endmodule + +module TSHX2DQA ( +input T1,T0,SCLK,ECLK,DQSW270,RST, +output Q ); //synthesis syn_black_box syn_lib_cell=1 +parameter GSR = "ENABLED"; +parameter REGSET = "SET"; +endmodule + +module TSHX2DQSA ( +input T1,T0,SCLK,ECLK,DQSW,RST, +output Q ); //synthesis syn_black_box syn_lib_cell=1 +parameter GSR = "ENABLED"; +parameter REGSET = "SET"; +endmodule + +module ODDRX2DQA ( +input D3,D2,D1,D0,DQSW270,SCLK,ECLK,RST, +output Q ); //synthesis syn_black_box syn_lib_cell=1 +parameter GSR = "ENABLED"; +endmodule + +module ODDRX2DQSB ( +input D3,D2,D1,D0,SCLK,ECLK,DQSW,RST, +output Q ); //synthesis syn_black_box syn_lib_cell=1 +parameter GSR = "ENABLED"; +endmodule + +module EHXPLLL ( +input CLKI, CLKFB, PHASESEL1, PHASESEL0, PHASEDIR, PHASESTEP, PHASELOADREG, +input STDBY, PLLWAKESYNC, +input RST, ENCLKOP, ENCLKOS, ENCLKOS2, ENCLKOS3, +output CLKOP,CLKOS,CLKOS2,CLKOS3,LOCK,INTLOCK, +output REFCLK, CLKINTFB ); //synthesis syn_black_box syn_lib_cell=1 +parameter CLKI_DIV = 1; +parameter CLKFB_DIV = 1; +parameter CLKOP_DIV = 8; +parameter CLKOS_DIV = 8; +parameter CLKOS2_DIV = 8; +parameter CLKOS3_DIV = 8; +parameter CLKOP_ENABLE = "ENABLED"; +parameter CLKOS_ENABLE = "DISABLED"; +parameter CLKOS2_ENABLE = "DISABLED"; +parameter CLKOS3_ENABLE = "DISABLED"; +parameter CLKOP_CPHASE = 0; +parameter CLKOS_CPHASE = 0; +parameter CLKOS2_CPHASE = 0; +parameter CLKOS3_CPHASE = 0; +parameter CLKOP_FPHASE = 0; +parameter CLKOS_FPHASE = 0; +parameter CLKOS2_FPHASE = 0; +parameter CLKOS3_FPHASE = 0; +parameter FEEDBK_PATH = "CLKOP"; +parameter CLKOP_TRIM_POL = "RISING"; +parameter CLKOP_TRIM_DELAY = 0; +parameter CLKOS_TRIM_POL = "RISING"; +parameter CLKOS_TRIM_DELAY = 0; +parameter OUTDIVIDER_MUXA = "DIVA"; +parameter OUTDIVIDER_MUXB = "DIVB"; +parameter OUTDIVIDER_MUXC = "DIVC"; +parameter OUTDIVIDER_MUXD = "DIVD"; +parameter PLL_LOCK_MODE = 0; +parameter PLL_LOCK_DELAY = 200; +parameter STDBY_ENABLE = "DISABLED"; +parameter REFIN_RESET = "DISABLED"; +parameter SYNC_ENABLE = "DISABLED"; +parameter INT_LOCK_STICKY = "ENABLED"; +parameter DPHASE_SOURCE = "DISABLED"; +parameter PLLRST_ENA = "DISABLED"; +parameter INTFB_WAKE = "DISABLED"; +endmodule + +module DTR ( +input STARTPULSE, +output DTROUT7,DTROUT6,DTROUT5,DTROUT4,DTROUT3,DTROUT2,DTROUT1,DTROUT0 ); //synthesis syn_black_box syn_lib_cell=1 +parameter DTR_TEMP = 25; +endmodule + +module OSCG ( +output OSC); //synthesis syn_black_box syn_lib_cell=1 +parameter DIV = 128; +endmodule + +module EXTREFB ( + input REFCLKP, REFCLKN, + output REFCLKO + ); //synthesis syn_black_box syn_lib_cell=1 black_box_pad_pin="REFCLKP,REFCLKN" + parameter REFCK_PWDNB = "DONTCARE"; + parameter REFCK_RTERM = "DONTCARE"; + parameter REFCK_DCBIAS_EN = "DONTCARE"; +endmodule + +module JTAGG ( +input TCK, TMS, TDI, JTDO2, JTDO1, +output TDO, JTDI, JTCK, JRTI2, JRTI1, +output JSHIFT, JUPDATE, JRSTN, JCE2, JCE1 ); //synthesis syn_black_box syn_lib_cell=1 +parameter ER1 = "ENABLED"; +parameter ER2 = "ENABLED"; +endmodule + +module SEDGA ( +input SEDENABLE, SEDSTART, SEDFRCERR, +output SEDCLKOUT, SEDDONE, SEDINPROG, SEDERR +); //synthesis syn_black_box syn_lib_cell=1 +parameter SED_CLK_FREQ = "2.4"; +parameter CHECKALWAYS = "DISABLED"; +parameter DEV_DENSITY = "85KUM"; +endmodule + + + +module DCUA ( + // Channel and Dual Pins + input CH0_HDINP, CH1_HDINP, CH0_HDINN, CH1_HDINN, D_TXBIT_CLKP_FROM_ND, D_TXBIT_CLKN_FROM_ND, D_SYNC_ND, D_TXPLL_LOL_FROM_ND, + CH0_RX_REFCLK, CH1_RX_REFCLK, CH0_FF_RXI_CLK, CH1_FF_RXI_CLK, CH0_FF_TXI_CLK, CH1_FF_TXI_CLK, CH0_FF_EBRD_CLK, CH1_FF_EBRD_CLK, + CH0_FF_TX_D_0, CH1_FF_TX_D_0, CH0_FF_TX_D_1, CH1_FF_TX_D_1, CH0_FF_TX_D_2, CH1_FF_TX_D_2, CH0_FF_TX_D_3, CH1_FF_TX_D_3, + CH0_FF_TX_D_4, CH1_FF_TX_D_4, CH0_FF_TX_D_5, CH1_FF_TX_D_5, CH0_FF_TX_D_6, CH1_FF_TX_D_6, CH0_FF_TX_D_7, CH1_FF_TX_D_7, + CH0_FF_TX_D_8, CH1_FF_TX_D_8, CH0_FF_TX_D_9, CH1_FF_TX_D_9, CH0_FF_TX_D_10, CH1_FF_TX_D_10, CH0_FF_TX_D_11, CH1_FF_TX_D_11, + CH0_FF_TX_D_12, CH1_FF_TX_D_12, CH0_FF_TX_D_13, CH1_FF_TX_D_13, CH0_FF_TX_D_14, CH1_FF_TX_D_14, CH0_FF_TX_D_15, CH1_FF_TX_D_15, + CH0_FF_TX_D_16, CH1_FF_TX_D_16, CH0_FF_TX_D_17, CH1_FF_TX_D_17, CH0_FF_TX_D_18, CH1_FF_TX_D_18, CH0_FF_TX_D_19, CH1_FF_TX_D_19, + CH0_FF_TX_D_20, CH1_FF_TX_D_20, CH0_FF_TX_D_21, CH1_FF_TX_D_21, CH0_FF_TX_D_22, CH1_FF_TX_D_22, CH0_FF_TX_D_23, CH1_FF_TX_D_23, + CH0_FFC_EI_EN, CH1_FFC_EI_EN, CH0_FFC_PCIE_DET_EN, CH1_FFC_PCIE_DET_EN, CH0_FFC_PCIE_CT, CH1_FFC_PCIE_CT, CH0_FFC_SB_INV_RX, CH1_FFC_SB_INV_RX, + CH0_FFC_ENABLE_CGALIGN, CH1_FFC_ENABLE_CGALIGN, CH0_FFC_SIGNAL_DETECT, CH1_FFC_SIGNAL_DETECT, CH0_FFC_FB_LOOPBACK, CH1_FFC_FB_LOOPBACK, CH0_FFC_SB_PFIFO_LP, CH1_FFC_SB_PFIFO_LP, + CH0_FFC_PFIFO_CLR, CH1_FFC_PFIFO_CLR, CH0_FFC_RATE_MODE_RX, CH1_FFC_RATE_MODE_RX, CH0_FFC_RATE_MODE_TX, CH1_FFC_RATE_MODE_TX, CH0_FFC_DIV11_MODE_RX, CH1_FFC_DIV11_MODE_RX, CH0_FFC_RX_GEAR_MODE, CH1_FFC_RX_GEAR_MODE, CH0_FFC_TX_GEAR_MODE, CH1_FFC_TX_GEAR_MODE, + CH0_FFC_DIV11_MODE_TX, CH1_FFC_DIV11_MODE_TX, CH0_FFC_LDR_CORE2TX_EN, CH1_FFC_LDR_CORE2TX_EN, CH0_FFC_LANE_TX_RST, CH1_FFC_LANE_TX_RST, CH0_FFC_LANE_RX_RST, CH1_FFC_LANE_RX_RST, + CH0_FFC_RRST, CH1_FFC_RRST, CH0_FFC_TXPWDNB, CH1_FFC_TXPWDNB, CH0_FFC_RXPWDNB, CH1_FFC_RXPWDNB, CH0_LDR_CORE2TX, CH1_LDR_CORE2TX, + D_SCIWDATA0, D_SCIWDATA1, D_SCIWDATA2, D_SCIWDATA3, D_SCIWDATA4, D_SCIWDATA5, D_SCIWDATA6, D_SCIWDATA7, + D_SCIADDR0, D_SCIADDR1, D_SCIADDR2, D_SCIADDR3, D_SCIADDR4, D_SCIADDR5, D_SCIENAUX, D_SCISELAUX, + CH0_SCIEN, CH1_SCIEN, CH0_SCISEL, CH1_SCISEL, D_SCIRD, D_SCIWSTN, D_CYAWSTN, D_FFC_SYNC_TOGGLE, + D_FFC_DUAL_RST, D_FFC_MACRO_RST, D_FFC_MACROPDB, D_FFC_TRST, CH0_FFC_CDR_EN_BITSLIP, CH1_FFC_CDR_EN_BITSLIP, D_SCAN_ENABLE, D_SCAN_IN_0, + D_SCAN_IN_1, D_SCAN_IN_2, D_SCAN_IN_3, D_SCAN_IN_4, D_SCAN_IN_5, D_SCAN_IN_6, D_SCAN_IN_7, D_SCAN_MODE, + D_SCAN_RESET, D_CIN0, D_CIN1, D_CIN2, D_CIN3, D_CIN4, D_CIN5, D_CIN6, + D_CIN7, D_CIN8, D_CIN9, D_CIN10, D_CIN11, + output CH0_HDOUTP, CH1_HDOUTP, CH0_HDOUTN, CH1_HDOUTN, D_TXBIT_CLKP_TO_ND, D_TXBIT_CLKN_TO_ND, D_SYNC_PULSE2ND, D_TXPLL_LOL_TO_ND, + CH0_FF_RX_F_CLK, CH1_FF_RX_F_CLK, CH0_FF_RX_H_CLK, CH1_FF_RX_H_CLK, CH0_FF_TX_F_CLK, CH1_FF_TX_F_CLK, CH0_FF_TX_H_CLK, CH1_FF_TX_H_CLK, + CH0_FF_RX_PCLK, CH1_FF_RX_PCLK, CH0_FF_TX_PCLK, CH1_FF_TX_PCLK, CH0_FF_RX_D_0, CH1_FF_RX_D_0, CH0_FF_RX_D_1, CH1_FF_RX_D_1, + CH0_FF_RX_D_2, CH1_FF_RX_D_2, CH0_FF_RX_D_3, CH1_FF_RX_D_3, CH0_FF_RX_D_4, CH1_FF_RX_D_4, CH0_FF_RX_D_5, CH1_FF_RX_D_5, + CH0_FF_RX_D_6, CH1_FF_RX_D_6, CH0_FF_RX_D_7, CH1_FF_RX_D_7, CH0_FF_RX_D_8, CH1_FF_RX_D_8, CH0_FF_RX_D_9, CH1_FF_RX_D_9, + CH0_FF_RX_D_10, CH1_FF_RX_D_10, CH0_FF_RX_D_11, CH1_FF_RX_D_11, CH0_FF_RX_D_12, CH1_FF_RX_D_12, CH0_FF_RX_D_13, CH1_FF_RX_D_13, + CH0_FF_RX_D_14, CH1_FF_RX_D_14, CH0_FF_RX_D_15, CH1_FF_RX_D_15, CH0_FF_RX_D_16, CH1_FF_RX_D_16, CH0_FF_RX_D_17, CH1_FF_RX_D_17, + CH0_FF_RX_D_18, CH1_FF_RX_D_18, CH0_FF_RX_D_19, CH1_FF_RX_D_19, CH0_FF_RX_D_20, CH1_FF_RX_D_20, CH0_FF_RX_D_21, CH1_FF_RX_D_21, + CH0_FF_RX_D_22, CH1_FF_RX_D_22, CH0_FF_RX_D_23, CH1_FF_RX_D_23, CH0_FFS_PCIE_DONE, CH1_FFS_PCIE_DONE, CH0_FFS_PCIE_CON, CH1_FFS_PCIE_CON, + CH0_FFS_RLOS, CH1_FFS_RLOS, CH0_FFS_LS_SYNC_STATUS, CH1_FFS_LS_SYNC_STATUS, CH0_FFS_CC_UNDERRUN, CH1_FFS_CC_UNDERRUN, CH0_FFS_CC_OVERRUN, CH1_FFS_CC_OVERRUN, + CH0_FFS_RXFBFIFO_ERROR, CH1_FFS_RXFBFIFO_ERROR, CH0_FFS_TXFBFIFO_ERROR, CH1_FFS_TXFBFIFO_ERROR, CH0_FFS_RLOL, CH1_FFS_RLOL, CH0_FFS_SKP_ADDED, CH1_FFS_SKP_ADDED, + CH0_FFS_SKP_DELETED, CH1_FFS_SKP_DELETED, CH0_LDR_RX2CORE, CH1_LDR_RX2CORE, D_SCIRDATA0, D_SCIRDATA1, D_SCIRDATA2, D_SCIRDATA3, + D_SCIRDATA4, D_SCIRDATA5, D_SCIRDATA6, D_SCIRDATA7, D_SCIINT, D_SCAN_OUT_0, D_SCAN_OUT_1, D_SCAN_OUT_2, + D_SCAN_OUT_3, D_SCAN_OUT_4, D_SCAN_OUT_5, D_SCAN_OUT_6, D_SCAN_OUT_7, D_COUT0, D_COUT1, D_COUT2, + D_COUT3, D_COUT4, D_COUT5, D_COUT6, D_COUT7, D_COUT8, D_COUT9, D_COUT10, + D_COUT11, D_COUT12, D_COUT13, D_COUT14, D_COUT15, D_COUT16, D_COUT17, D_COUT18, + D_COUT19, + // No of ports = 157 inputs + 129 outputs = 286 + + // PLL Pins + input D_REFCLKI, + output D_FFS_PLOL + // No of ports = 1 inputs + 1 outputs = 2 + + // Total no of ports = 288 + ); //synthesis syn_black_box syn_lib_cell=1 black_box_pad_pin="CH0_HDINP, CH1_HDINP, CH0_HDINN, CH1_HDINN, CH0_HDOUTP, CH1_HDOUTP, CH0_HDOUTN, CH1_HDOUTN" + + + // Ch_Dual_Attr + parameter D_MACROPDB = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter D_IB_PWDNB = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter D_XGE_MODE = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter D_LOW_MARK = "DONTCARE"; //"DONTCARE" "0d0"-"0d15" + parameter D_HIGH_MARK = "DONTCARE"; //"DONTCARE" "0d0"-"0d15" + parameter D_BUS8BIT_SEL = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter D_CDR_LOL_SET = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter D_BITCLK_LOCAL_EN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter D_BITCLK_ND_EN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter D_BITCLK_FROM_ND_EN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter D_SYNC_LOCAL_EN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter D_SYNC_ND_EN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_UC_MODE = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_UC_MODE = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_PCIE_MODE = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_PCIE_MODE = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_RIO_MODE = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_RIO_MODE = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_WA_MODE = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_WA_MODE = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_INVERT_RX = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_INVERT_RX = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_INVERT_TX = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_INVERT_TX = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_PRBS_SELECTION = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_PRBS_SELECTION = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_GE_AN_ENABLE = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_GE_AN_ENABLE = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_PRBS_LOCK = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_PRBS_LOCK = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_PRBS_ENABLE = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_PRBS_ENABLE = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_ENABLE_CG_ALIGN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_ENABLE_CG_ALIGN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_TX_GEAR_MODE = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_TX_GEAR_MODE = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_RX_GEAR_MODE = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_RX_GEAR_MODE = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_PCS_DET_TIME_SEL = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH1_PCS_DET_TIME_SEL = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH0_PCIE_EI_EN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_PCIE_EI_EN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_TX_GEAR_BYPASS = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_TX_GEAR_BYPASS = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_ENC_BYPASS = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_ENC_BYPASS = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_SB_BYPASS = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_SB_BYPASS = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_RX_SB_BYPASS = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_RX_SB_BYPASS = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_WA_BYPASS = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_WA_BYPASS = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_DEC_BYPASS = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_DEC_BYPASS = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_CTC_BYPASS = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_CTC_BYPASS = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_RX_GEAR_BYPASS = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_RX_GEAR_BYPASS = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_LSM_DISABLE = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_LSM_DISABLE = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_MATCH_2_ENABLE = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_MATCH_2_ENABLE = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_MATCH_4_ENABLE = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_MATCH_4_ENABLE = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_MIN_IPG_CNT = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH1_MIN_IPG_CNT = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH0_CC_MATCH_1 = "DONTCARE"; //"DONTCARE" "0x000"-"0x3ff" + parameter CH1_CC_MATCH_1 = "DONTCARE"; //"DONTCARE" "0x000"-"0x3ff" + parameter CH0_CC_MATCH_2 = "DONTCARE"; //"DONTCARE" "0x000"-"0x3ff" + parameter CH1_CC_MATCH_2 = "DONTCARE"; //"DONTCARE" "0x000"-"0x3ff" + parameter CH0_CC_MATCH_3 = "DONTCARE"; //"DONTCARE" "0x000"-"0x3ff" + parameter CH1_CC_MATCH_3 = "DONTCARE"; //"DONTCARE" "0x000"-"0x3ff" + parameter CH0_CC_MATCH_4 = "DONTCARE"; //"DONTCARE" "0x000"-"0x3ff" + parameter CH1_CC_MATCH_4 = "DONTCARE"; //"DONTCARE" "0x000"-"0x3ff" + parameter CH0_UDF_COMMA_MASK = "DONTCARE"; //"DONTCARE" "0x000"-"0x3ff" + parameter CH1_UDF_COMMA_MASK = "DONTCARE"; //"DONTCARE" "0x000"-"0x3ff" + parameter CH0_UDF_COMMA_A = "DONTCARE"; //"DONTCARE" "0x000"-"0x3ff" + parameter CH1_UDF_COMMA_A = "DONTCARE"; //"DONTCARE" "0x000"-"0x3ff" + parameter CH0_UDF_COMMA_B = "DONTCARE"; //"DONTCARE" "0x000"-"0x3ff" + parameter CH1_UDF_COMMA_B = "DONTCARE"; //"DONTCARE" "0x000"-"0x3ff" + parameter CH0_RX_DCO_CK_DIV = "DONTCARE"; //"DONTCARE" "0b000"-"0b111" + parameter CH1_RX_DCO_CK_DIV = "DONTCARE"; //"DONTCARE" "0b000"-"0b111" + parameter CH0_RCV_DCC_EN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_RCV_DCC_EN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_REQ_LVL_SET = "DONTCARE"; //"DONTCARE" "0b00" "0b11" + parameter CH1_REQ_LVL_SET = "DONTCARE"; //"DONTCARE" "0b00" "0b11" + parameter CH0_REQ_EN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_REQ_EN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_RTERM_RX = "DONTCARE"; //"DONTCARE" "0d0"-"0d31" + parameter CH1_RTERM_RX = "DONTCARE"; //"DONTCARE" "0d0"-"0d31" + parameter CH0_PDEN_SEL = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_PDEN_SEL = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_LDR_RX2CORE_SEL = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_LDR_RX2CORE_SEL = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_LDR_CORE2TX_SEL = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_LDR_CORE2TX_SEL = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_TPWDNB = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_TPWDNB = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_RATE_MODE_TX = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_RATE_MODE_TX = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_RTERM_TX = "DONTCARE"; //"DONTCARE" "0d0"-"0d31 + parameter CH1_RTERM_TX = "DONTCARE"; //"DONTCARE" "0d0"-"0d31" + parameter CH0_TX_CM_SEL = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH1_TX_CM_SEL = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH0_TDRV_PRE_EN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_TDRV_PRE_EN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_TDRV_SLICE0_SEL = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH1_TDRV_SLICE0_SEL = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH0_TDRV_SLICE1_SEL = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH1_TDRV_SLICE1_SEL = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH0_TDRV_SLICE2_SEL = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH1_TDRV_SLICE2_SEL = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH0_TDRV_SLICE3_SEL = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH1_TDRV_SLICE3_SEL = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH0_TDRV_SLICE4_SEL = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH1_TDRV_SLICE4_SEL = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH0_TDRV_SLICE5_SEL = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH1_TDRV_SLICE5_SEL = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH0_TDRV_SLICE0_CUR = "DONTCARE"; //"DONTCARE" "0b000"-"0b111" + parameter CH1_TDRV_SLICE0_CUR = "DONTCARE"; //"DONTCARE" "0b000"-"0b111" + parameter CH0_TDRV_SLICE1_CUR = "DONTCARE"; //"DONTCARE" "0b000"-"0b111" + parameter CH1_TDRV_SLICE1_CUR = "DONTCARE"; //"DONTCARE" "0b000"-"0b111" + parameter CH0_TDRV_SLICE2_CUR = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH1_TDRV_SLICE2_CUR = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH0_TDRV_SLICE3_CUR = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH1_TDRV_SLICE3_CUR = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH0_TDRV_SLICE4_CUR = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH1_TDRV_SLICE4_CUR = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH0_TDRV_SLICE5_CUR = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH1_TDRV_SLICE5_CUR = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH0_TDRV_DAT_SEL = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH1_TDRV_DAT_SEL = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH0_TX_DIV11_SEL = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_TX_DIV11_SEL = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_RPWDNB = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_RPWDNB = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_RATE_MODE_RX = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_RATE_MODE_RX = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_RLOS_SEL = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_RLOS_SEL = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_RX_LOS_LVL = "DONTCARE"; //"DONTCARE" "0b000"-"0b111" + parameter CH1_RX_LOS_LVL = "DONTCARE"; //"DONTCARE" "0b000"-"0b111" + parameter CH0_RX_LOS_CEQ = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH1_RX_LOS_CEQ = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH0_RX_LOS_HYST_EN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_RX_LOS_HYST_EN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_RX_LOS_EN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_RX_LOS_EN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_RX_DIV11_SEL = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_RX_DIV11_SEL = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_SEL_SD_RX_CLK = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_SEL_SD_RX_CLK = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_FF_RX_H_CLK_EN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_FF_RX_H_CLK_EN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_FF_RX_F_CLK_DIS = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_FF_RX_F_CLK_DIS = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_FF_TX_H_CLK_EN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_FF_TX_H_CLK_EN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_FF_TX_F_CLK_DIS = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_FF_TX_F_CLK_DIS = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_RX_RATE_SEL = "DONTCARE"; //"DONTCARE" "0d0"-"0d15" + parameter CH1_RX_RATE_SEL = "DONTCARE"; //"DONTCARE" "0d0"-"0d15" + parameter CH0_TDRV_POST_EN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_TDRV_POST_EN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_TX_POST_SIGN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_TX_POST_SIGN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_TX_PRE_SIGN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_TX_PRE_SIGN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_RXTERM_CM = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH1_RXTERM_CM = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH0_RXIN_CM = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH1_RXIN_CM = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH0_LEQ_OFFSET_SEL = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_LEQ_OFFSET_SEL = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_LEQ_OFFSET_TRIM = "DONTCARE"; //"DONTCARE" "0b000"-"0b111" + parameter CH1_LEQ_OFFSET_TRIM = "DONTCARE"; //"DONTCARE" "0b000"-"0b111" + parameter D_TX_MAX_RATE = "DONTCARE"; //"DONTCARE" "0.27"-"3.125" + parameter CH0_CDR_MAX_RATE = "DONTCARE"; //"DONTCARE" "0.27"-"3.125" + parameter CH1_CDR_MAX_RATE = "DONTCARE"; //"DONTCARE" "0.27"-"3.125" + parameter CH0_TXAMPLITUDE = "DONTCARE"; //"DONTCARE" "0d0"-"0d9" + parameter CH1_TXAMPLITUDE = "DONTCARE"; //"DONTCARE" "0d0"-"0d9" + parameter CH0_TXDEPRE = "DONTCARE"; //"DONTCARE" "0d0"-"0d9" + parameter CH1_TXDEPRE = "DONTCARE"; //"DONTCARE" "0d0"-"0d9" + parameter CH0_TXDEPOST = "DONTCARE"; //"DONTCARE" "0d0"-"0d9" + parameter CH1_TXDEPOST = "DONTCARE"; //"DONTCARE" "0d0"-"0d9" + parameter CH0_PROTOCOL = "DONTCARE"; //"DONTCARE" "0d0"-"0d9" + parameter CH1_PROTOCOL = "DONTCARE"; //"DONTCARE" "0d0"-"0d9" + // No of parameters = 172 + + // Analog_Attr + parameter D_ISETLOS = "DONTCARE"; //"DONTCARE" "0d0"-"0d255" + parameter D_SETIRPOLY_AUX = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter D_SETICONST_AUX = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter D_SETIRPOLY_CH = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter D_SETICONST_CH = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter D_REQ_ISET = "DONTCARE"; //"DONTCARE" "0b000"-"0b111" + parameter D_PD_ISET = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter D_DCO_CALIB_TIME_SEL = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH0_DCOCTLGI = "DONTCARE"; //"DONTCARE" "0b000"-"0b111" + parameter CH1_DCOCTLGI = "DONTCARE"; //"DONTCARE" "0b000"-"0b111" + parameter CH0_DCOATDDLY = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH1_DCOATDDLY = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH0_DCOATDCFG = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH1_DCOATDCFG = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH0_DCOBYPSATD = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_DCOBYPSATD = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_DCOSCALEI = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH1_DCOSCALEI = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH0_DCOITUNE4LSB = "DONTCARE"; //"DONTCARE" "0b000"-"0b111" + parameter CH1_DCOITUNE4LSB = "DONTCARE"; //"DONTCARE" "0b000"-"0b111" + parameter CH0_DCOIOSTUNE = "DONTCARE"; //"DONTCARE" "0b000"-"0b111" + parameter CH1_DCOIOSTUNE = "DONTCARE"; //"DONTCARE" "0b000"-"0b111" + parameter CH0_DCODISBDAVOID = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_DCODISBDAVOID = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_DCOCALDIV = "DONTCARE"; //"DONTCARE" "0b000"-"0b111" + parameter CH1_DCOCALDIV = "DONTCARE"; //"DONTCARE" "0b000"-"0b111" + parameter CH0_DCONUOFLSB = "DONTCARE"; //"DONTCARE" "0b000"-"0b111" + parameter CH1_DCONUOFLSB = "DONTCARE"; //"DONTCARE" "0b000"-"0b111" + parameter CH0_DCOIUPDNX2 = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_DCOIUPDNX2 = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_DCOSTEP = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH1_DCOSTEP = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH0_DCOSTARTVAL = "DONTCARE"; //"DONTCARE" "0b000"-"0b111" + parameter CH1_DCOSTARTVAL = "DONTCARE"; //"DONTCARE" "0b000"-"0b111" + parameter CH0_DCOFLTDAC = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH1_DCOFLTDAC = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH0_DCOITUNE = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH1_DCOITUNE = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH0_DCOFTNRG = "DONTCARE"; //"DONTCARE" "0b000"-"0b111" + parameter CH1_DCOFTNRG = "DONTCARE"; //"DONTCARE" "0b000"-"0b111" + parameter CH0_CDR_CNT4SEL = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH1_CDR_CNT4SEL = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH0_CDR_CNT8SEL = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH1_CDR_CNT8SEL = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter CH0_BAND_THRESHOLD = "DONTCARE"; //"DONTCARE" "0d0"-"0d63" + parameter CH1_BAND_THRESHOLD = "DONTCARE"; //"DONTCARE" "0d0"-"0d63" + parameter CH0_AUTO_FACQ_EN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_AUTO_FACQ_EN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_AUTO_CALIB_EN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_AUTO_CALIB_EN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_CALIB_CK_MODE = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_CALIB_CK_MODE = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH0_REG_BAND_OFFSET = "DONTCARE"; //"DONTCARE" "0d0"-"0d15" + parameter CH1_REG_BAND_OFFSET = "DONTCARE"; //"DONTCARE" "0d0"-"0d15" + parameter CH0_REG_BAND_SEL = "DONTCARE"; //"DONTCARE" "0d0"-"0d63" + parameter CH1_REG_BAND_SEL = "DONTCARE"; //"DONTCARE" "0d0"-"0d63" + parameter CH0_REG_IDAC_SEL = "DONTCARE"; //"DONTCARE" "0d0"-"0d1023" + parameter CH1_REG_IDAC_SEL = "DONTCARE"; //"DONTCARE" "0d0"-"0d1023" + parameter CH0_REG_IDAC_EN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter CH1_REG_IDAC_EN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + // No of parameters = 60 + + // PLL Attr + parameter D_TXPLL_PWDNB = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter D_SETPLLRC = "DONTCARE"; //"DONTCARE" "0d0"-"0d63" + parameter D_REFCK_MODE = "DONTCARE"; //"DONTCARE" "0b000"-"0b100" + parameter D_TX_VCO_CK_DIV = "DONTCARE"; //"DONTCARE" "0b000"-"0b111" + parameter D_PLL_LOL_SET = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter D_RG_EN = "DONTCARE"; //"DONTCARE" "0b0" "0b1" + parameter D_RG_SET = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter D_CMUSETISCL4VCO = "DONTCARE"; //"DONTCARE" "0b000"-"0b111" + parameter D_CMUSETI4VCO = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter D_CMUSETINITVCT = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter D_CMUSETZGM = "DONTCARE"; //"DONTCARE" "0b000"-"0b111" + parameter D_CMUSETP2AGM = "DONTCARE"; //"DONTCARE" "0b000"-"0b111" + parameter D_CMUSETP1GM = "DONTCARE"; //"DONTCARE" "0b000"-"0b111" + parameter D_CMUSETI4CPZ = "DONTCARE"; //"DONTCARE" "0d0" "0d15" + parameter D_CMUSETI4CPP = "DONTCARE"; //"DONTCARE" "0d0" "0d15" + parameter D_CMUSETICP4Z = "DONTCARE"; //"DONTCARE" "0b000"-"0b111" + parameter D_CMUSETICP4P = "DONTCARE"; //"DONTCARE" "0b00"-"0b11" + parameter D_CMUSETBIASI = "DONTCARE"; //"DONTCARE" "0b00" "0b11" + // No of parameters = 18 + + // Total no of parameters = 250 +endmodule + diff --git a/manufacturer/lattice/ecp5um/source/top.v b/manufacturer/lattice/ecp5um/source/top.v new file mode 100644 index 0000000..0fa939b --- /dev/null +++ b/manufacturer/lattice/ecp5um/source/top.v @@ -0,0 +1,2361 @@ +/* + * top.v + * + * Copyright (C) 2018, 2019, 2020, 2021 Mind Chasers Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Private Island Top for Darsena / ECP5UM + * + */ + + `include "directives.v" + +module top( + input rstn, + + // REFCLK + input refclkp_d0, refclkn_d0, + input refclkp_d1, refclkn_d1, + + // SGMII0 + input sgmii0_hdinp, + input sgmii0_hdinn, + output sgmii0_hdoutp, + output sgmii0_hdoutn, + + // SGMII1 + input sgmii1_hdinp, + input sgmii1_hdinn, + output sgmii1_hdoutp, + output sgmii1_hdoutn, + + // SGMII2 + input sgmii2_hdinp, + input sgmii2_hdinn, + output sgmii2_hdoutp, + output sgmii2_hdoutn, + + // SGMII3 + input sgmii3_hdinp, + input sgmii3_hdinn, + output sgmii3_hdoutp, + output sgmii3_hdoutn, + + // PHYs + output phy_mdc, + + output phy0_resetn, + inout phy0_mdio, + input [1:0] phy0_gpio, + input phy0_intn, + + output phy1_resetn, + inout phy1_mdio, + input [1:0] phy1_gpio, + input phy1_intn, + + // Microcontroller SPI and bit banging + input spi_cs, + input spi_clk, + output spi_miso, + input spi_mosi, + output fpga_int, + input fpga_gpio, + + // I2C + inout i2c_scl, + inout i2c_sda, + + // K02 UART + input uart_txd, + output uart_rxd, + +`ifdef DARSENA_V02 + output fpga_jtag_e, + // FTDI UART signals muxed with JTAG + input ftdi_tck_txd, + output ftdi_tdi_rxd, +`endif + + output [2:0] led, + + // Arduino Compatible GPIO + inout ard_sda, + inout ard_scl, + inout ard_rxd1, + inout ard_txd1, + inout ard_rxd2, + inout ard_txd2, + inout ard_rxd3, + inout ard_txd3, + inout pe0, // + inout pe1, // + inout pe3, + inout pe4, + inout pe5, + inout pg5, + inout ph3, // UART RX for SFP Testing + inout ph4, // UART TX for SFP Testing + inout [9:0] pa +); + + + +`include "sgmii_params.v" +`include "ethernet_params.v" + +/* PARAMS */ +localparam MDIO_ROM_ADDR_SZ = 7; + +/* nets and variables */ + +// clocks +wire clk_slow, clk_1_25, clk_10, clk_20; +wire clk_100; +wire refclko; + +// pulses +wire pulse_10ms, pulse_1_6ms; + +// misc resets +wire [3:0] phy_resetn; // bit[0] will get pruned out for now +wire [3:0] mac_reset; + +// dcu resets +wire [1:0] pcs_rst_dual; +wire [1:0] serdes_rst_dual; +wire [1:0] tx_serdes_rst; + +// channel resets +wire [3:0] rx_pcs_rst; +wire [3:0] rx_serdes_rst; +wire [3:0] tx_pcs_rst; + +// MDIO controller and driver +wire mdio_cont_work_start, mdio_cont_work_run; +wire mdio_cont_work_done; +wire [MDIO_ROM_ADDR_SZ-1:0] mdio_routine_addr; +wire [1:0] mdio_mux_sel; +wire mdio_done, mdo_oe; +wire mdo; +reg mdi; +wire [15:0] mdio_wd; +wire [15:0] mdio_rd; +wire [4:0] mdio_reg_addr; +wire mdio_ld, mdio_run; +wire mdio_rwn; +wire bin_to_ascii_run; + +`ifdef SHIELD_GIGE_SMA + wire phy2_resetn, phy2_mdc; + wire phy2_mdio_o, phy2_mdio_i, phy2_mdio_oe; +`elsif SHIELD_SFP_SMA + wire sfp_los, sfp_rate_select, sfp_pres_n, sfp_i2c_scl, sfp_tx_fault, sfp_tx_disable, sfp_i2c_sda; +`endif + +// MDIO Data block +wire [MDIO_ROM_ADDR_SZ-1:0] rom_a; +wire [7:0] rom_d; +wire [4:0] mdio_reg_addr_set; +wire [7:0] mdio_w_data_h_set, mdio_w_data_l_set; +wire [4:0] mdio_page_set; + +// I2C +wire sda_oe, scl_oe, sda_o, scl_o; + +// bin to ASCII +wire [15:0] bin_to_ascii_d_in; +wire [6:0] cont_rd; +wire read_fifo_we; +wire [8:0] fifo_r_d; + +// PCS, mac +wire pcs_pclk; +wire [1:0] pll_lol; +wire sgmii_rx_k[0:3], sgmii_tx_k[0:3]; +wire sgmii_tx_disp_correct[0:3]; +wire sgmii_rx_cv_err[0:3], sgmii_rx_disp_err[0:3], sgmii_rx_cdr_lol[0:3]; +wire sgmii_lsm_status[0:3], sgmii_rx_los_low[0:3]; +wire [7:0] rx_data0, rx_data1, rx_data2, rx_data3; +wire [7:0] tx_data0, tx_data1, tx_data2, tx_data3; +wire [6:0] read_fifo_d_i; +wire [3:0] rx_sample; +wire [3:0] pcs_error; + +// ipv4 +wire [3:0] ipv4_pkt_start; +wire [3:0] ipv4_pkt_complete; + +reg cont_fifo_re_m1, cont_fifo_re_m2; +wire cont_fifo_empty; +wire i2c_fifo_re; +wire i2c_cont_we, i2c_cont_done; +wire i_cont_fifo_re; +wire bin_to_ascii_we, mdio_rd_we, cont_rd_we; +wire [3:0] phy_up; + +// Interrupts +wire [6:0] int_do; +wire [3:0] mac_int; +wire int_sel; + +// Common Internal Memory Bus +wire[10:0] mem_addr; +wire [8:0] mem_d_i; +reg [8:0] mem_d_o; +wire mem_we, mem_oe; +wire [4:0] mem_do_mux_sel; + +// DPRAM +wire [10:0] param_phy0_addr, param_phy1_addr, param_phy2_addr, param_phy3_addr; +wire [8:0] param_phy0_din, param_phy1_din, param_phy2_din, param_phy3_din; +wire [8:0] param_phy0_dout, param_phy1_dout, param_phy2_dout, param_phy3_dout; +wire param_phy0_ce, param_phy1_ce, param_phy2_ce, param_phy3_ce; +wire param_phy0_we, param_phy1_we, param_phy2_we, param_phy3_we; +wire [8:0] param_ram_0_do, param_ram_1_do, param_ram_2_do, param_ram_3_do; + +wire [7:0] i2c_d_o; +wire [8:0] micro_fifo_do; +wire sys_mem_rx_ce, sys_mem_tx_ce, sys_mem_ptrs_sel; +wire [3:0] param_sel; + +// drop_fifos and filter +wire rx0_k_m1, rx0_k_m2, rx0_k_m3, rx0_k_m4; +wire [7:0] rx0_data_m1, rx0_data_m2, rx0_data_m3, rx0_data_m4; + +wire rx1_k_m1, rx1_k_m2, rx1_k_m3, rx1_k_m4; +wire [7:0] rx1_data_m1, rx1_data_m2, rx1_data_m3, rx1_data_m4; + +wire rx2_k_m1, rx2_k_m2, rx2_k_m3, rx2_k_m4; +wire [7:0] rx2_data_m1, rx2_data_m2, rx2_data_m3, rx2_data_m4; + +wire rx3_k_m1, rx3_k_m2, rx3_k_m3, rx3_k_m4; +wire [7:0] rx3_data_m1, rx3_data_m2, rx3_data_m3, rx3_data_m4; + +wire [3:0] rx_mac_keep; +wire [3:0] rx_sc_wr_done; + +// drop filter outputs +wire rx_df_fifo_we_01, rx_df_fifo_we_02, rx_df_fifo_we_03; +wire rx_df_fifo_we_10, rx_df_fifo_we_12, rx_df_fifo_we_13; +wire rx_df_fifo_we_20, rx_df_fifo_we_21, rx_df_fifo_we_23, rx_df_fifo_we_2u; +wire rx_df_fifo_we_30, rx_df_fifo_we_31, rx_df_fifo_we_32; +wire rx_df_fifo_we_u2; + +wire [8:0] rx_df_fifo_d_01, rx_df_fifo_d_02, rx_df_fifo_d_03; +wire [8:0] rx_df_fifo_d_10, rx_df_fifo_d_12, rx_df_fifo_d_13; +wire [8:0] rx_df_fifo_d_20, rx_df_fifo_d_21, rx_df_fifo_d_23, rx_df_fifo_d_2u; +wire [8:0] rx_df_fifo_d_30, rx_df_fifo_d_31, rx_df_fifo_d_32; +wire [8:0] rx_df_fifo_d_u2; + +// pkt filter +wire [3:0] trigger; +wire [3:0] rx_enet_bcast; +wire [3:0] rx_ipv4_arp; +wire rx_pf_keep_01; +wire rx_pf_keep_02; +wire rx_pf_keep_03; +wire rx_pf_keep_10; +wire rx_pf_keep_12; +wire rx_pf_keep_13; +wire rx_pf_keep_20; +wire rx_pf_keep_21; +wire rx_pf_keep_23; +wire rx_pf_keep_2u; +wire rx_pf_keep_30; +wire rx_pf_keep_31; +wire rx_pf_keep_32; +wire rx_pf_keep_u2; + +// rx_fifos +wire [3:0] rx_sc_fifo_we; +wire rx_sw_fifo_re_01, rx_sw_fifo_re_02, rx_sw_fifo_re_03; +wire rx_sf_fifo_empty_01, rx_sf_fifo_empty_02, rx_sf_fifo_empty_03; +wire rx_sw_fifo_re_10, rx_sw_fifo_re_12, rx_sw_fifo_re_13; +wire rx_sf_fifo_empty_10, rx_sf_fifo_empty_12, rx_sf_fifo_empty_13; +wire rx_sw_fifo_re_20, rx_sw_fifo_re_21, rx_sw_fifo_re_23, rx_sw_fifo_re_2u; +wire rx_sf_fifo_empty_20, rx_sf_fifo_empty_21, rx_sf_fifo_empty_23, rx_sf_fifo_empty_2u; +wire rx_sw_fifo_re_30, rx_sw_fifo_re_31, rx_sw_fifo_re_32; +wire rx_sf_fifo_empty_30, rx_sf_fifo_empty_31, rx_sf_fifo_empty_32; +wire rx_sw_fifo_re_u2, rx_uc_fifo_empty_u2; +wire [8:0] rx_sc_fifo_d0, rx_sc_fifo_d1, rx_sc_fifo_d2, rx_sc_fifo_d3; +wire [8:0] rx_sf_fifo_d_01, rx_sf_fifo_d_02, rx_sf_fifo_d_03; +wire [8:0] rx_sf_fifo_d_10, rx_sf_fifo_d_12, rx_sf_fifo_d_13; +wire [8:0] rx_sf_fifo_d_20, rx_sf_fifo_d_21, rx_sf_fifo_d_23, rx_sf_fifo_d_2u; +wire [8:0] rx_sf_fifo_d_30, rx_sf_fifo_d_31, rx_sf_fifo_d_32; +wire [8:0] rx_uc_fifo_d_u2; +wire rx_sf_almost_full_01, rx_sf_almost_full_02, rx_sf_almost_full_03; +wire rx_sf_almost_full_10, rx_sf_almost_full_12, rx_sf_almost_full_13; +wire rx_sf_almost_full_20, rx_sf_almost_full_21, rx_sf_almost_full_23; +wire [2:0] tx_src_sel0, tx_src_sel1, tx_src_sel2, tx_src_sel3; + + +// between switch and mac +wire [8:0] tx_sw_fifo_d0, tx_sw_fifo_d1, tx_sw_fifo_d2, tx_sw_fifo_d3, tx_sw_fifo_du; +wire [3:0] tx_sc_fifo_re; +wire tx_uc_fifo_re; +wire [3:0] tx_sw_fifo_empty; +wire tx_sw_fifo_we; + +wire [2:0] tx_sw_mode0, tx_sw_mode1, tx_sw_mode2, tx_sw_mode3; +wire tx_sw_modeu; +wire [3:0] tx_sc_done; + +// 100 Mbit +wire[3:0] mode_100Mbit; + +wire pkt_filter_sel_01, pkt_filter_sel_02, pkt_filter_sel_03; +wire pkt_filter_sel_10, pkt_filter_sel_12, pkt_filter_sel_13; +wire pkt_filter_sel_20, pkt_filter_sel_21, pkt_filter_sel_23, pkt_filter_sel_2u; +wire pkt_filter_sel_u2; + +// FCS +wire [1:0] fcs_addr0, fcs_addr1, fcs_addr2, fcs_addr3; +wire [7:0] fcs_din0, fcs_din1, fcs_din2, fcs_din3; +wire [7:0] fcs_dout0, fcs_dout1, fcs_dout2, fcs_dout3; +wire[3:0] fcs_init, fcs_enable; + +// half FIFO / DPRAM interface for uP +wire hfifo_we, hfifo_re; +wire [8:0] hfifo_tx_d, hfifo_rx_d; +wire hfifo_empty; +wire micro_fifo_int; +wire tx_uc_block; + +// SCI +wire[1:0] sci_sel_dual; +wire[3:0] sci_sel_ch; +wire[7:0] sci_rddata0, sci_rddata1 ; +wire[1:0] sci_int; + +// Metrics +wire tx_custom, metrics_start; +wire [8:0] metrics_d; + +// Network Debug & Metrics +reg [3:0] rx_active, tx_active; +wire [3:0] mac_rx_active; +wire [3:0] drop_rx0_active, drop_rx1_active, drop_rx2_active, drop_rx3_active; +wire [3:0] sync_rx0_active, sync_rx1_active, sync_rx2_active, sync_rx3_active; +wire [3:0] mac_tx_active; +wire [3:0] rx_sc_error; +wire [3:0] rx_eop, rx_sop; +wire [3:0] tx_eop, tx_sop; +wire [10:0] rx0_byte_cnt, rx1_byte_cnt, rx2_byte_cnt, rx3_byte_cnt; +wire [10:0] tx0_byte_cnt, tx1_byte_cnt, tx2_byte_cnt, tx3_byte_cnt; + +// Debug LEDs +reg lsm_status, rx_cdr_lol, rx_los_low; + +// Misc Debug +wire ext_sci_int; + +/**************************** + * + * Logic Begins Below + * + ***************************/ + +/* Lattice requires GSR to be in top-level module and be named GSR_INST */ +GSR GSR_INST(.GSR(rstn)); +PUR PUR_INST(.PUR(1'b1)); + +assign phy_mdc = clk_10; + +assign phy0_resetn = phy_resetn[0]; +assign phy1_resetn = phy_resetn[1]; + +`ifdef SHIELD_GIGE_SMA + assign phy2_resetn = phy_resetn[2]; + assign phy2_mdc = clk_10; +`elsif SHIELD_SFP_SMA + assign sfp_tx_disable = 1'b0; + assign sfp_i2c_scl = 1'b1; + assign sfp_rate_select = 1'b1; +`endif + + +/* + * Clocks derived from the internal OSCG + */ +clk_gen clk_gen_0( + .rstn( rstn ), + .clk_10( clk_10 ), + .clk_5( ), + .clk_2_5( ), + .clk_1_25( clk_1_25 ), + .clk_slow( clk_slow ) +); + + +/* +* main controller +* +* controls worker blocks +* interfaces with uC via I2C +* +*/ +controller #(.ADDR_SZ( MDIO_ROM_ADDR_SZ ))controller_0 +( + .rstn( rstn ), + .clk( clk_10 ), + .init(1'b1), + .pulse_100ms( 1'b0 ), + // PCS status lines + .pcs_rx_error( pcs_error ), + .pll_lol( pll_lol ), + // link status + .port_up( phy_up ), +// .sfp_los(sfp_los), + // mdio_controller interface + .mdio_cont_start(mdio_cont_work_start), + .mdio_cont_done(mdio_cont_work_done), + .mdio_routine_addr( mdio_routine_addr ), + .mdio_run( mdio_run ), + // mdio_data params + .mdio_page( mdio_page_set ), + .mdio_reg_addr( mdio_reg_addr_set ), + .mdio_w_data_h( mdio_w_data_h_set ), + .mdio_w_data_l( mdio_w_data_l_set ), + // bin_to_ascii interface + .bin_to_ascii_run( bin_to_ascii_run ), + // ext_sys_fifo interface: controller to external I/F FIFO + .fifo_mux_sel( read_fifo_mux_sel ), + .fifo_we( cont_rd_we ), + .read_fifo_d_o( cont_rd ), + // i2c interface + .i2c_rx_we ( i2c_cont_we ), + .i2c_rx_done ( i2c_cont_done ), + .i2c_d_in( i2c_d_o ), + // reset and config + .pcs_rst_dual( pcs_rst_dual ), + .serdes_rst_dual( serdes_rst_dual ), + .tx_serdes_rst( tx_serdes_rst ), + .phy_resetn( phy_resetn ), + .mac_reset( mac_reset ), + .tx_pcs_rst( tx_pcs_rst ), + .rx_serdes_rst( rx_serdes_rst ), + .rx_pcs_rst( rx_pcs_rst ), + .mdio_mux_sel( mdio_mux_sel ), + // TX custom packet + .tx_custom( tx_custom ) + +); + +/* + * Controls the routing of data and transmit modes + */ +switch switch_0( + .rstn( rstn ), + .clk( pcs_pclk ), + // PHY status + .phy_up( phy_up ), + .mode_100Mbit ( mode_100Mbit ), + // FIFO input data from RX FIFOs + .rx_d_01( rx_sf_fifo_d_01 ), + .rx_d_02( rx_sf_fifo_d_02 ), + .rx_d_03( rx_sf_fifo_d_03 ), + .rx_d_10( rx_sf_fifo_d_10 ), + .rx_d_12( rx_sf_fifo_d_12 ), + .rx_d_13( rx_sf_fifo_d_13 ), + .rx_d_20( rx_sf_fifo_d_20 ), + .rx_d_21( rx_sf_fifo_d_21 ), + .rx_d_23( rx_sf_fifo_d_23 ), + .rx_d_2u( rx_sf_fifo_d_2u ), + .rx_d_30( rx_sf_fifo_d_30 ), + .rx_d_31( rx_sf_fifo_d_31 ), + .rx_d_32( rx_sf_fifo_d_32 ), + .rx_d_u2( rx_uc_fifo_d_u2 ), + // RX FIFO read enables + .rx_fifo_re_01( rx_sw_fifo_re_01 ), + .rx_fifo_re_02( rx_sw_fifo_re_02 ), + .rx_fifo_re_03( rx_sw_fifo_re_03 ), + .rx_fifo_re_10( rx_sw_fifo_re_10 ), + .rx_fifo_re_12( rx_sw_fifo_re_12 ), + .rx_fifo_re_13( rx_sw_fifo_re_13 ), + .rx_fifo_re_20( rx_sw_fifo_re_20 ), + .rx_fifo_re_21( rx_sw_fifo_re_21 ), + .rx_fifo_re_23( rx_sw_fifo_re_23 ), + .rx_fifo_re_2u( rx_sw_fifo_re_2u ), + .rx_fifo_re_30( rx_sw_fifo_re_30 ), + .rx_fifo_re_31( rx_sw_fifo_re_31 ), + .rx_fifo_re_32( rx_sw_fifo_re_32 ), + .rx_fifo_re_u2( rx_sw_fifo_re_u2 ), + // RX FIFO Empty flags + .rx_fifo_empty_01( rx_sf_fifo_empty_01 ), + .rx_fifo_empty_02( rx_sf_fifo_empty_02 ), + .rx_fifo_empty_03( rx_sf_fifo_empty_03 ), + .rx_fifo_empty_10( rx_sf_fifo_empty_10 ), + .rx_fifo_empty_12( rx_sf_fifo_empty_12 ), + .rx_fifo_empty_13( rx_sf_fifo_empty_13 ), + .rx_fifo_empty_20( rx_sf_fifo_empty_20 ), + .rx_fifo_empty_21( rx_sf_fifo_empty_21 ), + .rx_fifo_empty_23( rx_sf_fifo_empty_23 ), + .rx_fifo_empty_2u( rx_sf_fifo_empty_2u ), + .rx_fifo_empty_30( rx_sf_fifo_empty_30 ), + .rx_fifo_empty_31( rx_sf_fifo_empty_31 ), + .rx_fifo_empty_32( rx_sf_fifo_empty_32 ), + .rx_fifo_empty_u2( rx_uc_fifo_empty_u2 ), + // RX Byte Count + .rx_wr_done(rx_sc_wr_done), + .rx0_byte_cnt(rx0_byte_cnt), + .rx1_byte_cnt(rx1_byte_cnt), + .rx2_byte_cnt(rx2_byte_cnt), + .rx3_byte_cnt(rx3_byte_cnt), + // TX FIFO output from internal muxes + .tx_d0( tx_sw_fifo_d0), + .tx_d1( tx_sw_fifo_d1 ), + .tx_d2( tx_sw_fifo_d2 ), + .tx_d3( tx_sw_fifo_d3 ), + .tx_du( tx_sw_fifo_du ), + // TX FIFO read enable inputs (need to route to RX output FIFOs) + .tx_fifo_re( tx_sc_fifo_re ), + .tx_fifo_we_u ( tx_sw_fifo_we ), + // TX FIFO Empty Flags (need to route to RX output FIFOs) + .tx_fifo_empty( tx_sw_fifo_empty ), + // TX modes for the PHYs and uc + .tx_mode0( tx_sw_mode0 ), + .tx_mode1( tx_sw_mode1 ), + .tx_mode2( tx_sw_mode2 ), + .tx_mode3( tx_sw_mode3 ), + .tx_modeu( tx_modeu ), + // TX byte cnt + .tx0_byte_cnt(tx0_byte_cnt), + .tx1_byte_cnt(tx1_byte_cnt), + .tx2_byte_cnt(tx2_byte_cnt), + .tx3_byte_cnt(tx3_byte_cnt), + // TX state machine done flag + .tx_f( tx_sc_done ), + // TX custom packet + .tx_custom ( tx_custom ) +); + + +/* + * RX and TX controller logic tied to PCS/SGMII protocol + */ +mac mac_0( + .rstn( ~mac_reset[0] ), + .phy_resetn ( phy_resetn[0] ), + .clk( pcs_pclk ), + .tap_port ( 1'b0 ), + // PCS / SERDES health + .rx_lsm( sgmii_lsm_status[0] ), + .rx_cv_err ( sgmii_rx_cv_err[0] ), + .rx_disp_err( sgmii_rx_disp_err[0] ), + .rx_cdr_lol( sgmii_rx_cdr_lol[0] ), + .rx_los ( sgmii_rx_los_low[0] ), + // AN + .phy_type(2'b00), // SGMII=0 + .pulse_1_6ms(pulse_1_6ms), + .pulse_10ms(pulse_10ms), + .fixed_speed(SGMII_SPEED_AN), + .an_disable( 1'b0 ), + .an_duplex( ), + .phy_up( phy_up[0] ), + .mode_100Mbit( mode_100Mbit[0] ), + // Switch I/F + .tx_mode( tx_sw_mode0 ), + .tx_f( tx_sc_done[0] ), + // PCS data I/F + .rx_k( sgmii_rx_k[0] ), + .rx_data( rx_data0 ), + .tx_k( sgmii_tx_k[0] ), + .tx_data( tx_data0 ), + .tx_disp_correct( sgmii_tx_disp_correct[0] ), + // TX FCS + .fcs_init( fcs_init[0] ), + .fcs_enable( fcs_enable[0] ), + .fcs_addr( fcs_addr0 ), + .fcs_dout( fcs_din0 ), + .fcs_din( fcs_dout0 ), + // MAC RX / FIFO Write + .rx_fifo_we( rx_sc_fifo_we[0] ), + .rx_fifo_d( rx_sc_fifo_d0 ), + .rx_error( rx_sc_error[0] ), + .rx_keep( rx_mac_keep[0] ), + .rx_wr_done( rx_sc_wr_done[0] ), + .rx_byte_cnt(rx0_byte_cnt), + .rx_mode(), + // MAC TX / FIFO Read + .tx_byte_cnt_i(tx0_byte_cnt), + .tx_src_sel(tx_src_sel0), + .tx_fifo_re( tx_sc_fifo_re[0] ), + .tx_fifo_d( tx_sw_fifo_d0 ), + .tx_fifo_empty( tx_sw_fifo_empty[0] ), + // Packet Filter + .rx_sample( rx_sample[0] ), + .ipv4_pkt_start( ipv4_pkt_start[0] ), + .trigger( ), + .rx_k_m1( rx0_k_m1 ), + .rx_k_m2( rx0_k_m2 ), + .rx_k_m3( rx0_k_m3), + .rx_k_m4( rx0_k_m4 ), + .rx_data_m1( rx0_data_m1 ), + .rx_data_m2( rx0_data_m2 ), + .rx_data_m3( rx0_data_m3), + .rx_data_m4( rx0_data_m4 ), + // Param RAM + .dpr_ad( param_phy0_addr ), + .dpr_we( param_phy0_we ), + .dpr_ce( param_phy0_ce ), + .dpr_di( param_phy0_din ), + .dpr_do( param_phy0_dout ), + // Flags, Metrics, Interrupts, and Debug + .rx_enet_bcast( rx_enet_bcast[0] ), + .rx_ipv4_arp( rx_ipv4_arp[0] ), + .mac_int( mac_int[0] ), + .rx_sop( rx_sop[0] ), + .rx_eop( rx_eop[0] ), + .tx_sop( tx_sop[0] ), + .tx_eop( tx_eop[0] ), + .metrics_start ( ), + .metrics_d ( 9'h0 ), + .rx_active( mac_rx_active[0] ), + .tx_active( mac_tx_active[0] ) +); + + +ipv4_rx ipv4_rx_0( + .rstn( rstn ), + .clk( pcs_pclk ), + // control + .phy_resetn ( phy_resetn[0] ), + .phy_up( phy_up[0] ), + // packet data + .pkt_start( ipv4_pkt_start[0] ), + .rx_eop( rx_eop[0] ), + .rx_data_m1( rx0_data_m1 ), + .rx_data_m2( rx0_data_m2 ), + .rx_data_m3( rx0_data_m3), + .rx_data_m4( rx0_data_m4 ), + // flags + .pkt_complete(ipv4_pkt_complete[0]), + .trigger_src_addr( ), + .trigger_dst_addr( trigger[0] ), + .keep( ) + ); + + +pkt_filter pkt_filter_01( + .rstn( rstn ), + .clk( pcs_pclk ), + // input for programming + .sel( pkt_filter_sel_01 ), + .we( mem_we ), + .addr( mem_addr[3:0] ), + .d_in( mem_d_i[7:0] ), + // registered data + .rx_data_m1( rx0_data_m1 ), + .rx_data_m2( rx0_data_m2 ), + .rx_data_m3( rx0_data_m3), + .rx_data_m4( rx0_data_m4 ), + // filter + .new_frame ( rx_sop[0] ), + .block( 1'b0 ), + .invert( 1'b1 ), + .trigger( trigger[0] ), + .keep( rx_pf_keep_01 ) +); + +drop_fifo drop_fifo_01( + .rstn( rstn ), + .clk ( pcs_pclk ), + .enable( 1'b1 ), + // control + .keep ( rx_pf_keep_01 | rx_mac_keep[0] ), + .passthrough( 1'b0 ), + // input + .we_in( rx_sc_fifo_we[0] ), + .wr_done( rx_sc_wr_done[0] ), + .d_in( rx_sc_fifo_d0 ), + // output + .we_out( rx_df_fifo_we_01 ), + .d_out( rx_df_fifo_d_01 ), + // debug + .active( drop_rx0_active[1] ) +); + +sync_fifo sync_fifo_rx_01( + .rstn( rstn ), + .clk ( pcs_pclk ), + // input + .we ( rx_df_fifo_we_01 & phy_up[1] ), + .d_in ( rx_df_fifo_d_01 ), + // output + .re ( rx_sw_fifo_re_01 ), + .d_out( rx_sf_fifo_d_01 ), + .empty( rx_sf_fifo_empty_01 ), + .almost_full( ), + .reset_ptrs( 1'b0 ), + // debug + .active( sync_rx0_active[1] ) +); + +pkt_filter pkt_filter_02( + .rstn( rstn ), + .clk( pcs_pclk ), + // input for programming + .sel( pkt_filter_sel_02 ), + .we( mem_we ), + .addr( mem_addr[3:0] ), + .d_in( mem_d_i[7:0] ), + // registered data + .rx_data_m1( rx0_data_m1 ), + .rx_data_m2( rx0_data_m2 ), + .rx_data_m3( rx0_data_m3), + .rx_data_m4( rx0_data_m4 ), + // filter + .new_frame ( rx_sop[0] ), + .block( rx_sf_almost_full_02 ), + .invert(1'b1), + .trigger(trigger[0]), + .keep( rx_pf_keep_02 ) +); + +drop_fifo drop_fifo_02( + .rstn( rstn ), + .clk ( pcs_pclk ), + .enable( 1'b1 ), + // control + .keep ( rx_pf_keep_02 | rx_mac_keep[0] ), + .passthrough( 1'b0 ), + // input + .we_in( rx_sc_fifo_we[0] ), + .wr_done( rx_sc_wr_done[0] ), + .d_in( rx_sc_fifo_d0 ), + // output + .we_out( rx_df_fifo_we_02 ), + .d_out( rx_df_fifo_d_02 ), + .active( drop_rx0_active[2] ) + ); + +sync_fifo sync_fifo_rx_02( + .rstn( rstn ), + .clk ( pcs_pclk ), + // input + .we ( rx_df_fifo_we_02 & phy_up[2] ), + .d_in ( rx_df_fifo_d_02 ), + // output + .re ( rx_sw_fifo_re_02 ), + .d_out( rx_sf_fifo_d_02 ), + .empty( rx_sf_fifo_empty_02 ), + .almost_full( rx_sf_almost_full_02 ), + .reset_ptrs( 1'b0 ), + // debug + .active(sync_rx0_active[2] ) +); + + +pkt_filter pkt_filter_03( + .rstn( rstn ), + .clk( pcs_pclk ), + // input for programming + .sel( pkt_filter_sel_03 ), + .we( mem_we ), + .addr( mem_addr[3:0] ), + .d_in( mem_d_i[7:0] ), + // registered data + .rx_data_m1( rx0_data_m1 ), + .rx_data_m2( rx0_data_m2 ), + .rx_data_m3( rx0_data_m3), + .rx_data_m4( rx0_data_m4 ), + // filter + .new_frame ( rx_sop[0] ), + .block( rx_sf_almost_full_03 ), + .invert( 1'b0 ), + .trigger( trigger[0] ), + .keep( rx_pf_keep_03 ) + ); + +drop_fifo drop_fifo_03( + .rstn( rstn ), + .clk ( pcs_pclk ), + .enable( 1'b0 ), + // control + .keep ( rx_pf_keep_03 | rx_mac_keep[0] ), + .passthrough( 1'b0 ), + // input + .we_in( rx_sc_fifo_we[0] ), + .wr_done( rx_sc_wr_done[0] ), + .d_in( rx_sc_fifo_d0 ), + // output + .we_out( rx_df_fifo_we_03 ), + .d_out( rx_df_fifo_d_03 ), + .active( drop_rx0_active[3] ) + ); + +sync_fifo sync_fifo_rx_03( + .rstn( rstn ), + .clk ( pcs_pclk ), + // input + .we ( rx_df_fifo_we_03 & phy_up[3] ), + .d_in ( rx_df_fifo_d_03 ), + // output + .re ( rx_sw_fifo_re_03 ), + .d_out( rx_sf_fifo_d_03 ), + .empty( rx_sf_fifo_empty_03 ), + .almost_full( rx_sf_almost_full_03 ), + .reset_ptrs( 1'b0 ), + // debug + .active( sync_rx0_active[3] ) + ); + +fcs fcs_0( + .rstn( rstn ), + .clk( pcs_pclk ), + .init( fcs_init[0] ), + .enable( fcs_enable[0] ), + .addr( fcs_addr0 ), + .din( fcs_din0 ), + .dout( fcs_dout0 ) +); + +/* + * Param RAM + */ +dpram param_ram_0( + .rstn(rstn), + .a_clk(clk_10), + .a_clk_e(param_sel[0]), + .a_we(mem_we), + .a_oe(mem_oe), + .a_addr(mem_addr), + .a_din(mem_d_i[8:0]), + .a_dout(param_ram_0_do), + // port B + .b_clk( pcs_pclk), + .b_clk_e(param_phy0_ce), + .b_we(param_phy0_we), + .b_oe( 1'b1 ), + .b_addr( param_phy0_addr ), + .b_din( param_phy0_dout ), + .b_dout( param_phy0_din ) + ); + +mac mac_1( + .rstn( ~mac_reset[1] ), + .phy_resetn ( phy_resetn[1] ), + .clk( pcs_pclk ), + .tap_port ( 1'b0 ), + // PCS / SERDES health + .rx_lsm( sgmii_lsm_status[1] ), + .rx_cv_err ( sgmii_rx_cv_err[1] ), + .rx_disp_err( sgmii_rx_disp_err[1] ), + .rx_cdr_lol( sgmii_rx_cdr_lol[1] ), + .rx_los ( sgmii_rx_los_low[1] ), + // AN + .phy_type(2'b00), // SGMII==0 + .pulse_1_6ms(pulse_1_6ms), + .pulse_10ms(pulse_10ms), + .fixed_speed(SGMII_SPEED_AN), + .an_disable( 1'b0 ), + .an_duplex( ), + .phy_up( phy_up[1] ), + .mode_100Mbit( mode_100Mbit[1] ), + // Switch I/F + .tx_mode( tx_sw_mode1 ), + .tx_f( tx_sc_done[1] ), + // PCS data I/F + .rx_k( sgmii_rx_k[1] ), + .rx_data( rx_data1 ), + .tx_k( sgmii_tx_k[1] ), + .tx_data( tx_data1 ), + .tx_disp_correct( sgmii_tx_disp_correct[1] ), + // FCS + .fcs_init( fcs_init[1] ), + .fcs_enable( fcs_enable[1] ), + .fcs_addr( fcs_addr1 ), + .fcs_dout( fcs_din1 ), + .fcs_din( fcs_dout1 ), + // MAC RX / FIFO Write + .rx_fifo_we( rx_sc_fifo_we[1] ), + .rx_fifo_d( rx_sc_fifo_d1 ), + .rx_error( rx_sc_error[1] ), + .rx_keep( rx_mac_keep[1] ), + .rx_wr_done( rx_sc_wr_done[1] ), + .rx_byte_cnt(rx1_byte_cnt), + .rx_mode(), + // MAC TX / FIFO Read + .tx_byte_cnt_i(tx1_byte_cnt), + .tx_src_sel(tx_src_sel1), + .tx_fifo_re( tx_sc_fifo_re[1] ), + .tx_fifo_d( tx_sw_fifo_d1 ), + .tx_fifo_empty( tx_sw_fifo_empty[1] ), + // Packet Filter + .rx_sample( ), + .ipv4_pkt_start( ipv4_pkt_start[1] ), + .trigger( ), + .rx_k_m1( rx1_k_m1 ), + .rx_k_m2( rx1_k_m2 ), + .rx_k_m3( rx1_k_m3), + .rx_k_m4( rx1_k_m4 ), + .rx_data_m1( rx1_data_m1 ), + .rx_data_m2( rx1_data_m2 ), + .rx_data_m3( rx1_data_m3), + .rx_data_m4( rx1_data_m4 ), + // Param RAM + .dpr_ad( param_phy1_addr ), + .dpr_we( param_phy1_we), + .dpr_ce(param_phy1_ce ), + .dpr_di(param_phy1_din), + .dpr_do(param_phy1_dout), + // Flags, Metrics, Interrupts, and Debug + .rx_enet_bcast( rx_enet_bcast[1] ), + .rx_ipv4_arp( rx_ipv4_arp[1] ), + .mac_int( mac_int[1] ), + .rx_sop( rx_sop[1] ), + .rx_eop( rx_eop[1] ), + .tx_sop( tx_sop[1] ), + .tx_eop( tx_eop[1] ), + .metrics_start ( ), + .metrics_d ( 9'h0 ), + .rx_active( mac_rx_active[1] ), + .tx_active( mac_tx_active[1] ) +); + +ipv4_rx ipv4_rx_1( + .rstn( rstn ), + .clk( pcs_pclk ), + // control + .phy_resetn ( phy_resetn[1] ), + .phy_up( phy_up[1] ), + // packet data + .pkt_start( ipv4_pkt_start[1] ), + .rx_eop( rx_eop[1] ), + .rx_data_m1( rx1_data_m1 ), + .rx_data_m2( rx1_data_m2 ), + .rx_data_m3( rx1_data_m3), + .rx_data_m4( rx1_data_m4 ), + // flags + .pkt_complete(ipv4_pkt_complete[1]), + .trigger_src_addr( ), + .trigger_dst_addr( trigger[1] ), + .keep( ) + ); + +pkt_filter #(.DEPTH(8), .DEPTHW(3), .WIDTH(32)) pkt_filter_10( + .rstn( rstn ), + .clk( pcs_pclk ), + // input for programming + .sel( pkt_filter_sel_10 ), + .we( mem_we ), + .addr( mem_addr[4:0] ), + .d_in( mem_d_i[7:0] ), + // registered data + .rx_data_m1( rx1_data_m1 ), + .rx_data_m2( rx1_data_m2 ), + .rx_data_m3( rx1_data_m3), + .rx_data_m4( rx1_data_m4 ), + // filter + .new_frame ( rx_sop[1] ), + .block( 1'b0 ), + .invert( 1'b1 ), + .trigger( trigger[1] ), + .keep( rx_pf_keep_10 ) + ); + +drop_fifo drop_fifo_10( + .rstn( rstn ), + .clk ( pcs_pclk ), + .enable( 1'b1 ), + // control + .keep ( rx_pf_keep_10 | rx_mac_keep[1] ), + .passthrough( 1'b0 ), + // input + .we_in( rx_sc_fifo_we[1] ), + .wr_done( rx_sc_wr_done[1] ), + .d_in( rx_sc_fifo_d1 ), + // output + .we_out( rx_df_fifo_we_10 ), + .d_out( rx_df_fifo_d_10 ), + // debug + .active( drop_rx1_active[0] ) + ); + +sync_fifo sync_fifo_rx_10( + .rstn( rstn ), + .clk ( pcs_pclk ), + // input / RX + .we ( rx_df_fifo_we_10 & phy_up[0] ), + .d_in ( rx_df_fifo_d_10 ), + // output / TX + .re ( rx_sw_fifo_re_10 ), + .d_out( rx_sf_fifo_d_10 ), + .empty( rx_sf_fifo_empty_10 ), + .almost_full( ), + .reset_ptrs( 1'b0 ), + // debug + .active( sync_rx1_active[0] ) +); + +pkt_filter pkt_filter_12( + .rstn( rstn ), + .clk( pcs_pclk ), + // input for programming + .sel( pkt_filter_sel_12 ), + .we( mem_we ), + .addr( mem_addr[3:0] ), + .d_in( mem_d_i[7:0] ), + // registered data + .rx_data_m1( rx1_data_m1 ), + .rx_data_m2( rx1_data_m2 ), + .rx_data_m3( rx1_data_m3), + .rx_data_m4( rx1_data_m4 ), + // filter + .new_frame ( rx_sop[1] ), + .block( rx_sf_almost_full_12 ), + .invert( 1'b1 ), + .trigger( trigger[1] ), + .keep( rx_pf_keep_12 ) + ); + +drop_fifo drop_fifo_12( + .rstn( rstn ), + .clk ( pcs_pclk ), + .enable(1'b1), + // control + .keep ( rx_pf_keep_12 | rx_mac_keep[1] ), + .passthrough( 1'b0 ), + // input + .we_in( rx_sc_fifo_we[1] ), + .wr_done( rx_sc_wr_done[1] ), + .d_in( rx_sc_fifo_d1 ), + // output + .we_out( rx_df_fifo_we_12 ), + .d_out( rx_df_fifo_d_12 ), + // debug + .active( drop_rx1_active[2] ) + ); + +sync_fifo sync_fifo_rx_12( + .rstn( rstn ), + .clk ( pcs_pclk ), + // input / RX + .we ( rx_df_fifo_we_12 & phy_up[2] ), + .d_in ( rx_df_fifo_d_12 ), + // output / TX + .re ( rx_sw_fifo_re_12 ), + .d_out( rx_sf_fifo_d_12 ), + .empty( rx_sf_fifo_empty_12 ), + .almost_full( rx_sf_almost_full_12 ), + .reset_ptrs( 1'b0 ), + // debug + .active( sync_rx1_active[2] ) +); + +pkt_filter pkt_filter_13( + .rstn( rstn ), + .clk( pcs_pclk ), + // input for programming + .sel( pkt_filter_sel_13 ), + .we( mem_we ), + .addr( mem_addr[3:0] ), + .d_in( mem_d_i[7:0] ), + // registered data + .rx_data_m1( rx1_data_m1 ), + .rx_data_m2( rx1_data_m2 ), + .rx_data_m3( rx1_data_m3), + .rx_data_m4( rx1_data_m4 ), + // filter + .new_frame ( rx_sop[1] ), + .block( 1'b0 ), + .invert( 1'b0 ), + .trigger( trigger[1] ), + .keep( rx_pf_keep_13 ) + ); + +drop_fifo drop_fifo_13( + .rstn( rstn ), + .clk ( pcs_pclk ), + .enable( 1'b0 ), + // control + .keep ( rx_pf_keep_13 | rx_mac_keep[1] ), + .passthrough( 1'b0 ), + // input + .we_in( rx_sc_fifo_we[1] ), + .wr_done( rx_sc_wr_done[1] ), + .d_in( rx_sc_fifo_d1 ), + // output + .we_out( rx_df_fifo_we_13 ), + .d_out( rx_df_fifo_d_13 ), + // debug + .active( drop_rx1_active[3] ) + ); + +sync_fifo sync_fifo_rx_13( + .rstn( rstn ), + .clk ( pcs_pclk ), + // input / RX + .we ( rx_df_fifo_we_13 & phy_up[3] ), + .d_in ( rx_df_fifo_d_13 ), + // output / TX + .re ( rx_sw_fifo_re_13 ), + .d_out( rx_sf_fifo_d_13 ), + .empty( rx_sf_fifo_empty_13 ), + .almost_full( ), + .reset_ptrs( 1'b0 ), + // debug + .active( sync_rx1_active[3] ) + ); + +fcs fcs_1( + .rstn( rstn ), + .clk( pcs_pclk ), + .init( fcs_init[1] ), + .enable( fcs_enable[1] ), + .addr( fcs_addr1 ), + .din( fcs_din1 ), + .dout( fcs_dout1 ) +); + +/* + * Param RAM + */ +dpram param_ram_1( + .rstn(rstn), + .a_clk(clk_10), + .a_clk_e(param_sel[0]), + .a_we(mem_we), + .a_oe(mem_oe), + .a_addr(mem_addr), + .a_din(mem_d_i[8:0]), + .a_dout(param_ram_1_do), + // port B + .b_clk( pcs_pclk), + .b_clk_e(param_phy1_ce), + .b_we(param_phy1_we), + .b_oe( 1'b1 ), + .b_addr( param_phy1_addr ), + .b_din( param_phy1_dout ), + .b_dout( param_phy1_din ) + ); + + +metrics metrics_2( + .rstn( rstn ), + .clk( pcs_pclk ), + .mode_100Mbit( mode_100Mbit[2] ), + // input data for gathering metrics + .rx_mac_keep( rx_mac_keep ), + .rx_pf_keep_01( rx_pf_keep_01 ), + .rx_pf_keep_02( rx_pf_keep_02 ), + .rx_pf_keep_10( rx_pf_keep_10 ), + .rx_pf_keep_12( rx_pf_keep_12 ), + .rx_pf_keep_20( rx_pf_keep_20 ), + .rx_pf_keep_21( rx_pf_keep_21 ), + .rx_pf_keep_23( rx_pf_keep_23 ), + + .rx_sop( rx_sop ), + .rx_eop( rx_eop ), + .tx_sop( tx_sop ), + .tx_eop( tx_eop ), + // metric outputs + .metrics_start ( metrics_start ), + .metrics_d( metrics_d ) +); + +mac mac_2( + .rstn(~mac_reset[2]), + .phy_resetn ( phy_resetn[2] ), + .clk( pcs_pclk ), + .tap_port ( 1'b0 ), + // PCS / SERDES health + .rx_lsm( 1'b1 ), // TODO: Fix LSM for SFP + .rx_cv_err ( sgmii_rx_cv_err[2] ), + .rx_disp_err( sgmii_rx_disp_err[2] ), + .rx_cdr_lol( sgmii_rx_cdr_lol[2] ), + .rx_los ( sgmii_rx_los_low[2] ), + // AN + .phy_type(2'b01), // SX==1 + .pulse_1_6ms(pulse_1_6ms), + .pulse_10ms(pulse_10ms), + .fixed_speed(SGMII_SPEED_1GBIT), + .an_disable( 1'b0 ), + .an_duplex( ), + .phy_up( phy_up[2] ), + .mode_100Mbit( mode_100Mbit[2] ), + // Switch I/F + .tx_mode( tx_sw_mode2 ), + .tx_f( tx_sc_done[2] ), + // PCS data I/F + .rx_k( sgmii_rx_k[2] ), + .rx_data( rx_data2 ), + .tx_k( sgmii_tx_k[2] ), + .tx_data( tx_data2 ), + .tx_disp_correct( sgmii_tx_disp_correct[2] ), + // FCS + .fcs_init( fcs_init[2] ), + .fcs_enable( fcs_enable[2] ), + .fcs_addr( fcs_addr2 ), + .fcs_dout( fcs_din2 ), + .fcs_din( fcs_dout2 ), + // MAC RX / FIFO Write + .rx_fifo_we( rx_sc_fifo_we[2] ), + .rx_fifo_d(rx_sc_fifo_d2), + .rx_error( rx_sc_error[2] ), + .rx_keep( rx_mac_keep[2] ), + .rx_wr_done( rx_sc_wr_done[2] ), + .rx_byte_cnt(rx2_byte_cnt), + .rx_mode(), + // MAC TX / FIFO Read + .tx_byte_cnt_i(tx2_byte_cnt), + .tx_src_sel(tx_src_sel2), + .tx_fifo_re( tx_sc_fifo_re[2] ), + .tx_fifo_d( tx_sw_fifo_d2 ), + .tx_fifo_empty( tx_sw_fifo_empty[2]), + // Packet Filter + .rx_sample( ), + .ipv4_pkt_start( ipv4_pkt_start[2] ), + .trigger( ), + .rx_k_m1( rx2_k_m1 ), + .rx_k_m2( rx2_k_m2 ), + .rx_k_m3( rx2_k_m3), + .rx_k_m4( rx2_k_m4 ), + .rx_data_m1( rx2_data_m1 ), + .rx_data_m2( rx2_data_m2 ), + .rx_data_m3( rx2_data_m3), + .rx_data_m4( rx2_data_m4 ), + // Param RAM + .dpr_ad( param_phy2_addr ), + .dpr_we( param_phy2_we ), + .dpr_ce( param_phy2_ce ), + .dpr_di( param_phy2_din ), + .dpr_do( param_phy2_dout ), + // Flags, Metrics, Interrupts, and Debug + .rx_enet_bcast( rx_enet_bcast[2] ), + .rx_ipv4_arp( rx_ipv4_arp[2] ), + .mac_int( mac_int[2] ), + .rx_sop( rx_sop[2] ), + .rx_eop( rx_eop[2] ), + .tx_sop( tx_sop[2] ), + .tx_eop( tx_eop[2] ), + .metrics_start ( metrics_start ), + .metrics_d( metrics_d ), + .rx_active( mac_rx_active[2] ), + .tx_active( mac_tx_active[2] ) +); + +ipv4_rx ipv4_rx_2( + .rstn( rstn ), + .clk( pcs_pclk ), + // control + .phy_resetn ( phy_resetn[2] ), + .phy_up( phy_up[2] ), + // packet data + .pkt_start( ipv4_pkt_start[2] ), + .rx_eop( rx_eop[2] ), + .rx_data_m1( rx2_data_m1 ), + .rx_data_m2( rx2_data_m2 ), + .rx_data_m3( rx2_data_m3), + .rx_data_m4( rx2_data_m4 ), + // flags + .pkt_complete(ipv4_pkt_complete[2]), + .trigger_src_addr( ), + .trigger_dst_addr( trigger[2] ), + .keep( ) + ); + + +pkt_filter pkt_filter_20( + .rstn( rstn ), + .clk( pcs_pclk ), + // input for programming + .sel( pkt_filter_sel_20 ), + .we( mem_we ), + .addr( mem_addr[3:0] ), + .d_in( mem_d_i[7:0] ), + // registered data + .rx_data_m1( rx2_data_m1 ), + .rx_data_m2( rx2_data_m2 ), + .rx_data_m3( rx2_data_m3), + .rx_data_m4( rx2_data_m4 ), + // filter + .new_frame ( rx_sop[2] ), + .block( rx_sf_almost_full_20 ), + .invert( 1'b0 ), + .trigger( trigger[2] ), + .keep( rx_pf_keep_20 ) +); + +drop_fifo drop_fifo_20( + .rstn( rstn ), + .clk ( pcs_pclk ), + .enable( 1'b0 ), + // control + .keep ( rx_pf_keep_20 | rx_mac_keep[2] ), + .passthrough( 1'b0 ), + // input + .we_in( rx_sc_fifo_we[2] ), + .wr_done( rx_sc_wr_done[2] ), + .d_in( rx_sc_fifo_d2 ), + // output + .we_out( rx_df_fifo_we_20 ), + .d_out( rx_df_fifo_d_20 ), + // debug + .active( drop_rx2_active[0] ) + ); + +sync_fifo sync_fifo_rx_20( + .rstn( rstn ), + .clk ( pcs_pclk ), + // input / RX + .we ( rx_df_fifo_we_20 & phy_up[0]), + .d_in ( rx_df_fifo_d_20 ), + // output / TX + .re ( rx_sw_fifo_re_20 ), + .d_out( rx_sf_fifo_d_20 ), + .empty( rx_sf_fifo_empty_20 ), + .almost_full( rx_sf_almost_full_20 ), + .reset_ptrs( 1'b0 ), + // debug + .active( sync_rx2_active[0] ) +); + +pkt_filter pkt_filter_21( + .rstn( rstn ), + .clk( pcs_pclk ), + // input for programming + .sel( pkt_filter_sel_21 ), + .we( mem_we ), + .addr( mem_addr[3:0] ), + .d_in( mem_d_i[7:0] ), + // registered data + .rx_data_m1( rx2_data_m1 ), + .rx_data_m2( rx2_data_m2 ), + .rx_data_m3( rx2_data_m3), + .rx_data_m4( rx2_data_m4 ), + // filter + .new_frame ( rx_sop[2] ), + .block( 1'b0 ), + .invert( 1'b0 ), + .trigger( trigger[2] ), + .keep( rx_pf_keep_21 ) +); + +drop_fifo drop_fifo_21( + .rstn( rstn ), + .clk ( pcs_pclk ), + .enable( 1'b0 ), + // control + .keep ( rx_pf_keep_21 | rx_mac_keep[2] ), + .passthrough( 1'b0 ), + // input + .we_in( rx_sc_fifo_we[2] ), + .wr_done( rx_sc_wr_done[2] ), + .d_in( rx_sc_fifo_d2 ), + // output + .we_out( rx_df_fifo_we_21 ), + .d_out( rx_df_fifo_d_21 ), + // debug + .active( drop_rx2_active[1] ) + ); + +sync_fifo sync_fifo_rx_21( + .rstn( rstn ), + .clk ( pcs_pclk ), + // input / RX + .we ( rx_df_fifo_we_21 & phy_up[1] ), + .d_in ( rx_df_fifo_d_21 ), + // output + .re ( rx_sw_fifo_re_21 ), + .d_out( rx_sf_fifo_d_21 ), + .empty( rx_sf_fifo_empty_21 ), + .almost_full( ), + .reset_ptrs( 1'b0 ), + // debug + .active( sync_rx2_active[1] ) +); + +pkt_filter pkt_filter_2u( + .rstn( rstn ), + .clk( pcs_pclk ), + // input for programming + .sel( pkt_filter_sel_2u ), + .we( mem_we ), + .addr( mem_addr[3:0] ), + .d_in( mem_d_i[7:0] ), + // registered data + .rx_data_m1( rx2_data_m1 ), + .rx_data_m2( rx2_data_m2 ), + .rx_data_m3( rx2_data_m3), + .rx_data_m4( rx2_data_m4 ), + // filter + .new_frame ( rx_sop[2] ), + .block( tx_uc_block ), + .invert( 1'b0 ), + .trigger( trigger[2] ), + .keep( rx_pf_keep_2u ) + ); + +drop_fifo drop_fifo_2u( + .rstn( rstn ), + .clk ( pcs_pclk ), + .enable( 1'b0 ), + // control + .passthrough( 1'b0 ), + .keep ( rx_pf_keep_2u | rx_mac_keep[2] ), + // input + .we_in( rx_sc_fifo_we[2] ), + .wr_done( rx_sc_wr_done[2] ), + .d_in( rx_sc_fifo_d2 ), + // output + .we_out( rx_df_fifo_we_2u ), + .d_out( rx_df_fifo_d_2u ), + // debug + .active( ) + ); + +// TODO: add a flag on we to keep UC from being overwritten +sync_fifo sync_fifo_rx_2u( + .rstn( rstn ), + .clk ( pcs_pclk ), + // input / RX + .we ( rx_df_fifo_we_2u ), + .d_in ( rx_df_fifo_d_2u ), + // output + .re ( rx_sw_fifo_re_2u ), + .d_out( rx_sf_fifo_d_2u ), + .empty( rx_sf_fifo_empty_2u ), + .almost_full( ), + .reset_ptrs( 1'b0 ), + // debug + .active( ) +); + +fcs fcs_2( + .rstn( rstn ), + .clk( pcs_pclk ), + .init( fcs_init[2] ), + .enable( fcs_enable[2] ), + .addr( fcs_addr2 ), + .din( fcs_din2 ), + .dout( fcs_dout2 ) +); + +mac mac_3( + .rstn( ~mac_reset[3] & ~sgmii_rx_los_low[3] ), + .phy_resetn ( phy_resetn[3] ), + .clk( pcs_pclk ), + .tap_port ( 1'b0 ), + // PCS / SERDES health + .rx_lsm( sgmii_lsm_status[3] ), + .rx_cv_err ( sgmii_rx_cv_err[3] ), + .rx_disp_err( sgmii_rx_disp_err[3] ), + .rx_cdr_lol( sgmii_rx_cdr_lol[3] ), + .rx_los ( sgmii_rx_los_low[3] ), + // MAC AN + .phy_type(2'b11), // SMA=3 + .pulse_1_6ms(pulse_1_6ms), + .pulse_10ms(pulse_10ms), + .fixed_speed(SGMII_SPEED_1GBIT), + .an_disable(1'b1), + .an_duplex( ), + .phy_up( phy_up[3] ), + .mode_100Mbit( mode_100Mbit[3] ), + // Switch I/F + .tx_mode( tx_sw_mode3 ), + .tx_f( tx_sc_done[3] ), + // PCS data I/F + .rx_k( sgmii_rx_k[3] ), + .rx_data( rx_data3 ), + .tx_k( sgmii_tx_k[3] ), + .tx_data( tx_data3 ), + .tx_disp_correct( sgmii_tx_disp_correct[3] ), + // Flags and Interrupts + .rx_keep( rx_mac_keep[3] ), + // TX FCS + .fcs_init( fcs_init[3] ), + .fcs_enable( fcs_enable[3] ), + .fcs_addr( fcs_addr3 ), + .fcs_dout( fcs_din3 ), + .fcs_din( fcs_dout3 ), + // MAC RX / FIFO Write + .rx_fifo_we( rx_sc_fifo_we[3] ), + .rx_fifo_d( rx_sc_fifo_d3 ), + .rx_error( rx_sc_error[3] ), + .rx_wr_done( rx_sc_wr_done[3] ), + .rx_byte_cnt(rx3_byte_cnt), + .rx_mode(), + // MAC TX / FIFO Read + .tx_byte_cnt_i(tx3_byte_cnt), + .tx_src_sel(tx_src_sel3), + .tx_fifo_re( tx_sc_fifo_re[3] ), + .tx_fifo_d( tx_sw_fifo_d3 ), + .tx_fifo_empty( tx_sw_fifo_empty[3] ), + // Packet Filter + .rx_sample( rx_sample[3] ), + .ipv4_pkt_start( ipv4_pkt_start[3] ), + .trigger( ), + .rx_k_m1( rx3_k_m1 ), + .rx_k_m2( rx3_k_m2 ), + .rx_k_m3( rx3_k_m3), + .rx_k_m4( rx3_k_m4 ), + .rx_data_m1( rx3_data_m1 ), + .rx_data_m2( rx3_data_m2 ), + .rx_data_m3( rx3_data_m3), + .rx_data_m4( rx3_data_m4 ), + // Param RAM + .dpr_ad( ), + .dpr_we( ), + .dpr_ce( ), + .dpr_di( 9'h0), + .dpr_do( ), + // Flags, Metrics, Interrupts, and Debug + .rx_enet_bcast( rx_enet_bcast[3] ), + .rx_ipv4_arp( rx_ipv4_arp[3] ), + .mac_int( mac_int[3] ), + .rx_sop( rx_sop[3] ), + .rx_eop( rx_eop[3] ), + .tx_sop( tx_sop[3] ), + .tx_eop( tx_eop[3] ), + .metrics_start ( ), + .metrics_d ( 9'h0 ), + .rx_active( mac_rx_active[3] ), + .tx_active( mac_tx_active[3] ) + ); + + +ipv4_rx ipv4_rx_3( + .rstn( rstn ), + .clk( pcs_pclk ), + // control + .phy_resetn ( phy_resetn[3] ), + .phy_up( phy_up[3] ), + // packet data + .pkt_start( ipv4_pkt_start[3] ), + .rx_eop( rx_eop[3] ), + .rx_data_m1( rx3_data_m1 ), + .rx_data_m2( rx3_data_m2 ), + .rx_data_m3( rx3_data_m3), + .rx_data_m4( rx3_data_m4 ), + // flags + .pkt_complete(ipv4_pkt_complete[3]), + .trigger_src_addr( ), + .trigger_dst_addr( trigger[3] ), + .keep( ) + ); + + + +pkt_filter pkt_filter_30( + .rstn( rstn ), + .clk( pcs_pclk ), + // input for programming + .sel( pkt_filter_sel_30 ), + .we( mem_we ), + .addr( mem_addr[3:0] ), + .d_in( mem_d_i[7:0] ), + // registered data + .rx_data_m1( rx3_data_m1 ), + .rx_data_m2( rx3_data_m2 ), + .rx_data_m3( rx3_data_m3), + .rx_data_m4( rx3_data_m4 ), + // filter + .new_frame ( rx_sop[3] ), + .block( 1'b0 ), + .invert( 1'b0 ), + .trigger( trigger[3] ), + .keep( rx_pf_keep_30 ) + ); + +drop_fifo drop_fifo_30( + .rstn( rstn ), + .clk ( pcs_pclk ), + .enable( 1'b0 ), + // control + .keep ( rx_pf_keep_30 | rx_mac_keep[3] ), + .passthrough( 1'b0 ), + // input + .we_in( rx_sc_fifo_we[3] ), + .wr_done( rx_sc_wr_done[3] ), + .d_in( rx_sc_fifo_d3 ), + // output + .we_out( rx_df_fifo_we_30 ), + .d_out( rx_df_fifo_d_30 ), + // debug + .active( drop_rx3_active[0] ) + ); + +sync_fifo sync_fifo_rx_30( + .rstn( rstn ), + .clk ( pcs_pclk ), + // input + .we ( rx_df_fifo_we_30 & phy_up[0] ), + .d_in ( rx_df_fifo_d_30 ), + // output + .re ( rx_sw_fifo_re_30 ), + .d_out( rx_sf_fifo_d_30 ), + .empty( rx_sf_fifo_empty_30 ), + .almost_full( ), + .reset_ptrs( 1'b0 ), + // debug + .active( sync_rx3_active[0] ) + ); + +pkt_filter pkt_filter_31( + .rstn( rstn ), + .clk( pcs_pclk ), + // input for programming + .sel( pkt_filter_sel_31 ), + .we( mem_we ), + .addr( mem_addr[3:0] ), + .d_in( mem_d_i[7:0] ), + // registered data + .rx_data_m1( rx3_data_m1 ), + .rx_data_m2( rx3_data_m2 ), + .rx_data_m3( rx3_data_m3), + .rx_data_m4( rx3_data_m4 ), + // filter + .new_frame ( rx_sop[3] ), + .block( 1'b0 ), + .invert( 1'b0 ), + .trigger( trigger[3] ), + .keep( rx_pf_keep_31 ) + ); + +drop_fifo drop_fifo_31( + .rstn( rstn ), + .clk ( pcs_pclk ), + .enable( 1'b0 ), + // control + .keep ( rx_pf_keep_31 | rx_mac_keep[3] ), + .passthrough( 1'b0 ), + // input + .we_in( rx_sc_fifo_we[3] ), + .wr_done( rx_sc_wr_done[3] ), + .d_in( rx_sc_fifo_d3 ), + // output + .we_out( rx_df_fifo_we_31 ), + .d_out( rx_df_fifo_d_31 ), + // debug + .active( drop_rx3_active[1] ) + ); + +sync_fifo sync_fifo_rx_31( + .rstn( rstn ), + .clk ( pcs_pclk ), + // input + .we ( rx_df_fifo_we_31 & phy_up[1] ), + .d_in ( rx_df_fifo_d_31 ), + // output + .re ( rx_sw_fifo_re_31 ), + .d_out( rx_sf_fifo_d_31 ), + .empty( rx_sf_fifo_empty_31 ), + .almost_full( ), + .reset_ptrs( 1'b0 ), + // debug + .active( sync_rx3_active[1] ) + ); + +fcs fcs_3( + .rstn( rstn ), + .clk( pcs_pclk ), + .init( fcs_init[3] ), + .enable( fcs_enable[3] ), + .addr( fcs_addr3 ), + .din( fcs_din3 ), + .dout( fcs_dout3 ) +); + +/* + * uCont i/f FIFO + * FIFO side connects to network switch + * RX: processor writes (data into switch) + * TX: processor reads (data from switch) + */ +half_fifo #(.DPRAM_DEPTH(9)) micro_fifo_0 ( + .rstn( rstn ), + .uc_clk(clk_10), + .fifo_clk(pcs_pclk), + // UC interrupt support + .fifo_we_int ( micro_fifo_int ), + // TX mode + .tx_mode(tx_sw_modeu), + // DPRAM common + .dpram_addr( mem_addr[8:0] ), + .dpram_din( mem_d_i[8:0] ), + .dpram_dout( micro_fifo_do ), + .dpram_we( mem_we ), + .dpram_oe( mem_oe ), + // UC select signals + .dpram_ptrs_sel( dpram_ptrs_sel ), + .dpram_rx_sel( dpram_rx_sel ), + .dpram_tx_sel( dpram_tx_sel ), + // FIFO TX (input) + .fifo_we( tx_sw_fifo_we ), + .fifo_d_in( tx_sw_fifo_du ), + // FIFO RX (output) + .fifo_re( rx_sw_fifo_re_u2 ), + .fifo_d_out( rx_uc_fifo_d_u2 ), + // FIFO flags + .rx_empty( rx_uc_fifo_empty_u2 ), + .tx_full ( tx_uc_block ) + ); + +/* + * Param RAM + */ +dpram param_ram_2( + .rstn(rstn), + .a_clk(clk_10), + .a_clk_e(param_sel[2]), + .a_we(mem_we), + .a_oe(mem_oe), + .a_addr(mem_addr), + .a_din(mem_d_i[8:0]), + .a_dout(param_ram_2_do), + // port B + .b_clk( pcs_pclk), + .b_clk_e(param_phy2_ce), + .b_we(param_phy2_we), + .b_oe( 1'b1 ), + .b_addr( param_phy2_addr ), + .b_din( param_phy2_dout ), + .b_dout( param_phy2_din ) +); + +//defparam param_ram_2.dp16kd_inst.INITVAL_00 = "00000000000000000000000000000000000000000000000000000000000000000022E10069F00800"; + + + +/* +* PCS Notes: +* All _c control signals are asynch in the SERDES/PCS +* All _s control signals are asynch and should be clocked before being used +* TxPLL provides system clock for FPGA logic +* tx_full_clk uses wire name 'txclk' and feeds both txi_clk and rxi_clk, as shown in Figure 9-27 +* For SGMII, tx_pclk is fed back internally to rxi_clk and ebrd_clk +* ebrd_clk: CTC FIFO Read Clock per Channel +* +*/ + +assign ext_sci_int = sci_int[0]; + +/* +PCSCLKDIV pcsclkdiv0 ( + .RST( ~rstn ), + .CLKI( refclko ), + .SEL2( 1'b1 ), // 101 is div by 8 + .SEL1( 1'b0 ), + .SEL0( 1'b1 ), + .CDIV1( ), + .CDIVX( ) +); +*/ + +/* + * PCS block that encapsulates two DCUs and the SCI block + */ + assign pcs_error[0] = sgmii_rx_cv_err[0] | sgmii_rx_cdr_lol[0] | !sgmii_lsm_status[0] | sgmii_rx_los_low[0]; + assign pcs_error[1] = sgmii_rx_cv_err[1] | sgmii_rx_cdr_lol[1] | !sgmii_lsm_status[1] | sgmii_rx_los_low[1]; + assign pcs_error[2] = sgmii_rx_cv_err[2] | sgmii_rx_cdr_lol[2] | sgmii_rx_los_low[2]; + assign pcs_error[3] = sgmii_rx_cv_err[3] | sgmii_rx_cdr_lol[3] | sgmii_rx_los_low[3]; + +pcs pcs_0 ( + + .refclk0_refclkn(refclkp_d0), + .refclk0_refclkp(refclkn_d0), + .refclk0_refclko( refclko ), + + // cross DCU tie offs + .sgmii0_cyawstn( 1'b0 ), + + //DCU0 CH0 to PHY0 + .sgmii0_hdinn(sgmii0_hdinn), + .sgmii0_hdinp(sgmii0_hdinp), + .sgmii0_hdoutn(sgmii0_hdoutn), + .sgmii0_hdoutp(sgmii0_hdoutp), + + // DCU resets + .sgmii0_tx_serdes_rst_c( tx_serdes_rst[0] ), // rset LOL signal in PLL TODO: change this + .sgmii0_rst_dual_c( pcs_rst_dual[0] ), // resets all serdes channels including aux and PCS + .sgmii0_serdes_rst_dual_c( serdes_rst_dual[0] ), // resets serdes dual gated by fpga_reset_enable + + // channel resets + .sgmii0_rx_pcs_rst_c( rx_pcs_rst[0] ), // reset channel PCS logic + .sgmii0_rx_serdes_rst_c( rx_serdes_rst[0] ), // reset digital logic in serdes rx + .sgmii0_tx_pcs_rst_c( tx_pcs_rst[0] ), // reset channel PCS logic + + .sgmii0_rx_pwrup_c(1'b1), // channel power up + .sgmii0_tx_pwrup_c(1'b1), // channel power up + + /* tx_pclk: Transmit Primary Clock. Direct connection to Primary + * clock network. When gearing is not enabled, this output + * equals the transmit full rate clock. When 2:1 gearing + * is enabled, it is a divide-by-2 half-rate clock. + */ + .sgmii0_tx_pclk( pcs_pclk ), // direct connection from primary clock network + .sgmii0_txi_clk( pcs_pclk ), // clocks the TX UI FIFOS (see Figure 27) + + .sgmii0_tx_disp_correct(sgmii_tx_disp_correct[0]), + .sgmii0_tx_k(sgmii_tx_k[0]), + .sgmii0_txdata( tx_data0 ), + .sgmii0_xmit(1'b0), //TODO: Auto Neg state machine + .sgmii0_signal_detect_c(1'b1), + .sgmii0_rx_cv_err( sgmii_rx_cv_err[0] ), // code violation with associated data, PCS will drive 0xEE and K=1 (Table 9-4) + .sgmii0_rx_disp_err( sgmii_rx_disp_err[0] ), + .sgmii0_rx_k( sgmii_rx_k[0] ), + .sgmii0_rxdata( rx_data0 ), + .sgmii0_lsm_status_s( sgmii_lsm_status[0] ), // lane is synced with commas ( 0 means no commas detected ) + .sgmii0_rx_cdr_lol_s( sgmii_rx_cdr_lol[0] ), // CDR Loss of lock + .sgmii0_rx_los_low_s( sgmii_rx_los_low[0] ), // Loss of signal (LO THRESHOLD RANGE) detection + + .sgmii0_ctc_ins_s(), // skip char added by CTC + .sgmii0_ctc_orun_s(), // CTC FIFO over run error + .sgmii0_ctc_urun_s(), // CTC FIFO under run error + .sgmii0_ctc_del_s(), // skip char deleted by CTC + .sgmii0_pll_lol( pll_lol[0] ), + + //DCU0 CH1 to PHY1 + .sgmii1_hdinn( sgmii1_hdinn ), + .sgmii1_hdinp( sgmii1_hdinp ), + .sgmii1_hdoutn( sgmii1_hdoutn ), + .sgmii1_hdoutp( sgmii1_hdoutp ), + + // DCU resets + .sgmii1_rst_dual_c( pcs_rst_dual[0] ), + .sgmii1_serdes_rst_dual_c( serdes_rst_dual[0] ), + .sgmii1_tx_serdes_rst_c( tx_serdes_rst[0] ), + + // Channel resets + .sgmii1_rx_pcs_rst_c( rx_pcs_rst[1] ), + .sgmii1_rx_serdes_rst_c( rx_serdes_rst[1] ), + .sgmii1_tx_pcs_rst_c( tx_pcs_rst[1] ), + + .sgmii1_rx_pwrup_c( 1'b1 ), + .sgmii1_tx_pwrup_c( 1'b1 ), + .sgmii1_serdes_pdb( 1'b1 ), + + .sgmii1_tx_pclk( ), + .sgmii1_txi_clk( pcs_pclk ), + + .sgmii1_rx_cv_err( sgmii_rx_cv_err[1] ), + .sgmii1_rx_disp_err( sgmii_rx_disp_err[1] ), + .sgmii1_rx_k( sgmii_rx_k[1] ), + .sgmii1_rxdata( rx_data1 ), + .sgmii1_tx_disp_correct( sgmii_tx_disp_correct[1] ), + .sgmii1_tx_k( sgmii_tx_k[1] ), + .sgmii1_txdata( tx_data1 ), + .sgmii1_xmit( 1'b0 ), // TODO: Auto Negotiation Bit + + .sgmii1_signal_detect_c( 1'b1 ), + + .sgmii1_ctc_del_s(), + .sgmii1_ctc_ins_s(), + .sgmii1_ctc_orun_s(), + .sgmii1_ctc_urun_s(), + + .sgmii1_lsm_status_s( sgmii_lsm_status[1] ), + .sgmii1_rx_cdr_lol_s( sgmii_rx_cdr_lol[1] ), + .sgmii1_rx_los_low_s( sgmii_rx_los_low[1] ), + + // DCU1 CH0 to Expansion + .sgmii2_hdinn( sgmii2_hdinn ), + .sgmii2_hdinp( sgmii2_hdinp ), + .sgmii2_hdoutn( sgmii2_hdoutn ), + .sgmii2_hdoutp( sgmii2_hdoutp ), + + // DCU Tie Offs + .sgmii2_cyawstn( 1'b0 ), + + // DCU resets + .sgmii2_rst_dual_c( pcs_rst_dual[1] ), + .sgmii2_serdes_rst_dual_c( serdes_rst_dual[1] ), + .sgmii2_tx_serdes_rst_c( tx_serdes_rst[1] ), + + // Channel resets + .sgmii2_rx_pcs_rst_c( rx_pcs_rst[2] ), + .sgmii2_rx_serdes_rst_c( rx_serdes_rst[2] ), + .sgmii2_tx_pcs_rst_c( tx_pcs_rst[2] ), + + .sgmii2_rx_pwrup_c( 1'b1 ), + .sgmii2_tx_pwrup_c( 1'b1 ), + .sgmii2_serdes_pdb( 1'b1 ), + + .sgmii2_tx_pclk( ), + .sgmii2_txi_clk( pcs_pclk ), + + .sgmii2_rx_cv_err( sgmii_rx_cv_err[2] ), + .sgmii2_rx_disp_err( sgmii_rx_disp_err[2] ), + .sgmii2_rx_k( sgmii_rx_k[2] ), + .sgmii2_rxdata( rx_data2 ), + .sgmii2_tx_disp_correct( sgmii_tx_disp_correct[2] ), + .sgmii2_tx_k( sgmii_tx_k[2] ), + .sgmii2_txdata( tx_data2 ), + .sgmii2_xmit( 1'b0 ), + + .sgmii2_signal_detect_c( 1'b1 ), + + .sgmii2_ctc_del_s(), + .sgmii2_ctc_ins_s(), + .sgmii2_ctc_orun_s(), + .sgmii2_ctc_urun_s(), + + .sgmii2_lsm_status_s( sgmii_lsm_status[2] ), + .sgmii2_rx_cdr_lol_s( sgmii_rx_cdr_lol[2] ), + .sgmii2_rx_los_low_s( sgmii_rx_los_low[2] ), + + .sgmii2_pll_lol( pll_lol[1] ), + + // DCU1 CH1 to Expansion + .sgmii3_hdinn( sgmii3_hdinn ), + .sgmii3_hdinp( sgmii3_hdinp ), + .sgmii3_hdoutn( sgmii3_hdoutn ), + .sgmii3_hdoutp( sgmii3_hdoutp ), + + // DCU resets + .sgmii3_rst_dual_c( pcs_rst_dual[1] ), + .sgmii3_serdes_rst_dual_c( serdes_rst_dual[1] ), + .sgmii3_tx_serdes_rst_c( tx_serdes_rst[1] ), + + // Channel resets + .sgmii3_rx_pcs_rst_c( rx_pcs_rst[3] ), + .sgmii3_rx_serdes_rst_c( rx_serdes_rst[3] ), + .sgmii3_tx_pcs_rst_c( tx_pcs_rst[3] ), + + .sgmii3_rx_pwrup_c( 1'b1 ), + .sgmii3_tx_pwrup_c( 1'b1 ), + + .sgmii3_tx_pclk( ), + .sgmii3_txi_clk( pcs_pclk ), + + .sgmii3_rx_cv_err( sgmii_rx_cv_err[3] ), + .sgmii3_rx_disp_err( sgmii_rx_disp_err[3] ), + .sgmii3_rx_k( sgmii_rx_k[3] ), + .sgmii3_rxdata( rx_data3 ), + .sgmii3_tx_disp_correct( sgmii_tx_disp_correct[3] ), +`ifdef SHIELD_SFP_SMA + .sgmii3_tx_k(rx2_k_m1), // MAC 2 RX k + .sgmii3_txdata(rx2_data_m1), // MAC 2 RX data +`else + .sgmii3_tx_k( sgmii_tx_k[3] ), + .sgmii3_txdata( tx_data3 ), +`endif + .sgmii3_xmit( 1'b0 ), // TODO: Auto Negotiation Bit + .sgmii3_signal_detect_c( 1'b1 ), + + .sgmii3_ctc_del_s(), + .sgmii3_ctc_ins_s(), + .sgmii3_ctc_orun_s(), + .sgmii3_ctc_urun_s(), + + .sgmii3_lsm_status_s( sgmii_lsm_status[3] ), + .sgmii3_rx_cdr_lol_s( sgmii_rx_cdr_lol[3] ), + .sgmii3_rx_los_low_s( sgmii_rx_los_low[3] ), + + + // DCU0 SCI + .sgmii0_sci_sel_dual( sci_sel_dual[0] ), + .sgmii0_sci_en_dual( 1'b1 ), + .sgmii0_sci_addr( mem_addr[5:0] ), // SCI Register Address Bits + .sgmii0_sci_rddata( sci_rddata0 ), + .sgmii0_sci_wrdata( mem_d_i[7:0] ), + .sgmii0_sci_rd( ~fb_oen ), + .sgmii0_sci_wrn( fb_rwn ), + + + .sgmii0_sci_sel( sci_sel_ch[0] ), + .sgmii0_sci_en( 1'b1 ), + + .sgmii1_sci_sel( sci_sel_ch[1] ), + .sgmii1_sci_en( 1'b1 ), + + .sgmii0_sci_int( sci_int[1] ), + + // DCU1 SCI + .sgmii2_sci_sel_dual( sci_sel_dual[1] ), + .sgmii2_sci_en_dual( 1'b1 ), + .sgmii2_sci_addr( mem_addr[5:0] ), // SCI Register Address Bits + .sgmii2_sci_rddata( sci_rddata1 ), + .sgmii2_sci_wrdata( mem_d_i[7:0] ), + .sgmii2_sci_rd( ~fb_oen ), + .sgmii2_sci_wrn( fb_rwn ), + + .sgmii2_sci_sel( sci_sel_ch[2] ), + .sgmii2_sci_en( 1'b1 ), + + .sgmii2_sci_int( sci_int[0] ), + + .sgmii3_sci_sel( sci_sel_ch[3] ) + +); + +// Link Timer for AN +link_timer link_timer_0( + .rstn(rstn), + .clk(pcs_pclk), + .pulse_1_6ms(pulse_1_6ms), + .pulse_10ms(pulse_10ms) +); + +mdio_controller #(.ADDR_SZ( MDIO_ROM_ADDR_SZ )) mdio_controller_0 +( + .rstn(rstn), + .clk(clk_10), + .work_start(mdio_cont_work_start), + .work_run(mdio_cont_work_run), + .work_done(mdio_cont_work_done), + .routine_addr( mdio_routine_addr ), + .buffer_full(1'b0), + .addr(rom_a), + .di(rom_d), + .reg_addr(mdio_reg_addr), + .dout(mdio_wd), + .ld(mdio_ld), + .rwn(mdio_rwn), + .done(mdio_done) +); + +`ifdef PHY_MARVELL +mdio_data_mvl #(.ADDR_SZ( MDIO_ROM_ADDR_SZ )) mdio_data_mvl_0( + .ad( rom_a ), + .page( mdio_page_set ), + .reg_addr( mdio_reg_addr_set ), + .data_in_h( mdio_w_data_h_set ), + .data_in_l( mdio_w_data_l_set ), + .d( rom_d ), + .oe( ~mdio_mux_sel[1] ) +); +`endif + +mdio_data_ti #(.ADDR_SZ( MDIO_ROM_ADDR_SZ )) mdio_data_ti_0( + .ad( rom_a ), + .page( mdio_page_set ), + .reg_addr( mdio_reg_addr_set ), + .data_in_h( mdio_w_data_h_set ), + .data_in_l( mdio_w_data_l_set ), + .d( rom_d ), + .oe( 1'b1 ) +); + + +/* MDIO mux and output enables */ +always @(*) begin + case (mdio_mux_sel) + 2'b00: mdi = phy0_mdio; + 2'b01: mdi = phy1_mdio; + 2'b10: mdi = phy2_mdio_i; // compile as 0 if GIGE_SHIELD isn't defined + 2'b11: mdi = 1'b1; + endcase +end + +assign phy0_mdio = (mdo_oe & ~mdio_mux_sel[1] & ~mdio_mux_sel[0]) ? mdo : 1'bz; +assign phy1_mdio = (mdo_oe & ~mdio_mux_sel[1] & mdio_mux_sel[0]) ? mdo : 1'bz; +assign phy2_mdio_oe = (mdo_oe & mdio_mux_sel[1] & ~mdio_mux_sel[0]); +assign phy2_mdio_o = mdo; + +mdio mdio_0( + .rstn(rstn), + .mdc(clk_10), + // MDIO + .mdi(mdi), + .mdo(mdo), + .mdo_oe(mdo_oe), + // mdio controller interface + .rwn(mdio_rwn), + .phy_addr(5'h00), + .reg_addr(mdio_reg_addr), + .di(mdio_wd), + .ld(mdio_ld), + .run( mdio_run ), + .done(mdio_done), // signal controller that mdio xfer is done + // output port to converter + .dout(mdio_rd), + .we( mdio_rd_we ) +); + + +spi spi_0 ( + .rstn(rstn), + .clk(clk_10), + // spi signals + .spi_cs( spi_cs ), + .spi_clk( spi_clk ), + .spi_d_in( spi_mosi), + .spi_d_o( spi_do ), + .spi_d_oe(spi_do_e ), + // internal FPGA memory + .mem_addr( mem_addr ), + .mux_sel ( mem_do_mux_sel ), + .d_i( mem_d_o ), + .d_o( mem_d_i ), + // individual memory selects + .we( mem_we ), + .oe( mem_oe ), + .dpram_tx_sel( dpram_tx_sel ), + .dpram_rx_sel( dpram_rx_sel ), + .dpram_ptrs_sel( dpram_ptrs_sel ), + .param_sel( param_sel ), + .pkt_filter_sel_01( pkt_filter_sel_01 ), + .pkt_filter_sel_02( pkt_filter_sel_02 ), + .pkt_filter_sel_03( pkt_filter_sel_03 ), + .pkt_filter_sel_10( pkt_filter_sel_10 ), + .pkt_filter_sel_12( pkt_filter_sel_12 ), + .pkt_filter_sel_13( pkt_filter_sel_13 ), + .pkt_filter_sel_20( pkt_filter_sel_20 ), + .pkt_filter_sel_21( pkt_filter_sel_21 ), + .pkt_filter_sel_23( pkt_filter_sel_23 ), + .pkt_filter_sel_2u( pkt_filter_sel_2u ), + .pkt_filter_sel_30( pkt_filter_sel_30 ), + .pkt_filter_sel_31( pkt_filter_sel_31 ), + .pkt_filter_sel_32( pkt_filter_sel_32 ), + .pkt_filter_sel_u2( pkt_filter_sel_u2 ), + .interrupts_sel( int_sel ), + .sci_sel_dual( sci_sel_dual ), + .sci_sel_ch( sci_sel_ch ) +); + +assign spi_miso = spi_do_e ? spi_do : 1'bz; + +/* data mux out of internal memories */ +always@(*) +begin + case(mem_do_mux_sel) + 5'b00000: mem_d_o = { 2'b0, sci_rddata1 }; + 5'b00001: mem_d_o = { 2'b0, sci_rddata0 }; + 5'b00010: mem_d_o = { 1'b0, micro_fifo_do }; + 5'b00011: mem_d_o = { 1'b0, micro_fifo_do }; + 5'b00100: mem_d_o = { 1'b0, micro_fifo_do }; + 5'b01000: mem_d_o = param_ram_0_do; + 5'b01001: mem_d_o = param_ram_1_do; + 5'b01010: mem_d_o = param_ram_2_do; + 5'b01011: mem_d_o = param_ram_3_do; + 5'b10000: mem_d_o = { 2'b0, int_do }; + default: mem_d_o = 9'h0; + endcase +end + + +interrupts interrupts_0( + .rstn( rstn ), + .clk( pcs_pclk ), + .uc_clk( clk_10 ), + // uC interface + .sel( int_sel ), + .we( mem_we ), + .addr( mem_addr[0] ), + .d_in( mem_d_i[6:0] ), + .d_out( int_do ), + // interrupt sources + .cont_int( micro_fifo_int ), + .phy_int ( { 2'b0, phy1_intn, phy0_intn }), + .mac_int ( { mac_int[3], mac_int[2], mac_int[1], mac_int[0] } ), + .int_o( ) +); + + +assign i2c_sda = sda_oe ? sda_o : 1'bz; +assign i2c_scl = scl_oe ? scl_o : 1'bz; + +i2c i2c_0( + .rstn( rstn ), + .clk( clk_10 ), + // external I2C I/O + .scl_i( i2c_scl ), + .scl_o( scl_o ), + .scl_oe( scl_oe ), + .sda_i( i2c_sda ), + .sda_o( sda_o ), + .sda_oe( sda_oe ), + // shared memory and controller data output + .mem_do( i2c_d_o ), + // dedicated memory interface + .mem_ad( ), + .mem_we( ), + .mem_ce( ), + .mem_di( 8'haa ), + // dedicated controller write interface + .cont_we( i2c_cont_we ), + .cont_done( i2c_cont_done ), + // Controller->FIFO input interface + .fifo_re( i2c_fifo_re ), + .tx_fifo_empty( cont_fifo_empty ), + .fifo_di( fifo_r_d[6:0] ) +); + + +/* +* ext_sys_fifo delays and enables: +* we need the mdio_we delay since the fifo is clocked twice: high and low data +* +*/ +always@ ( posedge clk_10 or negedge rstn ) + begin + if ( !rstn ) + begin + cont_fifo_re_m1 <= 1'b0; + cont_fifo_re_m2 <= 1'b0; + end + else + begin + cont_fifo_re_m1 <= i2c_fifo_re; + cont_fifo_re_m2 <= cont_fifo_re_m1; + end + end + +// create a single re pulse +assign i_cont_fifo_re = cont_fifo_re_m1 & ~cont_fifo_re_m2; + +assign bin_to_ascii_we = mdio_rd_we | cont_rd_we; +assign bin_to_ascii_d_in = read_fifo_mux_sel ? mdio_rd : cont_rd; + +/* + * Input: MDIO writes + * Output: I2C read FIFO + */ +bin_to_ascii bin_to_ascii_0( + .rstn( rstn ), + .clk( clk_10 ), + .width ( 1'b1 ), + // mdio interface + .we_i ( bin_to_ascii_we ), + .d_in( bin_to_ascii_d_in ), + // mdio controller interface + .run ( bin_to_ascii_run ), + .done (), + .busy( 1'b0 ), + // fifo port + .we_o ( read_fifo_we ), + .d_out( read_fifo_d_i ) +); + +/* + * Input: bin_to_ascii + * Output: I2C read + */ +sync_fifo ext_sys_fifo_0( + .rstn( rstn ), + .clk ( clk_10 ), + // input + .we ( read_fifo_we ), + .d_in ( { 2'b0, read_fifo_d_i } ), + // output + .re ( i_cont_fifo_re ), + .d_out( fifo_r_d ), + .empty( cont_fifo_empty ), + .almost_full( ), + .reset_ptrs( 1'b0 ), + // debug + .active( ) +); + +always @(*) begin + case (mdio_mux_sel) + 2'b00: rx_cdr_lol = sgmii_rx_cdr_lol[0]; + 2'b01: rx_cdr_lol = sgmii_rx_cdr_lol[1]; + 2'b10: rx_cdr_lol = sgmii_rx_cdr_lol[2]; + 2'b11: rx_cdr_lol = 1'b1; + endcase +end + +always @(*) begin + case (mdio_mux_sel) + 2'b00: lsm_status = sgmii_lsm_status[0]; + 2'b01: lsm_status = sgmii_lsm_status[1]; + 2'b10: lsm_status = sgmii_lsm_status[2]; + 2'b11: lsm_status = 1'b1; + endcase +end + +always @(*) begin + case (mdio_mux_sel) + 2'b00: rx_los_low = sgmii_rx_los_low[0]; + 2'b01: rx_los_low = sgmii_rx_los_low[1]; + 2'b10: rx_los_low = sgmii_rx_los_low[2]; + 2'b11: rx_los_low = 1'b1; + endcase +end + +/* Debug and Arduino Expansion */ + +assign led[0] = 1'b1; +assign led[1] = phy_up[0]; +assign led[2] = phy_up[1]; + +`ifdef DEBUG_SPI + assign ard_scl = spi_clk; + assign ard_sda = spi_cs; + assign ard_rxd1 = spi_do_e ? spi_do : 1'bz; + assign ard_txd1 = spi_mosi; +`elsif DEBUG_MDIO + assign ard_scl = phy_mdc; + assign ard_sda = phy0_mdio; + assign ard_rxd1 = 1'bz; + assign ard_txd1 = refclko; +`elsif DEBUG_IC2 + assign ard_scl = i2c_scl; + assign ard_sda = sda_oe ? sda_o : i2c_sda; + assign ard_rxd1 = 1'bz; + assign ard_txd1 = sda_oe; +`else + assign ard_scl = rx_sop[0]; + assign ard_sda = 1'bz; +`endif + +`ifdef ARD_EXP_UART + assign ard_txd2 = uart_txd; + assign uart_rxd = ard_rxd2; + assign ftdi_tdi_rxd = 1'bz; +`else + + // assign uart_rxd = ftdi_tck_txd; +`endif + + assign ftdi_tdi_rxd = 1'bz; + + assign pe1 = pcs_error[2]; // RX data on SFP good + assign pe4 = ~sgmii_tx_k[2]; + assign pe5 = phy1_gpio[1]; + assign pg5 = 1'bz; + assign pe3 = fpga_gpio; + +`ifdef SHIELD_GIGE_SMA + assign pa[0] = phy2_mdc; + assign pa[1] = phy2_mdio_oe ? phy2_mdio_o : 1'bz; + assign phy2_mdio_i = pa[1]; + assign pa[2] = phy2_resetn; +`else + assign phy2_mdio_i = 1'b0; +`endif + +`ifdef SHIELD_SFP_SMA + // SFP UART testing + assign uart_rxd = ph3; + assign ph4 = uart_txd; + + assign sfp_los = pa[1]; + assign pa[2] = sfp_rate_select; + assign sfp_pres_n = pa[3]; + assign pa[4] = sfp_i2c_scl; + assign sfp_tx_fault = pa[5]; + assign pa[6] = sfp_tx_disable; + assign sfp_i2c_sda = pa[7]; + + // SFP LEDS + assign ard_txd3 = !sfp_pres_n; // LED1 + assign ard_rxd3 = !sfp_tx_fault; // LED2 + assign ard_txd2 = !sfp_los; // LED3 + assign ard_rxd2 = !pcs_error[2]; // LED4 + assign ard_txd1 = phy_up[0]; // LED5 + assign ard_rxd1 = !mac_tx_active[0];// LED6 +`endif + + assign fpga_int = pcs_error[2] | pcs_error[3]; + +`ifdef DARSENA_V02 + assign fpga_jtag_e =1'b1; +`endif + +endmodule |
