diff options
Diffstat (limited to 'manufacturer/lattice/ecp5um/privateisland.ldf')
| -rw-r--r-- | manufacturer/lattice/ecp5um/privateisland.ldf | 139 |
1 files changed, 139 insertions, 0 deletions
diff --git a/manufacturer/lattice/ecp5um/privateisland.ldf b/manufacturer/lattice/ecp5um/privateisland.ldf new file mode 100644 index 0000000..56f2c3c --- /dev/null +++ b/manufacturer/lattice/ecp5um/privateisland.ldf @@ -0,0 +1,139 @@ +<?xml version="1.0" encoding="UTF-8"?> +<BaliProject version="3.2" title="privateisland" device="LFE5UM-45F-8BG381C" default_implementation="impl1"> + <Options> + <Option name="HDL type" value="Verilog"/> + </Options> + <Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="darsena"> + <Options> + <Option name="HDL type" value="Verilog"/> + <Option name="def_top" value="top"/> + <Option name="include path" value="../../../source"/> + <Option name="lib" value="work"/> + <Option name="top" value="top"/> + </Options> + <Source name="source/top.v" type="Verilog" type_short="Verilog"> + <Options top_module="top"/> + </Source> + <Source name="../../../source/bin_to_ascii.v" type="Verilog" type_short="Verilog"> + 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type="Verilog" type_short="Verilog"> + <Options/> + </Source> + <Source name="../../../source/pkt_filter.v" type="Verilog" type_short="Verilog"> + <Options/> + </Source> + <Source name="../../../source/sgmii_params.v" type="Verilog" type_short="Verilog" excluded="TRUE"> + <Options/> + </Source> + <Source name="../../../source/spi.v" type="Verilog" type_short="Verilog"> + <Options/> + </Source> + <Source name="../../../source/switch.v" type="Verilog" type_short="Verilog"> + <Options/> + </Source> + <Source name="../../../source/sync_fifo.v" type="Verilog" type_short="Verilog"> + <Options/> + </Source> + <Source name="clarity/pcs/pcs.sbx" type="sbx" type_short="SBX"> + <Options/> + </Source> + <Source name="clarity/pcs/pcs.v" type="Verilog" type_short="Verilog" excluded="TRUE"> + <Options/> + </Source> + <Source name="clarity/pcs/refclk0/refclk0.v" type="Verilog" type_short="Verilog" excluded="TRUE"> + <Options/> + </Source> + <Source name="clarity/pcs/sgmii0/sgmii0.v" type="Verilog" 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type_short="Reveal"> + <Options/> + </Source> + <Source name="programming/local_background.xcf" type="Programming Project File" type_short="Programming" excluded="TRUE"> + <Options/> + </Source> + <Source name="programming/local_jtag.xcf" type="Programming Project File" type_short="Programming"> + <Options/> + </Source> + <Source name="programming/read_device_status.xcf" type="Programming Project File" type_short="Programming" excluded="TRUE"> + <Options/> + </Source> + </Implementation> + <Strategy name="darsena" file="boards/darsena/darsena.sty"/> +</BaliProject> |
