diff options
Diffstat (limited to 'clarity/pcs/sgmii3')
| -rw-r--r-- | clarity/pcs/sgmii3/sgmii3.fdc | 3 | ||||
| -rw-r--r-- | clarity/pcs/sgmii3/sgmii3.lpc | 97 | ||||
| -rw-r--r-- | clarity/pcs/sgmii3/sgmii3.v | 422 |
3 files changed, 0 insertions, 522 deletions
diff --git a/clarity/pcs/sgmii3/sgmii3.fdc b/clarity/pcs/sgmii3/sgmii3.fdc deleted file mode 100644 index 5424a21..0000000 --- a/clarity/pcs/sgmii3/sgmii3.fdc +++ /dev/null @@ -1,3 +0,0 @@ -###==== Start Generation - -define_attribute {i:Lane0} {loc} {DCU1_CH1} diff --git a/clarity/pcs/sgmii3/sgmii3.lpc b/clarity/pcs/sgmii3/sgmii3.lpc deleted file mode 100644 index fc45681..0000000 --- a/clarity/pcs/sgmii3/sgmii3.lpc +++ /dev/null @@ -1,97 +0,0 @@ -[Device] -Family=ecp5um -OperatingCondition=COM -Package=CABGA381 -PartName=LFE5UM-45F-8BG381C -PartType=LFE5UM-45F -SpeedGrade=8 -Status=P -[IP] -CoreName=PCS -CoreRevision=8.2 -CoreStatus=Demo -CoreType=LPM -Date=03/15/2019 -ModuleName=sgmii3 -ParameterFileVersion=1.0 -SourceFormat=verilog -Time=18:46:48 -VendorName=Lattice Semiconductor Corporation -[Parameters] -;ACHARA=0 00H -;ACHARB=0 00H -;ACHARM=0 00H -;RXMCAENABLE=Disabled -CDRLOLACTION=Full Recalibration -CDRLOLRANGE=0 -CDR_MAX_RATE=1.25 -CDR_MULT=25X -CDR_REF_RATE=50.0000 -CH_MODE=Rx and Tx -Destination=Synplicity -EDIF=1 -Expression=BusA(0 to 7) -IO=0 -IO_TYPE=GbE -LEQ=0 -LOOPBACK=Disabled -LOSPORT=Enabled -NUM_CHS=1 -Order=Big Endian [MSB:LSB] -PPORT_RX_RDY=Disabled -PPORT_TX_RDY=Disabled -PROTOCOL=GbE -PWAIT_RX_RDY=3000 -PWAIT_TX_RDY=3000 -RCSRC=Disabled -REFCLK_RATE=50.0000 -RSTSEQSEL=Disabled -RX8B10B=Enabled -RXCOMMAA=1010000011 -RXCOMMAB=0101111100 -RXCOMMAM=1111111111 -RXCOUPLING=AC -RXCTC=Enabled -RXCTCBYTEN=0 00H -RXCTCBYTEN1=0 00H -RXCTCBYTEN2=1 BCH -RXCTCBYTEN3=0 50H -RXCTCMATCHPATTERN=M2-S2 -RXDIFFTERM=50 ohms -RXFIFO_ENABLE=Enabled -RXINVPOL=Non-invert -RXLDR=Off -RXLOSTHRESHOLD=4 -RXLSM=Enabled -RXSC=K28P5 -RXWA=Barrel Shift -RX_DATA_WIDTH=8/10-Bit -RX_FICLK_RATE=125.0000 -RX_LINE_RATE=1.2500 -RX_RATE_DIV=Full Rate -SCIPORT=Enabled -SOFTLOL=Disabled -TX8B10B=Enabled -TXAMPLITUDE=400 -TXDEPOST=Disabled -TXDEPRE=Disabled -TXDIFFTERM=50 ohms -TXFIFO_ENABLE=Enabled -TXINVPOL=Non-invert -TXLDR=Off -TXPLLLOLTHRESHOLD=0 -TXPLLMULT=25X -TX_DATA_WIDTH=8/10-Bit -TX_FICLK_RATE=125.0000 -TX_LINE_RATE=1.2500 -TX_MAX_RATE=1.25 -TX_RATE_DIV=Full Rate -VHDL=0 -Verilog=1 -[FilesGenerated] -sgmii3.pp=pp -sgmii3.sym=sym -sgmii3.tft=tft -sgmii3.txt=pcs_module -[SYSTEMPNR] -LN0=DCU1_CH1 diff --git a/clarity/pcs/sgmii3/sgmii3.v b/clarity/pcs/sgmii3/sgmii3.v deleted file mode 100644 index 4f1eefe..0000000 --- a/clarity/pcs/sgmii3/sgmii3.v +++ /dev/null @@ -1,422 +0,0 @@ -// Verilog netlist produced by program ASBGen: Ports rev. 2.30, Attr. rev. 2.70 -// Netlist written on Fri Mar 15 18:48:22 2019 -// -// Verilog Description of module sgmii3 -// - -`timescale 1ns/1ps -module sgmii3 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk, - tx_pclk, txi_clk, txdata, tx_k, xmit, tx_disp_correct, - rxdata, rx_k, rx_disp_err, rx_cv_err, signal_detect_c, - rx_los_low_s, lsm_status_s, ctc_urun_s, ctc_orun_s, rx_cdr_lol_s, - ctc_ins_s, ctc_del_s, tx_pcs_rst_c, rx_pcs_rst_c, rx_serdes_rst_c, - tx_pwrup_c, rx_pwrup_c, sci_wrdata, sci_addr, sci_rddata, - sci_en_dual, sci_sel_dual, sci_en, sci_sel, sci_rd, sci_wrn, - sci_int, cyawstn, rst_dual_c, serdes_rst_dual_c, serdes_pdb, - tx_serdes_rst_c, pll_refclki); - output hdoutp; - output hdoutn; - input hdinp; - input hdinn; - input rxrefclk; - output tx_pclk; - input txi_clk; - input [7:0]txdata; - input [0:0]tx_k; - input [0:0]xmit; - input [0:0]tx_disp_correct; - output [7:0]rxdata; - output [0:0]rx_k; - output [0:0]rx_disp_err; - output [0:0]rx_cv_err; - input signal_detect_c; - output rx_los_low_s; - output lsm_status_s; - output ctc_urun_s; - output ctc_orun_s; - output rx_cdr_lol_s; - output ctc_ins_s; - output ctc_del_s; - input tx_pcs_rst_c; - input rx_pcs_rst_c; - input rx_serdes_rst_c; - input tx_pwrup_c; - input rx_pwrup_c; - input [7:0]sci_wrdata; - input [5:0]sci_addr; - output [7:0]sci_rddata; - input sci_en_dual; - input sci_sel_dual; - input sci_en; - input sci_sel; - input sci_rd; - input sci_wrn; - output sci_int; - input cyawstn; - input rst_dual_c; - input serdes_rst_dual_c; - input serdes_pdb; - input tx_serdes_rst_c; - input pll_refclki; - - - wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, - n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, - n22, n23, n24, n25, n26, n27, n28, n29, n30, n31, - n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, - n42, n43, n46, n47, n48, n49, n50, n51, n52, n53, - n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, - n64, n65, n66, n67, n68, n69, n70, n71, n72, n73, - n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, - n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, - n94, n95, n96, n97, n98, n99, n100, n101, _Z; - - DCUA DCU1_inst (.CH0_HDINP(1'b0), .CH1_HDINP(hdinp), .CH0_HDINN(1'b0), - .CH1_HDINN(hdinn), .D_TXBIT_CLKP_FROM_ND(1'b0), .D_TXBIT_CLKN_FROM_ND(1'b0), - .D_SYNC_ND(1'b0), .D_TXPLL_LOL_FROM_ND(1'b0), .CH0_RX_REFCLK(1'b0), - .CH1_RX_REFCLK(rxrefclk), .CH0_FF_RXI_CLK(1'b1), .CH1_FF_RXI_CLK(tx_pclk), - .CH0_FF_TXI_CLK(1'b1), .CH1_FF_TXI_CLK(txi_clk), .CH0_FF_EBRD_CLK(1'b1), - .CH1_FF_EBRD_CLK(tx_pclk), .CH0_FF_TX_D_0(1'b0), .CH1_FF_TX_D_0(txdata[0]), - .CH0_FF_TX_D_1(1'b0), .CH1_FF_TX_D_1(txdata[1]), .CH0_FF_TX_D_2(1'b0), - .CH1_FF_TX_D_2(txdata[2]), .CH0_FF_TX_D_3(1'b0), .CH1_FF_TX_D_3(txdata[3]), - .CH0_FF_TX_D_4(1'b0), .CH1_FF_TX_D_4(txdata[4]), .CH0_FF_TX_D_5(1'b0), - .CH1_FF_TX_D_5(txdata[5]), .CH0_FF_TX_D_6(1'b0), .CH1_FF_TX_D_6(txdata[6]), - .CH0_FF_TX_D_7(1'b0), .CH1_FF_TX_D_7(txdata[7]), .CH0_FF_TX_D_8(1'b0), - .CH1_FF_TX_D_8(tx_k[0]), .CH0_FF_TX_D_9(1'b0), .CH1_FF_TX_D_9(1'b0), - .CH0_FF_TX_D_10(1'b0), .CH1_FF_TX_D_10(xmit[0]), .CH0_FF_TX_D_11(1'b0), - .CH1_FF_TX_D_11(tx_disp_correct[0]), .CH0_FF_TX_D_12(1'b0), .CH1_FF_TX_D_12(1'b0), - .CH0_FF_TX_D_13(1'b0), .CH1_FF_TX_D_13(1'b0), .CH0_FF_TX_D_14(1'b0), - .CH1_FF_TX_D_14(1'b0), .CH0_FF_TX_D_15(1'b0), .CH1_FF_TX_D_15(1'b0), - .CH0_FF_TX_D_16(1'b0), .CH1_FF_TX_D_16(1'b0), .CH0_FF_TX_D_17(1'b0), - .CH1_FF_TX_D_17(1'b0), .CH0_FF_TX_D_18(1'b0), .CH1_FF_TX_D_18(1'b0), - .CH0_FF_TX_D_19(1'b0), .CH1_FF_TX_D_19(1'b0), .CH0_FF_TX_D_20(1'b0), - .CH1_FF_TX_D_20(1'b0), .CH0_FF_TX_D_21(1'b0), .CH1_FF_TX_D_21(1'b0), - .CH0_FF_TX_D_22(1'b0), .CH1_FF_TX_D_22(1'b0), .CH0_FF_TX_D_23(1'b0), - .CH1_FF_TX_D_23(1'b0), .CH0_FFC_EI_EN(1'b0), .CH1_FFC_EI_EN(1'b0), - .CH0_FFC_PCIE_DET_EN(1'b0), .CH1_FFC_PCIE_DET_EN(1'b0), .CH0_FFC_PCIE_CT(1'b0), - .CH1_FFC_PCIE_CT(1'b0), .CH0_FFC_SB_INV_RX(1'b0), .CH1_FFC_SB_INV_RX(1'b0), - .CH0_FFC_ENABLE_CGALIGN(1'b0), .CH1_FFC_ENABLE_CGALIGN(1'b0), .CH0_FFC_SIGNAL_DETECT(1'b0), - .CH1_FFC_SIGNAL_DETECT(signal_detect_c), .CH0_FFC_FB_LOOPBACK(1'b0), - .CH1_FFC_FB_LOOPBACK(1'b0), .CH0_FFC_SB_PFIFO_LP(1'b0), .CH1_FFC_SB_PFIFO_LP(1'b0), - .CH0_FFC_PFIFO_CLR(1'b0), .CH1_FFC_PFIFO_CLR(1'b0), .CH0_FFC_RATE_MODE_RX(1'b0), - .CH1_FFC_RATE_MODE_RX(1'b0), .CH0_FFC_RATE_MODE_TX(1'b0), .CH1_FFC_RATE_MODE_TX(1'b0), - .CH0_FFC_DIV11_MODE_RX(1'b0), .CH1_FFC_DIV11_MODE_RX(1'b0), .CH0_FFC_DIV11_MODE_TX(1'b0), - .CH1_FFC_DIV11_MODE_TX(1'b0), .CH0_FFC_RX_GEAR_MODE(1'b0), .CH1_FFC_RX_GEAR_MODE(1'b0), - .CH0_FFC_TX_GEAR_MODE(1'b0), .CH1_FFC_TX_GEAR_MODE(1'b0), .CH0_FFC_LDR_CORE2TX_EN(1'b0), - .CH1_FFC_LDR_CORE2TX_EN(1'b0), .CH0_FFC_LANE_TX_RST(1'b0), .CH1_FFC_LANE_TX_RST(tx_pcs_rst_c), - .CH0_FFC_LANE_RX_RST(1'b0), .CH1_FFC_LANE_RX_RST(rx_pcs_rst_c), - .CH0_FFC_RRST(1'b0), .CH1_FFC_RRST(rx_serdes_rst_c), .CH0_FFC_TXPWDNB(1'b0), - .CH1_FFC_TXPWDNB(tx_pwrup_c), .CH0_FFC_RXPWDNB(1'b0), .CH1_FFC_RXPWDNB(rx_pwrup_c), - .CH0_LDR_CORE2TX(1'b0), .CH1_LDR_CORE2TX(1'b0), .D_SCIWDATA0(sci_wrdata[0]), - .D_SCIWDATA1(sci_wrdata[1]), .D_SCIWDATA2(sci_wrdata[2]), .D_SCIWDATA3(sci_wrdata[3]), - .D_SCIWDATA4(sci_wrdata[4]), .D_SCIWDATA5(sci_wrdata[5]), .D_SCIWDATA6(sci_wrdata[6]), - .D_SCIWDATA7(sci_wrdata[7]), .D_SCIADDR0(sci_addr[0]), .D_SCIADDR1(sci_addr[1]), - .D_SCIADDR2(sci_addr[2]), .D_SCIADDR3(sci_addr[3]), .D_SCIADDR4(sci_addr[4]), - .D_SCIADDR5(sci_addr[5]), .D_SCIENAUX(sci_en_dual), .D_SCISELAUX(sci_sel_dual), - .CH0_SCIEN(1'b0), .CH1_SCIEN(sci_en), .CH0_SCISEL(1'b0), .CH1_SCISEL(sci_sel), - .D_SCIRD(sci_rd), .D_SCIWSTN(sci_wrn), .D_CYAWSTN(cyawstn), .D_FFC_SYNC_TOGGLE(1'b0), - .D_FFC_DUAL_RST(rst_dual_c), .D_FFC_MACRO_RST(serdes_rst_dual_c), - .D_FFC_MACROPDB(serdes_pdb), .D_FFC_TRST(tx_serdes_rst_c), .CH0_FFC_CDR_EN_BITSLIP(1'b0), - .CH1_FFC_CDR_EN_BITSLIP(1'b0), .D_SCAN_ENABLE(1'b0), .D_SCAN_IN_0(1'b0), - .D_SCAN_IN_1(1'b0), .D_SCAN_IN_2(1'b0), .D_SCAN_IN_3(1'b0), .D_SCAN_IN_4(1'b0), - .D_SCAN_IN_5(1'b0), .D_SCAN_IN_6(1'b0), .D_SCAN_IN_7(1'b0), .D_SCAN_MODE(1'b0), - .D_SCAN_RESET(1'b0), .D_CIN0(1'b0), .D_CIN1(1'b0), .D_CIN2(1'b0), - .D_CIN3(1'b0), .D_CIN4(1'b0), .D_CIN5(1'b0), .D_CIN6(1'b0), - .D_CIN7(1'b0), .D_CIN8(1'b0), .D_CIN9(1'b0), .D_CIN10(1'b0), - .D_CIN11(1'b0), .CH0_HDOUTP(n47), .CH1_HDOUTP(hdoutp), .CH0_HDOUTN(n48), - .CH1_HDOUTN(hdoutn), .D_TXBIT_CLKP_TO_ND(n1), .D_TXBIT_CLKN_TO_ND(n2), - .D_SYNC_PULSE2ND(n3), .D_TXPLL_LOL_TO_ND(n4), .CH0_FF_RX_F_CLK(n49), - .CH1_FF_RX_F_CLK(n5), .CH0_FF_RX_H_CLK(n50), .CH1_FF_RX_H_CLK(n6), - .CH0_FF_TX_F_CLK(n51), .CH1_FF_TX_F_CLK(n7), .CH0_FF_TX_H_CLK(n52), - .CH1_FF_TX_H_CLK(n8), .CH0_FF_RX_PCLK(n53), .CH1_FF_RX_PCLK(n9), - .CH0_FF_TX_PCLK(n54), .CH1_FF_TX_PCLK(tx_pclk), .CH0_FF_RX_D_0(n55), - .CH1_FF_RX_D_0(rxdata[0]), .CH0_FF_RX_D_1(n56), .CH1_FF_RX_D_1(rxdata[1]), - .CH0_FF_RX_D_2(n57), .CH1_FF_RX_D_2(rxdata[2]), .CH0_FF_RX_D_3(n58), - .CH1_FF_RX_D_3(rxdata[3]), .CH0_FF_RX_D_4(n59), .CH1_FF_RX_D_4(rxdata[4]), - .CH0_FF_RX_D_5(n60), .CH1_FF_RX_D_5(rxdata[5]), .CH0_FF_RX_D_6(n61), - .CH1_FF_RX_D_6(rxdata[6]), .CH0_FF_RX_D_7(n62), .CH1_FF_RX_D_7(rxdata[7]), - .CH0_FF_RX_D_8(n63), .CH1_FF_RX_D_8(rx_k[0]), .CH0_FF_RX_D_9(n64), - .CH1_FF_RX_D_9(rx_disp_err[0]), .CH0_FF_RX_D_10(n65), .CH1_FF_RX_D_10(rx_cv_err[0]), - .CH0_FF_RX_D_11(n66), .CH1_FF_RX_D_11(n10), .CH0_FF_RX_D_12(n67), - .CH1_FF_RX_D_12(n68), .CH0_FF_RX_D_13(n69), .CH1_FF_RX_D_13(n70), - .CH0_FF_RX_D_14(n71), .CH1_FF_RX_D_14(n72), .CH0_FF_RX_D_15(n73), - .CH1_FF_RX_D_15(n74), .CH0_FF_RX_D_16(n75), .CH1_FF_RX_D_16(n76), - .CH0_FF_RX_D_17(n77), .CH1_FF_RX_D_17(n78), .CH0_FF_RX_D_18(n79), - .CH1_FF_RX_D_18(n80), .CH0_FF_RX_D_19(n81), .CH1_FF_RX_D_19(n82), - .CH0_FF_RX_D_20(n83), .CH1_FF_RX_D_20(n84), .CH0_FF_RX_D_21(n85), - .CH1_FF_RX_D_21(n86), .CH0_FF_RX_D_22(n87), .CH1_FF_RX_D_22(n88), - .CH0_FF_RX_D_23(n89), .CH1_FF_RX_D_23(n11), .CH0_FFS_PCIE_DONE(n90), - .CH1_FFS_PCIE_DONE(n12), .CH0_FFS_PCIE_CON(n91), .CH1_FFS_PCIE_CON(n13), - .CH0_FFS_RLOS(n92), .CH1_FFS_RLOS(rx_los_low_s), .CH0_FFS_LS_SYNC_STATUS(n93), - .CH1_FFS_LS_SYNC_STATUS(lsm_status_s), .CH0_FFS_CC_UNDERRUN(n94), - .CH1_FFS_CC_UNDERRUN(ctc_urun_s), .CH0_FFS_CC_OVERRUN(n95), .CH1_FFS_CC_OVERRUN(ctc_orun_s), - .CH0_FFS_RXFBFIFO_ERROR(n96), .CH1_FFS_RXFBFIFO_ERROR(n14), .CH0_FFS_TXFBFIFO_ERROR(n97), - .CH1_FFS_TXFBFIFO_ERROR(n15), .CH0_FFS_RLOL(n98), .CH1_FFS_RLOL(rx_cdr_lol_s), - .CH0_FFS_SKP_ADDED(n99), .CH1_FFS_SKP_ADDED(ctc_ins_s), .CH0_FFS_SKP_DELETED(n100), - .CH1_FFS_SKP_DELETED(ctc_del_s), .CH0_LDR_RX2CORE(n101), .CH1_LDR_RX2CORE(_Z), - .D_SCIRDATA0(sci_rddata[0]), .D_SCIRDATA1(sci_rddata[1]), .D_SCIRDATA2(sci_rddata[2]), - .D_SCIRDATA3(sci_rddata[3]), .D_SCIRDATA4(sci_rddata[4]), .D_SCIRDATA5(sci_rddata[5]), - .D_SCIRDATA6(sci_rddata[6]), .D_SCIRDATA7(sci_rddata[7]), .D_SCIINT(sci_int), - .D_SCAN_OUT_0(n16), .D_SCAN_OUT_1(n17), .D_SCAN_OUT_2(n18), .D_SCAN_OUT_3(n19), - .D_SCAN_OUT_4(n20), .D_SCAN_OUT_5(n21), .D_SCAN_OUT_6(n22), .D_SCAN_OUT_7(n23), - .D_COUT0(n24), .D_COUT1(n25), .D_COUT2(n26), .D_COUT3(n27), - .D_COUT4(n28), .D_COUT5(n29), .D_COUT6(n30), .D_COUT7(n31), - .D_COUT8(n32), .D_COUT9(n33), .D_COUT10(n34), .D_COUT11(n35), - .D_COUT12(n36), .D_COUT13(n37), .D_COUT14(n38), .D_COUT15(n39), - .D_COUT16(n40), .D_COUT17(n41), .D_COUT18(n42), .D_COUT19(n43), - .D_REFCLKI(pll_refclki), .D_FFS_PLOL(n46)) /* synthesis LOC=DCU1 CHAN=CH1 */ ; - defparam DCU1_inst.D_MACROPDB = "0b1"; - defparam DCU1_inst.D_IB_PWDNB = "0b1"; - defparam DCU1_inst.D_XGE_MODE = "0b0"; - defparam DCU1_inst.D_LOW_MARK = "0d4"; - defparam DCU1_inst.D_HIGH_MARK = "0d12"; - defparam DCU1_inst.D_BUS8BIT_SEL = "0b0"; - defparam DCU1_inst.D_CDR_LOL_SET = "0b00"; - defparam DCU1_inst.D_TXPLL_PWDNB = "0b1"; - defparam DCU1_inst.D_BITCLK_LOCAL_EN = "0b1"; - defparam DCU1_inst.D_BITCLK_ND_EN = "0b0"; - defparam DCU1_inst.D_BITCLK_FROM_ND_EN = "0b0"; - defparam DCU1_inst.D_SYNC_LOCAL_EN = "0b1"; - defparam DCU1_inst.D_SYNC_ND_EN = "0b0"; - defparam DCU1_inst.CH1_UC_MODE = "0b0"; - defparam DCU1_inst.CH1_PCIE_MODE = "0b0"; - defparam DCU1_inst.CH1_RIO_MODE = "0b0"; - defparam DCU1_inst.CH1_WA_MODE = "0b0"; - defparam DCU1_inst.CH1_INVERT_RX = "0b0"; - defparam DCU1_inst.CH1_INVERT_TX = "0b0"; - defparam DCU1_inst.CH1_PRBS_SELECTION = "0b0"; - defparam DCU1_inst.CH1_GE_AN_ENABLE = "0b0"; - defparam DCU1_inst.CH1_PRBS_LOCK = "0b0"; - defparam DCU1_inst.CH1_PRBS_ENABLE = "0b0"; - defparam DCU1_inst.CH1_ENABLE_CG_ALIGN = "0b1"; - defparam DCU1_inst.CH1_TX_GEAR_MODE = "0b0"; - defparam DCU1_inst.CH1_RX_GEAR_MODE = "0b0"; - defparam DCU1_inst.CH1_PCS_DET_TIME_SEL = "0b00"; - defparam DCU1_inst.CH1_PCIE_EI_EN = "0b0"; - defparam DCU1_inst.CH1_TX_GEAR_BYPASS = "0b0"; - defparam DCU1_inst.CH1_ENC_BYPASS = "0b0"; - defparam DCU1_inst.CH1_SB_BYPASS = "0b0"; - defparam DCU1_inst.CH1_RX_SB_BYPASS = "0b0"; - defparam DCU1_inst.CH1_WA_BYPASS = "0b0"; - defparam DCU1_inst.CH1_DEC_BYPASS = "0b0"; - defparam DCU1_inst.CH1_CTC_BYPASS = "0b0"; - defparam DCU1_inst.CH1_RX_GEAR_BYPASS = "0b0"; - defparam DCU1_inst.CH1_LSM_DISABLE = "0b0"; - defparam DCU1_inst.CH1_MATCH_2_ENABLE = "0b1"; - defparam DCU1_inst.CH1_MATCH_4_ENABLE = "0b0"; - defparam DCU1_inst.CH1_MIN_IPG_CNT = "0b11"; - defparam DCU1_inst.CH1_CC_MATCH_1 = "0x000"; - defparam DCU1_inst.CH1_CC_MATCH_2 = "0x000"; - defparam DCU1_inst.CH1_CC_MATCH_3 = "0x1BC"; - defparam DCU1_inst.CH1_CC_MATCH_4 = "0x050"; - defparam DCU1_inst.CH1_UDF_COMMA_MASK = "0x3ff"; - defparam DCU1_inst.CH1_UDF_COMMA_A = "0x283"; - defparam DCU1_inst.CH1_UDF_COMMA_B = "0x17C"; - defparam DCU1_inst.CH1_RX_DCO_CK_DIV = "0b010"; - defparam DCU1_inst.CH1_RCV_DCC_EN = "0b0"; - defparam DCU1_inst.CH1_TPWDNB = "0b1"; - defparam DCU1_inst.CH1_RATE_MODE_TX = "0b0"; - defparam DCU1_inst.CH1_RTERM_TX = "0d19"; - defparam DCU1_inst.CH1_TX_CM_SEL = "0b00"; - defparam DCU1_inst.CH1_TDRV_PRE_EN = "0b0"; - defparam DCU1_inst.CH1_TDRV_SLICE0_SEL = "0b00"; - defparam DCU1_inst.CH1_TDRV_SLICE1_SEL = "0b00"; - defparam DCU1_inst.CH1_TDRV_SLICE2_SEL = "0b01"; - defparam DCU1_inst.CH1_TDRV_SLICE3_SEL = "0b01"; - defparam DCU1_inst.CH1_TDRV_SLICE4_SEL = "0b00"; - defparam DCU1_inst.CH1_TDRV_SLICE5_SEL = "0b00"; - defparam DCU1_inst.CH1_TDRV_SLICE0_CUR = "0b000"; - defparam DCU1_inst.CH1_TDRV_SLICE1_CUR = "0b000"; - defparam DCU1_inst.CH1_TDRV_SLICE2_CUR = "0b11"; - defparam DCU1_inst.CH1_TDRV_SLICE3_CUR = "0b00"; - defparam DCU1_inst.CH1_TDRV_SLICE4_CUR = "0b00"; - defparam DCU1_inst.CH1_TDRV_SLICE5_CUR = "0b00"; - defparam DCU1_inst.CH1_TDRV_DAT_SEL = "0b00"; - defparam DCU1_inst.CH1_TX_DIV11_SEL = "0b0"; - defparam DCU1_inst.CH1_RPWDNB = "0b1"; - defparam DCU1_inst.CH1_RATE_MODE_RX = "0b0"; - defparam DCU1_inst.CH1_RX_DIV11_SEL = "0b0"; - defparam DCU1_inst.CH1_SEL_SD_RX_CLK = "0b0"; - defparam DCU1_inst.CH1_FF_RX_H_CLK_EN = "0b0"; - defparam DCU1_inst.CH1_FF_RX_F_CLK_DIS = "0b0"; - defparam DCU1_inst.CH1_FF_TX_H_CLK_EN = "0b0"; - defparam DCU1_inst.CH1_FF_TX_F_CLK_DIS = "0b0"; - defparam DCU1_inst.CH1_TDRV_POST_EN = "0b0"; - defparam DCU1_inst.CH1_TX_POST_SIGN = "0b0"; - defparam DCU1_inst.CH1_TX_PRE_SIGN = "0b0"; - defparam DCU1_inst.CH1_REQ_LVL_SET = "0b00"; - defparam DCU1_inst.CH1_REQ_EN = "0b1"; - defparam DCU1_inst.CH1_RTERM_RX = "0d22"; - defparam DCU1_inst.CH1_RXTERM_CM = "0b11"; - defparam DCU1_inst.CH1_PDEN_SEL = "0b1"; - defparam DCU1_inst.CH1_RXIN_CM = "0b11"; - defparam DCU1_inst.CH1_LEQ_OFFSET_SEL = "0b0"; - defparam DCU1_inst.CH1_LEQ_OFFSET_TRIM = "0b000"; - defparam DCU1_inst.CH1_RLOS_SEL = "0b1"; - defparam DCU1_inst.CH1_RX_LOS_LVL = "0b100"; - defparam DCU1_inst.CH1_RX_LOS_CEQ = "0b11"; - defparam DCU1_inst.CH1_RX_LOS_HYST_EN = "0b0"; - defparam DCU1_inst.CH1_RX_LOS_EN = "0b1"; - defparam DCU1_inst.CH1_LDR_RX2CORE_SEL = "0b0"; - defparam DCU1_inst.CH1_LDR_CORE2TX_SEL = "0b0"; - defparam DCU1_inst.D_TX_MAX_RATE = "1.25"; - defparam DCU1_inst.CH1_CDR_MAX_RATE = "1.25"; - defparam DCU1_inst.CH1_TXAMPLITUDE = "0d400"; - defparam DCU1_inst.CH1_TXDEPRE = "DISABLED"; - defparam DCU1_inst.CH1_TXDEPOST = "DISABLED"; - defparam DCU1_inst.CH1_PROTOCOL = "GBE"; - defparam DCU1_inst.D_ISETLOS = "0d0"; - defparam DCU1_inst.D_SETIRPOLY_AUX = "0b00"; - defparam DCU1_inst.D_SETICONST_AUX = "0b00"; - defparam DCU1_inst.D_SETIRPOLY_CH = "0b00"; - defparam DCU1_inst.D_SETICONST_CH = "0b00"; - defparam DCU1_inst.D_REQ_ISET = "0b000"; - defparam DCU1_inst.D_PD_ISET = "0b00"; - defparam DCU1_inst.D_DCO_CALIB_TIME_SEL = "0b00"; - defparam DCU1_inst.CH1_CDR_CNT4SEL = "0b00"; - defparam DCU1_inst.CH1_CDR_CNT8SEL = "0b00"; - defparam DCU1_inst.CH1_DCOATDCFG = "0b00"; - defparam DCU1_inst.CH1_DCOATDDLY = "0b00"; - defparam DCU1_inst.CH1_DCOBYPSATD = "0b1"; - defparam DCU1_inst.CH1_DCOCALDIV = "0b001"; - defparam DCU1_inst.CH1_DCOCTLGI = "0b010"; - defparam DCU1_inst.CH1_DCODISBDAVOID = "0b0"; - defparam DCU1_inst.CH1_DCOFLTDAC = "0b01"; - defparam DCU1_inst.CH1_DCOFTNRG = "0b110"; - defparam DCU1_inst.CH1_DCOIOSTUNE = "0b000"; - defparam DCU1_inst.CH1_DCOITUNE = "0b00"; - defparam DCU1_inst.CH1_DCOITUNE4LSB = "0b111"; - defparam DCU1_inst.CH1_DCOIUPDNX2 = "0b1"; - defparam DCU1_inst.CH1_DCONUOFLSB = "0b101"; - defparam DCU1_inst.CH1_DCOSCALEI = "0b00"; - defparam DCU1_inst.CH1_DCOSTARTVAL = "0b000"; - defparam DCU1_inst.CH1_DCOSTEP = "0b00"; - defparam DCU1_inst.CH1_BAND_THRESHOLD = "0d0"; - defparam DCU1_inst.CH1_AUTO_FACQ_EN = "0b1"; - defparam DCU1_inst.CH1_AUTO_CALIB_EN = "0b1"; - defparam DCU1_inst.CH1_CALIB_CK_MODE = "0b0"; - defparam DCU1_inst.CH1_REG_BAND_OFFSET = "0d0"; - defparam DCU1_inst.CH1_REG_BAND_SEL = "0d0"; - defparam DCU1_inst.CH1_REG_IDAC_SEL = "0d0"; - defparam DCU1_inst.CH1_REG_IDAC_EN = "0b0"; - defparam DCU1_inst.D_CMUSETISCL4VCO = "0b000"; - defparam DCU1_inst.D_CMUSETI4VCO = "0b00"; - defparam DCU1_inst.D_CMUSETINITVCT = "0b00"; - defparam DCU1_inst.D_CMUSETZGM = "0b000"; - defparam DCU1_inst.D_CMUSETP2AGM = "0b000"; - defparam DCU1_inst.D_CMUSETP1GM = "0b000"; - defparam DCU1_inst.D_CMUSETI4CPZ = "0d3"; - defparam DCU1_inst.D_CMUSETI4CPP = "0d3"; - defparam DCU1_inst.D_CMUSETICP4Z = "0b101"; - defparam DCU1_inst.D_CMUSETICP4P = "0b01"; - defparam DCU1_inst.D_CMUSETBIASI = "0b00"; - defparam DCU1_inst.D_SETPLLRC = "0d1"; - defparam DCU1_inst.CH1_RX_RATE_SEL = "0d8"; - defparam DCU1_inst.D_REFCK_MODE = "0b100"; - defparam DCU1_inst.D_TX_VCO_CK_DIV = "0b010"; - defparam DCU1_inst.D_PLL_LOL_SET = "0b00"; - defparam DCU1_inst.D_RG_EN = "0b0"; - defparam DCU1_inst.D_RG_SET = "0b00"; - assign n1 = 1'bz; - assign n2 = 1'bz; - assign n3 = 1'bz; - assign n4 = 1'bz; - assign n5 = 1'bz; - assign n6 = 1'bz; - assign n7 = 1'bz; - assign n8 = 1'bz; - assign n9 = 1'bz; - assign n10 = 1'bz; - assign n11 = 1'bz; - assign n12 = 1'bz; - assign n13 = 1'bz; - assign n14 = 1'bz; - assign n15 = 1'bz; - assign n16 = 1'bz; - assign n17 = 1'bz; - assign n18 = 1'bz; - assign n19 = 1'bz; - assign n20 = 1'bz; - assign n21 = 1'bz; - assign n22 = 1'bz; - assign n23 = 1'bz; - assign n24 = 1'bz; - assign n25 = 1'bz; - assign n26 = 1'bz; - assign n27 = 1'bz; - assign n28 = 1'bz; - assign n29 = 1'bz; - assign n30 = 1'bz; - assign n31 = 1'bz; - assign n32 = 1'bz; - assign n33 = 1'bz; - assign n34 = 1'bz; - assign n35 = 1'bz; - assign n36 = 1'bz; - assign n37 = 1'bz; - assign n38 = 1'bz; - assign n39 = 1'bz; - assign n40 = 1'bz; - assign n41 = 1'bz; - assign n42 = 1'bz; - assign n43 = 1'bz; - assign n46 = 1'bz; - assign n47 = 1'bz; - assign n48 = 1'bz; - assign n49 = 1'bz; - assign n50 = 1'bz; - assign n51 = 1'bz; - assign n52 = 1'bz; - assign n53 = 1'bz; - assign n54 = 1'bz; - assign n55 = 1'bz; - assign n56 = 1'bz; - assign n57 = 1'bz; - assign n58 = 1'bz; - assign n59 = 1'bz; - assign n60 = 1'bz; - assign n61 = 1'bz; - assign n62 = 1'bz; - assign n63 = 1'bz; - assign n64 = 1'bz; - assign n65 = 1'bz; - assign n66 = 1'bz; - assign n67 = 1'bz; - assign n68 = 1'bz; - assign n69 = 1'bz; - assign n70 = 1'bz; - assign n71 = 1'bz; - assign n72 = 1'bz; - assign n73 = 1'bz; - assign n74 = 1'bz; - assign n75 = 1'bz; - assign n76 = 1'bz; - assign n77 = 1'bz; - assign n78 = 1'bz; - assign n79 = 1'bz; - assign n80 = 1'bz; - assign n81 = 1'bz; - assign n82 = 1'bz; - assign n83 = 1'bz; - assign n84 = 1'bz; - assign n85 = 1'bz; - assign n86 = 1'bz; - assign n87 = 1'bz; - assign n88 = 1'bz; - assign n89 = 1'bz; - assign n90 = 1'bz; - assign n91 = 1'bz; - assign n92 = 1'bz; - assign n93 = 1'bz; - assign n94 = 1'bz; - assign n95 = 1'bz; - assign n96 = 1'bz; - assign n97 = 1'bz; - assign n98 = 1'bz; - assign n99 = 1'bz; - assign n100 = 1'bz; - assign n101 = 1'bz; - assign _Z = 1'bz; - -endmodule - |
