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-rw-r--r--clarity/pcs/sgmii2/sgmii2.fdc3
-rw-r--r--clarity/pcs/sgmii2/sgmii2.lpc97
-rw-r--r--clarity/pcs/sgmii2/sgmii2.v439
-rw-r--r--clarity/pcs/sgmii2/sgmii2_softlogic.v1060
4 files changed, 1599 insertions, 0 deletions
diff --git a/clarity/pcs/sgmii2/sgmii2.fdc b/clarity/pcs/sgmii2/sgmii2.fdc
new file mode 100644
index 0000000..29b09af
--- /dev/null
+++ b/clarity/pcs/sgmii2/sgmii2.fdc
@@ -0,0 +1,3 @@
+###==== Start Generation
+
+define_attribute {i:Lane0} {loc} {DCU1_CH0}
diff --git a/clarity/pcs/sgmii2/sgmii2.lpc b/clarity/pcs/sgmii2/sgmii2.lpc
new file mode 100644
index 0000000..5e8a34b
--- /dev/null
+++ b/clarity/pcs/sgmii2/sgmii2.lpc
@@ -0,0 +1,97 @@
+[Device]
+Family=ecp5um
+OperatingCondition=COM
+Package=CABGA381
+PartName=LFE5UM-45F-8BG381C
+PartType=LFE5UM-45F
+SpeedGrade=8
+Status=P
+[IP]
+CoreName=PCS
+CoreRevision=8.2
+CoreStatus=Demo
+CoreType=LPM
+Date=03/15/2019
+ModuleName=sgmii2
+ParameterFileVersion=1.0
+SourceFormat=verilog
+Time=18:46:19
+VendorName=Lattice Semiconductor Corporation
+[Parameters]
+;ACHARA=0 00H
+;ACHARB=0 00H
+;ACHARM=0 00H
+;RXMCAENABLE=Disabled
+CDRLOLACTION=Full Recalibration
+CDRLOLRANGE=0
+CDR_MAX_RATE=1.25
+CDR_MULT=25X
+CDR_REF_RATE=50.0000
+CH_MODE=Rx and Tx
+Destination=Synplicity
+EDIF=1
+Expression=BusA(0 to 7)
+IO=0
+IO_TYPE=GbE
+LEQ=0
+LOOPBACK=Disabled
+LOSPORT=Enabled
+NUM_CHS=1
+Order=Big Endian [MSB:LSB]
+PPORT_RX_RDY=Disabled
+PPORT_TX_RDY=Disabled
+PROTOCOL=GbE
+PWAIT_RX_RDY=3000
+PWAIT_TX_RDY=3000
+RCSRC=Disabled
+REFCLK_RATE=50.0000
+RSTSEQSEL=Disabled
+RX8B10B=Enabled
+RXCOMMAA=1010000011
+RXCOMMAB=0101111100
+RXCOMMAM=1111111111
+RXCOUPLING=AC
+RXCTC=Enabled
+RXCTCBYTEN=0 00H
+RXCTCBYTEN1=0 00H
+RXCTCBYTEN2=1 BCH
+RXCTCBYTEN3=0 50H
+RXCTCMATCHPATTERN=M2-S2
+RXDIFFTERM=50 ohms
+RXFIFO_ENABLE=Enabled
+RXINVPOL=Non-invert
+RXLDR=Off
+RXLOSTHRESHOLD=4
+RXLSM=Enabled
+RXSC=K28P5
+RXWA=Barrel Shift
+RX_DATA_WIDTH=8/10-Bit
+RX_FICLK_RATE=125.0000
+RX_LINE_RATE=1.2500
+RX_RATE_DIV=Full Rate
+SCIPORT=Enabled
+SOFTLOL=Enabled
+TX8B10B=Enabled
+TXAMPLITUDE=400
+TXDEPOST=Disabled
+TXDEPRE=Disabled
+TXDIFFTERM=50 ohms
+TXFIFO_ENABLE=Enabled
+TXINVPOL=Non-invert
+TXLDR=Off
+TXPLLLOLTHRESHOLD=0
+TXPLLMULT=25X
+TX_DATA_WIDTH=8/10-Bit
+TX_FICLK_RATE=125.0000
+TX_LINE_RATE=1.2500
+TX_MAX_RATE=1.25
+TX_RATE_DIV=Full Rate
+VHDL=0
+Verilog=1
+[FilesGenerated]
+sgmii2.pp=pp
+sgmii2.sym=sym
+sgmii2.tft=tft
+sgmii2.txt=pcs_module
+[SYSTEMPNR]
+LN0=DCU1_CH0
diff --git a/clarity/pcs/sgmii2/sgmii2.v b/clarity/pcs/sgmii2/sgmii2.v
new file mode 100644
index 0000000..77abaf2
--- /dev/null
+++ b/clarity/pcs/sgmii2/sgmii2.v
@@ -0,0 +1,439 @@
+// Verilog netlist produced by program ASBGen: Ports rev. 2.30, Attr. rev. 2.70
+// Netlist written on Fri Mar 15 18:48:22 2019
+//
+// Verilog Description of module sgmii2
+//
+
+`timescale 1ns/1ps
+module sgmii2 (hdoutp, hdoutn, hdinp, hdinn, rxrefclk,
+ tx_pclk, txi_clk, txdata, tx_k, xmit, tx_disp_correct,
+ rxdata, rx_k, rx_disp_err, rx_cv_err, signal_detect_c,
+ rx_los_low_s, lsm_status_s, ctc_urun_s, ctc_orun_s, rx_cdr_lol_s,
+ ctc_ins_s, ctc_del_s, tx_pcs_rst_c, rx_pcs_rst_c, rx_serdes_rst_c,
+ tx_pwrup_c, rx_pwrup_c, sci_wrdata, sci_addr, sci_rddata,
+ sci_en_dual, sci_sel_dual, sci_en, sci_sel, sci_rd, sci_wrn,
+ sci_int, cyawstn, rst_dual_c, serdes_rst_dual_c, serdes_pdb,
+ tx_serdes_rst_c, pll_refclki, sli_rst, pll_lol);
+ output hdoutp;
+ output hdoutn;
+ input hdinp;
+ input hdinn;
+ input rxrefclk;
+ output tx_pclk;
+ input txi_clk;
+ input [7:0]txdata;
+ input [0:0]tx_k;
+ input [0:0]xmit;
+ input [0:0]tx_disp_correct;
+ output [7:0]rxdata;
+ output [0:0]rx_k;
+ output [0:0]rx_disp_err;
+ output [0:0]rx_cv_err;
+ input signal_detect_c;
+ output rx_los_low_s;
+ output lsm_status_s;
+ output ctc_urun_s;
+ output ctc_orun_s;
+ output rx_cdr_lol_s;
+ output ctc_ins_s;
+ output ctc_del_s;
+ input tx_pcs_rst_c;
+ input rx_pcs_rst_c;
+ input rx_serdes_rst_c;
+ input tx_pwrup_c;
+ input rx_pwrup_c;
+ input [7:0]sci_wrdata;
+ input [5:0]sci_addr;
+ output [7:0]sci_rddata;
+ input sci_en_dual;
+ input sci_sel_dual;
+ input sci_en;
+ input sci_sel;
+ input sci_rd;
+ input sci_wrn;
+ output sci_int;
+ input cyawstn;
+ input rst_dual_c;
+ input serdes_rst_dual_c;
+ input serdes_pdb;
+ input tx_serdes_rst_c;
+ input pll_refclki;
+ input sli_rst;
+ output pll_lol;
+
+
+ wire n1, n2, n3, n4, n5, n6, n7, n8, n9, n10, n11,
+ n12, n13, n14, n15, n16, n17, n18, n19, n20, n21,
+ n22, n23, n24, n25, n26, n27, n28, n29, n30, n31,
+ n32, n33, n34, n35, n36, n37, n38, n39, n40, n41,
+ n42, n43, n46, n47, n48, n49, n50, n51, n52, n53,
+ n54, n55, n56, n57, n58, n59, n60, n61, n62, n63,
+ n64, n65, n66, n67, n68, n69, n70, n71, n72, n73,
+ n74, n75, n76, n77, n78, n79, n80, n81, n82, n83,
+ n84, n85, n86, n87, n88, n89, n90, n91, n92, n93,
+ n94, n95, n96, n97, n98, n99, n100, n101, _Z;
+
+ DCUA DCU1_inst (.CH0_HDINP(hdinp), .CH1_HDINP(1'b0), .CH0_HDINN(hdinn),
+ .CH1_HDINN(1'b0), .D_TXBIT_CLKP_FROM_ND(1'b0), .D_TXBIT_CLKN_FROM_ND(1'b0),
+ .D_SYNC_ND(1'b0), .D_TXPLL_LOL_FROM_ND(1'b0), .CH0_RX_REFCLK(rxrefclk),
+ .CH1_RX_REFCLK(1'b0), .CH0_FF_RXI_CLK(tx_pclk), .CH1_FF_RXI_CLK(1'b1),
+ .CH0_FF_TXI_CLK(txi_clk), .CH1_FF_TXI_CLK(1'b1), .CH0_FF_EBRD_CLK(tx_pclk),
+ .CH1_FF_EBRD_CLK(1'b1), .CH0_FF_TX_D_0(txdata[0]), .CH1_FF_TX_D_0(1'b0),
+ .CH0_FF_TX_D_1(txdata[1]), .CH1_FF_TX_D_1(1'b0), .CH0_FF_TX_D_2(txdata[2]),
+ .CH1_FF_TX_D_2(1'b0), .CH0_FF_TX_D_3(txdata[3]), .CH1_FF_TX_D_3(1'b0),
+ .CH0_FF_TX_D_4(txdata[4]), .CH1_FF_TX_D_4(1'b0), .CH0_FF_TX_D_5(txdata[5]),
+ .CH1_FF_TX_D_5(1'b0), .CH0_FF_TX_D_6(txdata[6]), .CH1_FF_TX_D_6(1'b0),
+ .CH0_FF_TX_D_7(txdata[7]), .CH1_FF_TX_D_7(1'b0), .CH0_FF_TX_D_8(tx_k[0]),
+ .CH1_FF_TX_D_8(1'b0), .CH0_FF_TX_D_9(1'b0), .CH1_FF_TX_D_9(1'b0),
+ .CH0_FF_TX_D_10(xmit[0]), .CH1_FF_TX_D_10(1'b0), .CH0_FF_TX_D_11(tx_disp_correct[0]),
+ .CH1_FF_TX_D_11(1'b0), .CH0_FF_TX_D_12(1'b0), .CH1_FF_TX_D_12(1'b0),
+ .CH0_FF_TX_D_13(1'b0), .CH1_FF_TX_D_13(1'b0), .CH0_FF_TX_D_14(1'b0),
+ .CH1_FF_TX_D_14(1'b0), .CH0_FF_TX_D_15(1'b0), .CH1_FF_TX_D_15(1'b0),
+ .CH0_FF_TX_D_16(1'b0), .CH1_FF_TX_D_16(1'b0), .CH0_FF_TX_D_17(1'b0),
+ .CH1_FF_TX_D_17(1'b0), .CH0_FF_TX_D_18(1'b0), .CH1_FF_TX_D_18(1'b0),
+ .CH0_FF_TX_D_19(1'b0), .CH1_FF_TX_D_19(1'b0), .CH0_FF_TX_D_20(1'b0),
+ .CH1_FF_TX_D_20(1'b0), .CH0_FF_TX_D_21(1'b0), .CH1_FF_TX_D_21(1'b0),
+ .CH0_FF_TX_D_22(1'b0), .CH1_FF_TX_D_22(1'b0), .CH0_FF_TX_D_23(1'b0),
+ .CH1_FF_TX_D_23(1'b0), .CH0_FFC_EI_EN(1'b0), .CH1_FFC_EI_EN(1'b0),
+ .CH0_FFC_PCIE_DET_EN(1'b0), .CH1_FFC_PCIE_DET_EN(1'b0), .CH0_FFC_PCIE_CT(1'b0),
+ .CH1_FFC_PCIE_CT(1'b0), .CH0_FFC_SB_INV_RX(1'b0), .CH1_FFC_SB_INV_RX(1'b0),
+ .CH0_FFC_ENABLE_CGALIGN(1'b0), .CH1_FFC_ENABLE_CGALIGN(1'b0), .CH0_FFC_SIGNAL_DETECT(signal_detect_c),
+ .CH1_FFC_SIGNAL_DETECT(1'b0), .CH0_FFC_FB_LOOPBACK(1'b0), .CH1_FFC_FB_LOOPBACK(1'b0),
+ .CH0_FFC_SB_PFIFO_LP(1'b0), .CH1_FFC_SB_PFIFO_LP(1'b0), .CH0_FFC_PFIFO_CLR(1'b0),
+ .CH1_FFC_PFIFO_CLR(1'b0), .CH0_FFC_RATE_MODE_RX(1'b0), .CH1_FFC_RATE_MODE_RX(1'b0),
+ .CH0_FFC_RATE_MODE_TX(1'b0), .CH1_FFC_RATE_MODE_TX(1'b0), .CH0_FFC_DIV11_MODE_RX(1'b0),
+ .CH1_FFC_DIV11_MODE_RX(1'b0), .CH0_FFC_DIV11_MODE_TX(1'b0), .CH1_FFC_DIV11_MODE_TX(1'b0),
+ .CH0_FFC_RX_GEAR_MODE(1'b0), .CH1_FFC_RX_GEAR_MODE(1'b0), .CH0_FFC_TX_GEAR_MODE(1'b0),
+ .CH1_FFC_TX_GEAR_MODE(1'b0), .CH0_FFC_LDR_CORE2TX_EN(1'b0), .CH1_FFC_LDR_CORE2TX_EN(1'b0),
+ .CH0_FFC_LANE_TX_RST(tx_pcs_rst_c), .CH1_FFC_LANE_TX_RST(1'b0),
+ .CH0_FFC_LANE_RX_RST(rx_pcs_rst_c), .CH1_FFC_LANE_RX_RST(1'b0),
+ .CH0_FFC_RRST(rx_serdes_rst_c), .CH1_FFC_RRST(1'b0), .CH0_FFC_TXPWDNB(tx_pwrup_c),
+ .CH1_FFC_TXPWDNB(1'b0), .CH0_FFC_RXPWDNB(rx_pwrup_c), .CH1_FFC_RXPWDNB(1'b0),
+ .CH0_LDR_CORE2TX(1'b0), .CH1_LDR_CORE2TX(1'b0), .D_SCIWDATA0(sci_wrdata[0]),
+ .D_SCIWDATA1(sci_wrdata[1]), .D_SCIWDATA2(sci_wrdata[2]), .D_SCIWDATA3(sci_wrdata[3]),
+ .D_SCIWDATA4(sci_wrdata[4]), .D_SCIWDATA5(sci_wrdata[5]), .D_SCIWDATA6(sci_wrdata[6]),
+ .D_SCIWDATA7(sci_wrdata[7]), .D_SCIADDR0(sci_addr[0]), .D_SCIADDR1(sci_addr[1]),
+ .D_SCIADDR2(sci_addr[2]), .D_SCIADDR3(sci_addr[3]), .D_SCIADDR4(sci_addr[4]),
+ .D_SCIADDR5(sci_addr[5]), .D_SCIENAUX(sci_en_dual), .D_SCISELAUX(sci_sel_dual),
+ .CH0_SCIEN(sci_en), .CH1_SCIEN(1'b0), .CH0_SCISEL(sci_sel), .CH1_SCISEL(1'b0),
+ .D_SCIRD(sci_rd), .D_SCIWSTN(sci_wrn), .D_CYAWSTN(cyawstn), .D_FFC_SYNC_TOGGLE(1'b0),
+ .D_FFC_DUAL_RST(rst_dual_c), .D_FFC_MACRO_RST(serdes_rst_dual_c),
+ .D_FFC_MACROPDB(serdes_pdb), .D_FFC_TRST(tx_serdes_rst_c), .CH0_FFC_CDR_EN_BITSLIP(1'b0),
+ .CH1_FFC_CDR_EN_BITSLIP(1'b0), .D_SCAN_ENABLE(1'b0), .D_SCAN_IN_0(1'b0),
+ .D_SCAN_IN_1(1'b0), .D_SCAN_IN_2(1'b0), .D_SCAN_IN_3(1'b0), .D_SCAN_IN_4(1'b0),
+ .D_SCAN_IN_5(1'b0), .D_SCAN_IN_6(1'b0), .D_SCAN_IN_7(1'b0), .D_SCAN_MODE(1'b0),
+ .D_SCAN_RESET(1'b0), .D_CIN0(1'b0), .D_CIN1(1'b0), .D_CIN2(1'b0),
+ .D_CIN3(1'b0), .D_CIN4(1'b0), .D_CIN5(1'b0), .D_CIN6(1'b0),
+ .D_CIN7(1'b0), .D_CIN8(1'b0), .D_CIN9(1'b0), .D_CIN10(1'b0),
+ .D_CIN11(1'b0), .CH0_HDOUTP(hdoutp), .CH1_HDOUTP(n47), .CH0_HDOUTN(hdoutn),
+ .CH1_HDOUTN(n48), .D_TXBIT_CLKP_TO_ND(n1), .D_TXBIT_CLKN_TO_ND(n2),
+ .D_SYNC_PULSE2ND(n3), .D_TXPLL_LOL_TO_ND(n4), .CH0_FF_RX_F_CLK(n5),
+ .CH1_FF_RX_F_CLK(n49), .CH0_FF_RX_H_CLK(n6), .CH1_FF_RX_H_CLK(n50),
+ .CH0_FF_TX_F_CLK(n7), .CH1_FF_TX_F_CLK(n51), .CH0_FF_TX_H_CLK(n8),
+ .CH1_FF_TX_H_CLK(n52), .CH0_FF_RX_PCLK(n9), .CH1_FF_RX_PCLK(n53),
+ .CH0_FF_TX_PCLK(tx_pclk), .CH1_FF_TX_PCLK(n54), .CH0_FF_RX_D_0(rxdata[0]),
+ .CH1_FF_RX_D_0(n55), .CH0_FF_RX_D_1(rxdata[1]), .CH1_FF_RX_D_1(n56),
+ .CH0_FF_RX_D_2(rxdata[2]), .CH1_FF_RX_D_2(n57), .CH0_FF_RX_D_3(rxdata[3]),
+ .CH1_FF_RX_D_3(n58), .CH0_FF_RX_D_4(rxdata[4]), .CH1_FF_RX_D_4(n59),
+ .CH0_FF_RX_D_5(rxdata[5]), .CH1_FF_RX_D_5(n60), .CH0_FF_RX_D_6(rxdata[6]),
+ .CH1_FF_RX_D_6(n61), .CH0_FF_RX_D_7(rxdata[7]), .CH1_FF_RX_D_7(n62),
+ .CH0_FF_RX_D_8(rx_k[0]), .CH1_FF_RX_D_8(n63), .CH0_FF_RX_D_9(rx_disp_err[0]),
+ .CH1_FF_RX_D_9(n64), .CH0_FF_RX_D_10(rx_cv_err[0]), .CH1_FF_RX_D_10(n65),
+ .CH0_FF_RX_D_11(n10), .CH1_FF_RX_D_11(n66), .CH0_FF_RX_D_12(n67),
+ .CH1_FF_RX_D_12(n68), .CH0_FF_RX_D_13(n69), .CH1_FF_RX_D_13(n70),
+ .CH0_FF_RX_D_14(n71), .CH1_FF_RX_D_14(n72), .CH0_FF_RX_D_15(n73),
+ .CH1_FF_RX_D_15(n74), .CH0_FF_RX_D_16(n75), .CH1_FF_RX_D_16(n76),
+ .CH0_FF_RX_D_17(n77), .CH1_FF_RX_D_17(n78), .CH0_FF_RX_D_18(n79),
+ .CH1_FF_RX_D_18(n80), .CH0_FF_RX_D_19(n81), .CH1_FF_RX_D_19(n82),
+ .CH0_FF_RX_D_20(n83), .CH1_FF_RX_D_20(n84), .CH0_FF_RX_D_21(n85),
+ .CH1_FF_RX_D_21(n86), .CH0_FF_RX_D_22(n87), .CH1_FF_RX_D_22(n88),
+ .CH0_FF_RX_D_23(n11), .CH1_FF_RX_D_23(n89), .CH0_FFS_PCIE_DONE(n12),
+ .CH1_FFS_PCIE_DONE(n90), .CH0_FFS_PCIE_CON(n13), .CH1_FFS_PCIE_CON(n91),
+ .CH0_FFS_RLOS(rx_los_low_s), .CH1_FFS_RLOS(n92), .CH0_FFS_LS_SYNC_STATUS(lsm_status_s),
+ .CH1_FFS_LS_SYNC_STATUS(n93), .CH0_FFS_CC_UNDERRUN(ctc_urun_s),
+ .CH1_FFS_CC_UNDERRUN(n94), .CH0_FFS_CC_OVERRUN(ctc_orun_s), .CH1_FFS_CC_OVERRUN(n95),
+ .CH0_FFS_RXFBFIFO_ERROR(n14), .CH1_FFS_RXFBFIFO_ERROR(n96), .CH0_FFS_TXFBFIFO_ERROR(n15),
+ .CH1_FFS_TXFBFIFO_ERROR(n97), .CH0_FFS_RLOL(rx_cdr_lol_s), .CH1_FFS_RLOL(n98),
+ .CH0_FFS_SKP_ADDED(ctc_ins_s), .CH1_FFS_SKP_ADDED(n99), .CH0_FFS_SKP_DELETED(ctc_del_s),
+ .CH1_FFS_SKP_DELETED(n100), .CH0_LDR_RX2CORE(n101), .CH1_LDR_RX2CORE(_Z),
+ .D_SCIRDATA0(sci_rddata[0]), .D_SCIRDATA1(sci_rddata[1]), .D_SCIRDATA2(sci_rddata[2]),
+ .D_SCIRDATA3(sci_rddata[3]), .D_SCIRDATA4(sci_rddata[4]), .D_SCIRDATA5(sci_rddata[5]),
+ .D_SCIRDATA6(sci_rddata[6]), .D_SCIRDATA7(sci_rddata[7]), .D_SCIINT(sci_int),
+ .D_SCAN_OUT_0(n16), .D_SCAN_OUT_1(n17), .D_SCAN_OUT_2(n18), .D_SCAN_OUT_3(n19),
+ .D_SCAN_OUT_4(n20), .D_SCAN_OUT_5(n21), .D_SCAN_OUT_6(n22), .D_SCAN_OUT_7(n23),
+ .D_COUT0(n24), .D_COUT1(n25), .D_COUT2(n26), .D_COUT3(n27),
+ .D_COUT4(n28), .D_COUT5(n29), .D_COUT6(n30), .D_COUT7(n31),
+ .D_COUT8(n32), .D_COUT9(n33), .D_COUT10(n34), .D_COUT11(n35),
+ .D_COUT12(n36), .D_COUT13(n37), .D_COUT14(n38), .D_COUT15(n39),
+ .D_COUT16(n40), .D_COUT17(n41), .D_COUT18(n42), .D_COUT19(n43),
+ .D_REFCLKI(pll_refclki), .D_FFS_PLOL(pll_lol)) /* synthesis LOC=DCU1 CHAN=CH0 */ ;
+ defparam DCU1_inst.D_MACROPDB = "0b1";
+ defparam DCU1_inst.D_IB_PWDNB = "0b1";
+ defparam DCU1_inst.D_XGE_MODE = "0b0";
+ defparam DCU1_inst.D_LOW_MARK = "0d4";
+ defparam DCU1_inst.D_HIGH_MARK = "0d12";
+ defparam DCU1_inst.D_BUS8BIT_SEL = "0b0";
+ defparam DCU1_inst.D_CDR_LOL_SET = "0b00";
+ defparam DCU1_inst.D_TXPLL_PWDNB = "0b1";
+ defparam DCU1_inst.D_BITCLK_LOCAL_EN = "0b1";
+ defparam DCU1_inst.D_BITCLK_ND_EN = "0b0";
+ defparam DCU1_inst.D_BITCLK_FROM_ND_EN = "0b0";
+ defparam DCU1_inst.D_SYNC_LOCAL_EN = "0b1";
+ defparam DCU1_inst.D_SYNC_ND_EN = "0b0";
+ defparam DCU1_inst.CH0_UC_MODE = "0b0";
+ defparam DCU1_inst.CH0_PCIE_MODE = "0b0";
+ defparam DCU1_inst.CH0_RIO_MODE = "0b0";
+ defparam DCU1_inst.CH0_WA_MODE = "0b0";
+ defparam DCU1_inst.CH0_INVERT_RX = "0b0";
+ defparam DCU1_inst.CH0_INVERT_TX = "0b0";
+ defparam DCU1_inst.CH0_PRBS_SELECTION = "0b0";
+ defparam DCU1_inst.CH0_GE_AN_ENABLE = "0b0";
+ defparam DCU1_inst.CH0_PRBS_LOCK = "0b0";
+ defparam DCU1_inst.CH0_PRBS_ENABLE = "0b0";
+ defparam DCU1_inst.CH0_ENABLE_CG_ALIGN = "0b1";
+ defparam DCU1_inst.CH0_TX_GEAR_MODE = "0b0";
+ defparam DCU1_inst.CH0_RX_GEAR_MODE = "0b0";
+ defparam DCU1_inst.CH0_PCS_DET_TIME_SEL = "0b00";
+ defparam DCU1_inst.CH0_PCIE_EI_EN = "0b0";
+ defparam DCU1_inst.CH0_TX_GEAR_BYPASS = "0b0";
+ defparam DCU1_inst.CH0_ENC_BYPASS = "0b0";
+ defparam DCU1_inst.CH0_SB_BYPASS = "0b0";
+ defparam DCU1_inst.CH0_RX_SB_BYPASS = "0b0";
+ defparam DCU1_inst.CH0_WA_BYPASS = "0b0";
+ defparam DCU1_inst.CH0_DEC_BYPASS = "0b0";
+ defparam DCU1_inst.CH0_CTC_BYPASS = "0b0";
+ defparam DCU1_inst.CH0_RX_GEAR_BYPASS = "0b0";
+ defparam DCU1_inst.CH0_LSM_DISABLE = "0b0";
+ defparam DCU1_inst.CH0_MATCH_2_ENABLE = "0b1";
+ defparam DCU1_inst.CH0_MATCH_4_ENABLE = "0b0";
+ defparam DCU1_inst.CH0_MIN_IPG_CNT = "0b11";
+ defparam DCU1_inst.CH0_CC_MATCH_1 = "0x000";
+ defparam DCU1_inst.CH0_CC_MATCH_2 = "0x000";
+ defparam DCU1_inst.CH0_CC_MATCH_3 = "0x1BC";
+ defparam DCU1_inst.CH0_CC_MATCH_4 = "0x050";
+ defparam DCU1_inst.CH0_UDF_COMMA_MASK = "0x3ff";
+ defparam DCU1_inst.CH0_UDF_COMMA_A = "0x283";
+ defparam DCU1_inst.CH0_UDF_COMMA_B = "0x17C";
+ defparam DCU1_inst.CH0_RX_DCO_CK_DIV = "0b010";
+ defparam DCU1_inst.CH0_RCV_DCC_EN = "0b0";
+ defparam DCU1_inst.CH0_TPWDNB = "0b1";
+ defparam DCU1_inst.CH0_RATE_MODE_TX = "0b0";
+ defparam DCU1_inst.CH0_RTERM_TX = "0d19";
+ defparam DCU1_inst.CH0_TX_CM_SEL = "0b00";
+ defparam DCU1_inst.CH0_TDRV_PRE_EN = "0b0";
+ defparam DCU1_inst.CH0_TDRV_SLICE0_SEL = "0b00";
+ defparam DCU1_inst.CH0_TDRV_SLICE1_SEL = "0b00";
+ defparam DCU1_inst.CH0_TDRV_SLICE2_SEL = "0b01";
+ defparam DCU1_inst.CH0_TDRV_SLICE3_SEL = "0b01";
+ defparam DCU1_inst.CH0_TDRV_SLICE4_SEL = "0b00";
+ defparam DCU1_inst.CH0_TDRV_SLICE5_SEL = "0b00";
+ defparam DCU1_inst.CH0_TDRV_SLICE0_CUR = "0b000";
+ defparam DCU1_inst.CH0_TDRV_SLICE1_CUR = "0b000";
+ defparam DCU1_inst.CH0_TDRV_SLICE2_CUR = "0b11";
+ defparam DCU1_inst.CH0_TDRV_SLICE3_CUR = "0b00";
+ defparam DCU1_inst.CH0_TDRV_SLICE4_CUR = "0b00";
+ defparam DCU1_inst.CH0_TDRV_SLICE5_CUR = "0b00";
+ defparam DCU1_inst.CH0_TDRV_DAT_SEL = "0b00";
+ defparam DCU1_inst.CH0_TX_DIV11_SEL = "0b0";
+ defparam DCU1_inst.CH0_RPWDNB = "0b1";
+ defparam DCU1_inst.CH0_RATE_MODE_RX = "0b0";
+ defparam DCU1_inst.CH0_RX_DIV11_SEL = "0b0";
+ defparam DCU1_inst.CH0_SEL_SD_RX_CLK = "0b0";
+ defparam DCU1_inst.CH0_FF_RX_H_CLK_EN = "0b0";
+ defparam DCU1_inst.CH0_FF_RX_F_CLK_DIS = "0b0";
+ defparam DCU1_inst.CH0_FF_TX_H_CLK_EN = "0b0";
+ defparam DCU1_inst.CH0_FF_TX_F_CLK_DIS = "0b0";
+ defparam DCU1_inst.CH0_TDRV_POST_EN = "0b0";
+ defparam DCU1_inst.CH0_TX_POST_SIGN = "0b0";
+ defparam DCU1_inst.CH0_TX_PRE_SIGN = "0b0";
+ defparam DCU1_inst.CH0_REQ_LVL_SET = "0b00";
+ defparam DCU1_inst.CH0_REQ_EN = "0b1";
+ defparam DCU1_inst.CH0_RTERM_RX = "0d22";
+ defparam DCU1_inst.CH0_RXTERM_CM = "0b11";
+ defparam DCU1_inst.CH0_PDEN_SEL = "0b1";
+ defparam DCU1_inst.CH0_RXIN_CM = "0b11";
+ defparam DCU1_inst.CH0_LEQ_OFFSET_SEL = "0b0";
+ defparam DCU1_inst.CH0_LEQ_OFFSET_TRIM = "0b000";
+ defparam DCU1_inst.CH0_RLOS_SEL = "0b1";
+ defparam DCU1_inst.CH0_RX_LOS_LVL = "0b100";
+ defparam DCU1_inst.CH0_RX_LOS_CEQ = "0b11";
+ defparam DCU1_inst.CH0_RX_LOS_HYST_EN = "0b0";
+ defparam DCU1_inst.CH0_RX_LOS_EN = "0b1";
+ defparam DCU1_inst.CH0_LDR_RX2CORE_SEL = "0b0";
+ defparam DCU1_inst.CH0_LDR_CORE2TX_SEL = "0b0";
+ defparam DCU1_inst.D_TX_MAX_RATE = "1.25";
+ defparam DCU1_inst.CH0_CDR_MAX_RATE = "1.25";
+ defparam DCU1_inst.CH0_TXAMPLITUDE = "0d400";
+ defparam DCU1_inst.CH0_TXDEPRE = "DISABLED";
+ defparam DCU1_inst.CH0_TXDEPOST = "DISABLED";
+ defparam DCU1_inst.CH0_PROTOCOL = "GBE";
+ defparam DCU1_inst.D_ISETLOS = "0d0";
+ defparam DCU1_inst.D_SETIRPOLY_AUX = "0b00";
+ defparam DCU1_inst.D_SETICONST_AUX = "0b00";
+ defparam DCU1_inst.D_SETIRPOLY_CH = "0b00";
+ defparam DCU1_inst.D_SETICONST_CH = "0b00";
+ defparam DCU1_inst.D_REQ_ISET = "0b000";
+ defparam DCU1_inst.D_PD_ISET = "0b00";
+ defparam DCU1_inst.D_DCO_CALIB_TIME_SEL = "0b00";
+ defparam DCU1_inst.CH0_CDR_CNT4SEL = "0b00";
+ defparam DCU1_inst.CH0_CDR_CNT8SEL = "0b00";
+ defparam DCU1_inst.CH0_DCOATDCFG = "0b00";
+ defparam DCU1_inst.CH0_DCOATDDLY = "0b00";
+ defparam DCU1_inst.CH0_DCOBYPSATD = "0b1";
+ defparam DCU1_inst.CH0_DCOCALDIV = "0b001";
+ defparam DCU1_inst.CH0_DCOCTLGI = "0b010";
+ defparam DCU1_inst.CH0_DCODISBDAVOID = "0b0";
+ defparam DCU1_inst.CH0_DCOFLTDAC = "0b01";
+ defparam DCU1_inst.CH0_DCOFTNRG = "0b110";
+ defparam DCU1_inst.CH0_DCOIOSTUNE = "0b000";
+ defparam DCU1_inst.CH0_DCOITUNE = "0b00";
+ defparam DCU1_inst.CH0_DCOITUNE4LSB = "0b111";
+ defparam DCU1_inst.CH0_DCOIUPDNX2 = "0b1";
+ defparam DCU1_inst.CH0_DCONUOFLSB = "0b101";
+ defparam DCU1_inst.CH0_DCOSCALEI = "0b00";
+ defparam DCU1_inst.CH0_DCOSTARTVAL = "0b000";
+ defparam DCU1_inst.CH0_DCOSTEP = "0b00";
+ defparam DCU1_inst.CH0_BAND_THRESHOLD = "0d0";
+ defparam DCU1_inst.CH0_AUTO_FACQ_EN = "0b1";
+ defparam DCU1_inst.CH0_AUTO_CALIB_EN = "0b1";
+ defparam DCU1_inst.CH0_CALIB_CK_MODE = "0b0";
+ defparam DCU1_inst.CH0_REG_BAND_OFFSET = "0d0";
+ defparam DCU1_inst.CH0_REG_BAND_SEL = "0d0";
+ defparam DCU1_inst.CH0_REG_IDAC_SEL = "0d0";
+ defparam DCU1_inst.CH0_REG_IDAC_EN = "0b0";
+ defparam DCU1_inst.D_CMUSETISCL4VCO = "0b000";
+ defparam DCU1_inst.D_CMUSETI4VCO = "0b00";
+ defparam DCU1_inst.D_CMUSETINITVCT = "0b00";
+ defparam DCU1_inst.D_CMUSETZGM = "0b000";
+ defparam DCU1_inst.D_CMUSETP2AGM = "0b000";
+ defparam DCU1_inst.D_CMUSETP1GM = "0b000";
+ defparam DCU1_inst.D_CMUSETI4CPZ = "0d3";
+ defparam DCU1_inst.D_CMUSETI4CPP = "0d3";
+ defparam DCU1_inst.D_CMUSETICP4Z = "0b101";
+ defparam DCU1_inst.D_CMUSETICP4P = "0b01";
+ defparam DCU1_inst.D_CMUSETBIASI = "0b00";
+ defparam DCU1_inst.D_SETPLLRC = "0d1";
+ defparam DCU1_inst.CH0_RX_RATE_SEL = "0d8";
+ defparam DCU1_inst.D_REFCK_MODE = "0b100";
+ defparam DCU1_inst.D_TX_VCO_CK_DIV = "0b010";
+ defparam DCU1_inst.D_PLL_LOL_SET = "0b00";
+ defparam DCU1_inst.D_RG_EN = "0b0";
+ defparam DCU1_inst.D_RG_SET = "0b00";
+ assign n1 = 1'bz;
+ assign n2 = 1'bz;
+ assign n3 = 1'bz;
+ assign n4 = 1'bz;
+ assign n5 = 1'bz;
+ assign n6 = 1'bz;
+ assign n7 = 1'bz;
+ assign n8 = 1'bz;
+ assign n9 = 1'bz;
+ assign n10 = 1'bz;
+ assign n11 = 1'bz;
+ assign n12 = 1'bz;
+ assign n13 = 1'bz;
+ assign n14 = 1'bz;
+ assign n15 = 1'bz;
+ assign n16 = 1'bz;
+ assign n17 = 1'bz;
+ assign n18 = 1'bz;
+ assign n19 = 1'bz;
+ assign n20 = 1'bz;
+ assign n21 = 1'bz;
+ assign n22 = 1'bz;
+ assign n23 = 1'bz;
+ assign n24 = 1'bz;
+ assign n25 = 1'bz;
+ assign n26 = 1'bz;
+ assign n27 = 1'bz;
+ assign n28 = 1'bz;
+ assign n29 = 1'bz;
+ assign n30 = 1'bz;
+ assign n31 = 1'bz;
+ assign n32 = 1'bz;
+ assign n33 = 1'bz;
+ assign n34 = 1'bz;
+ assign n35 = 1'bz;
+ assign n36 = 1'bz;
+ assign n37 = 1'bz;
+ assign n38 = 1'bz;
+ assign n39 = 1'bz;
+ assign n40 = 1'bz;
+ assign n41 = 1'bz;
+ assign n42 = 1'bz;
+ assign n43 = 1'bz;
+ assign n46 = 1'bz;
+ assign n47 = 1'bz;
+ assign n48 = 1'bz;
+ assign n49 = 1'bz;
+ assign n50 = 1'bz;
+ assign n51 = 1'bz;
+ assign n52 = 1'bz;
+ assign n53 = 1'bz;
+ assign n54 = 1'bz;
+ assign n55 = 1'bz;
+ assign n56 = 1'bz;
+ assign n57 = 1'bz;
+ assign n58 = 1'bz;
+ assign n59 = 1'bz;
+ assign n60 = 1'bz;
+ assign n61 = 1'bz;
+ assign n62 = 1'bz;
+ assign n63 = 1'bz;
+ assign n64 = 1'bz;
+ assign n65 = 1'bz;
+ assign n66 = 1'bz;
+ assign n67 = 1'bz;
+ assign n68 = 1'bz;
+ assign n69 = 1'bz;
+ assign n70 = 1'bz;
+ assign n71 = 1'bz;
+ assign n72 = 1'bz;
+ assign n73 = 1'bz;
+ assign n74 = 1'bz;
+ assign n75 = 1'bz;
+ assign n76 = 1'bz;
+ assign n77 = 1'bz;
+ assign n78 = 1'bz;
+ assign n79 = 1'bz;
+ assign n80 = 1'bz;
+ assign n81 = 1'bz;
+ assign n82 = 1'bz;
+ assign n83 = 1'bz;
+ assign n84 = 1'bz;
+ assign n85 = 1'bz;
+ assign n86 = 1'bz;
+ assign n87 = 1'bz;
+ assign n88 = 1'bz;
+ assign n89 = 1'bz;
+ assign n90 = 1'bz;
+ assign n91 = 1'bz;
+ assign n92 = 1'bz;
+ assign n93 = 1'bz;
+ assign n94 = 1'bz;
+ assign n95 = 1'bz;
+ assign n96 = 1'bz;
+ assign n97 = 1'bz;
+ assign n98 = 1'bz;
+ assign n99 = 1'bz;
+ assign n100 = 1'bz;
+ assign n101 = 1'bz;
+ assign _Z = 1'bz;
+ sgmii2sll_core sll_inst (.sli_rst(sli_rst), .sli_refclk(pll_refclki),
+ .sli_pclk(tx_pclk), .sli_div2_rate(1'b0), .sli_div11_rate(1'b0),
+ .sli_gear_mode(1'b0), .sli_cpri_mode({3'b000}), .sli_pcie_mode(1'b0),
+ .slo_plol());
+ defparam sll_inst.PPROTOCOL = "GBE";
+ defparam sll_inst.PLOL_SETTING = 0;
+ defparam sll_inst.PDYN_RATE_CTRL = "DISABLED";
+ defparam sll_inst.PPCIE_MAX_RATE = "2.5";
+ defparam sll_inst.PDIFF_VAL_LOCK = 98;
+ defparam sll_inst.PDIFF_VAL_UNLOCK = 196;
+ defparam sll_inst.PPCLK_TC = 327680;
+ defparam sll_inst.PDIFF_DIV11_VAL_LOCK = 0;
+ defparam sll_inst.PDIFF_DIV11_VAL_UNLOCK = 0;
+ defparam sll_inst.PPCLK_DIV11_TC = 0;
+
+endmodule
+
+
diff --git a/clarity/pcs/sgmii2/sgmii2_softlogic.v b/clarity/pcs/sgmii2/sgmii2_softlogic.v
new file mode 100644
index 0000000..5346253
--- /dev/null
+++ b/clarity/pcs/sgmii2/sgmii2_softlogic.v
@@ -0,0 +1,1060 @@
+
+// ===========================================================================
+// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
+// ---------------------------------------------------------------------------
+// Copyright (c) 2015 by Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// ------------------------------------------------------------------
+//
+// Permission:
+//
+// Lattice SG Pte. Ltd. grants permission to use this code
+// pursuant to the terms of the Lattice Reference Design License Agreement.
+//
+//
+// Disclaimer:
+//
+// This VHDL or Verilog source code is intended as a design reference
+// which illustrates how these types of functions can be implemented.
+// It is the user's responsibility to verify their design for
+// consistency and functionality through the use of formal
+// verification methods. Lattice provides no warranty
+// regarding the use or functionality of this code.
+//
+// ---------------------------------------------------------------------------
+//
+// Lattice SG Pte. Ltd.
+// 101 Thomson Road, United Square #07-02
+// Singapore 307591
+//
+//
+// TEL: 1-800-Lattice (USA and Canada)
+// +65-6631-2000 (Singapore)
+// +1-503-268-8001 (other locations)
+//
+// web: http://www.latticesemi.com/
+// email: techsupport@latticesemi.com
+//
+// ---------------------------------------------------------------------------
+//
+// =============================================================================
+// FILE DETAILS
+// Project : SLL - Soft Loss Of Lock(LOL) Logic
+// File : sll_core.v
+// Title : Top-level file for SLL
+// Dependencies : 1.
+// : 2.
+// Description :
+// =============================================================================
+// REVISION HISTORY
+// Version : 1.0
+// Author(s) : AV
+// Mod. Date : March 2, 2015
+// Changes Made : Initial Creation
+// =============================================================================
+// REVISION HISTORY
+// Version : 1.1
+// Author(s) : AV
+// Mod. Date : June 8, 2015
+// Changes Made : Following updates were made
+// : 1. Changed all the PLOL status logic and FSM to run
+// : on sli_refclk.
+// : 2. Added the HB logic for presence of tx_pclk
+// : 3. Changed the lparam assignment scheme for
+// : simulation purposes.
+// =============================================================================
+// REVISION HISTORY
+// Version : 1.2
+// Author(s) : AV
+// Mod. Date : June 24, 2015
+// Changes Made : Updated the gearing logic for SDI dynamic rate change
+// =============================================================================
+// REVISION HISTORY
+// Version : 1.3
+// Author(s) : AV
+// Mod. Date : July 14, 2015
+// Changes Made : Added the logic for dynamic rate change in CPRI
+// =============================================================================
+// REVISION HISTORY
+// Version : 1.4
+// Author(s) : AV
+// Mod. Date : August 21, 2015
+// Changes Made : Added the logic for dynamic rate change of 5G CPRI &
+// PCIe.
+// =============================================================================
+// REVISION HISTORY
+// Version : 1.5
+// Author(s) : ES/EB
+// Mod. Date : March 21, 2017
+// Changes Made : 1. Added pdiff_sync signal to syncrhonize pcount_diff
+// : to sli_refclk.
+// : 2. Updated terminal count logic for PCIe 5G
+// : 3. Modified checking of pcount_diff in SLL state
+// : machine to cover actual count
+// : (from 16-bits to 22-bits)
+// =============================================================================
+// REVISION HISTORY
+// Version : 1.6
+// Author(s) : ES
+// Mod. Date : April 19, 2017
+// Changes Made : 1. Added registered lock and unlock signal from
+// pdiff_sync to totally decouple pcount_diff from
+// SLL state machine.
+// : 2. Modified LPCLK_TC_4 to 1:1 clock ratio when CPRI
+// is operating @ 4.9125Gbps data rate.
+// =============================================================================
+`timescale 1ns/10ps
+
+module sgmii2sll_core (
+ //Reset and Clock inputs
+ sli_rst, //Active high asynchronous reset input
+ sli_refclk, //Refclk input to the Tx PLL
+ sli_pclk, //Tx pclk output from the PCS
+
+ //Control inputs
+ sli_div2_rate, //Divide by 2 control; 0 - Full rate; 1 - Half rate
+ sli_div11_rate, //Divide by 11 control; 0 - Full rate; 1 - Div by 11
+ sli_gear_mode, //Gear mode control for PCS; 0 - 8/10; 1- 16/20
+ sli_cpri_mode, //Mode of operation specific to CPRI protocol
+ sli_pcie_mode, //Mode of operation specific to PCIe mode (2.5G or 5G)
+
+ //LOL Output
+ slo_plol //Tx PLL Loss of Lock output to the user logic
+ );
+
+// Inputs
+input sli_rst;
+input sli_refclk;
+input sli_pclk;
+input sli_div2_rate;
+input sli_div11_rate;
+input sli_gear_mode;
+input [2:0] sli_cpri_mode;
+input sli_pcie_mode;
+
+// Outputs
+output slo_plol;
+
+
+// Parameters
+parameter PPROTOCOL = "PCIE"; //Protocol selected by the User
+parameter PLOL_SETTING = 0; //PLL LOL setting. Possible values are 0,1,2,3
+parameter PDYN_RATE_CTRL = "DISABLED"; //PCS Dynamic Rate control
+parameter PPCIE_MAX_RATE = "2.5"; //PCIe max data rate
+parameter PDIFF_VAL_LOCK = 20; //Differential count value for Lock
+parameter PDIFF_VAL_UNLOCK = 39; //Differential count value for Unlock
+parameter PPCLK_TC = 65535; //Terminal count value for counter running on sli_pclk
+parameter PDIFF_DIV11_VAL_LOCK = 3; //Differential count value for Lock for SDI Div11
+parameter PDIFF_DIV11_VAL_UNLOCK = 3; //Differential count value for Unlock for SDI Div11
+parameter PPCLK_DIV11_TC = 2383; //Terminal count value (SDI Div11) for counter running on sli_pclk
+
+
+// Local Parameters
+localparam [1:0] LPLL_LOSS_ST = 2'b00; //PLL Loss state
+localparam [1:0] LPLL_PRELOSS_ST = 2'b01; //PLL Pre-Loss state
+localparam [1:0] LPLL_PRELOCK_ST = 2'b10; //PLL Pre-Lock state
+localparam [1:0] LPLL_LOCK_ST = 2'b11; //PLL Lock state
+`ifdef RSL_SIM_MODE
+localparam [15:0] LRCLK_TC = 16'd63; //Terminal count value for counter running on sli_refclk
+`else
+localparam [15:0] LRCLK_TC = 16'd65535; //Terminal count value for counter running on sli_refclk
+`endif
+localparam [15:0] LRCLK_TC_PUL_WIDTH = 16'd50; //Pulse width for the Refclk terminal count pulse
+localparam [7:0] LHB_WAIT_CNT = 8'd255; //Wait count for the Heartbeat signal
+
+// Local Parameters related to the CPRI dynamic modes
+// Terminal count values for the four CPRI modes
+localparam LPCLK_TC_0 = 32768;
+localparam LPCLK_TC_1 = 65536;
+localparam LPCLK_TC_2 = 131072;
+localparam LPCLK_TC_3 = 163840;
+localparam LPCLK_TC_4 = 65536;
+
+// Lock values count values for the four CPRI modes and four PLOL settings (4x5)
+// CPRI rate mode 0 CPRI rate mode 1 CPRI rate mode 2 CPRI rate mode 3 CPRI rate mode 4
+localparam LPDIFF_LOCK_00 = 9; localparam LPDIFF_LOCK_10 = 19; localparam LPDIFF_LOCK_20 = 39; localparam LPDIFF_LOCK_30 = 49; localparam LPDIFF_LOCK_40 = 19;
+localparam LPDIFF_LOCK_01 = 9; localparam LPDIFF_LOCK_11 = 19; localparam LPDIFF_LOCK_21 = 39; localparam LPDIFF_LOCK_31 = 49; localparam LPDIFF_LOCK_41 = 19;
+localparam LPDIFF_LOCK_02 = 49; localparam LPDIFF_LOCK_12 = 98; localparam LPDIFF_LOCK_22 = 196; localparam LPDIFF_LOCK_32 = 245; localparam LPDIFF_LOCK_42 = 98;
+localparam LPDIFF_LOCK_03 = 131; localparam LPDIFF_LOCK_13 = 262; localparam LPDIFF_LOCK_23 = 524; localparam LPDIFF_LOCK_33 = 655; localparam LPDIFF_LOCK_43 = 262;
+
+// Unlock values count values for the four CPRI modes and four PLOL settings (4x5)
+// CPRI rate mode 0 CPRI rate mode 1 CPRI rate mode 2 CPRI rate mode 3 CPRI rate mode 4
+localparam LPDIFF_UNLOCK_00 = 19; localparam LPDIFF_UNLOCK_10 = 39; localparam LPDIFF_UNLOCK_20 = 78; localparam LPDIFF_UNLOCK_30 = 98; localparam LPDIFF_UNLOCK_40 = 39;
+localparam LPDIFF_UNLOCK_01 = 65; localparam LPDIFF_UNLOCK_11 = 131; localparam LPDIFF_UNLOCK_21 = 262; localparam LPDIFF_UNLOCK_31 = 327; localparam LPDIFF_UNLOCK_41 = 131;
+localparam LPDIFF_UNLOCK_02 = 72; localparam LPDIFF_UNLOCK_12 = 144; localparam LPDIFF_UNLOCK_22 = 288; localparam LPDIFF_UNLOCK_32 = 360; localparam LPDIFF_UNLOCK_42 = 144;
+localparam LPDIFF_UNLOCK_03 = 196; localparam LPDIFF_UNLOCK_13 = 393; localparam LPDIFF_UNLOCK_23 = 786; localparam LPDIFF_UNLOCK_33 = 983; localparam LPDIFF_UNLOCK_43 = 393;
+
+// Input and Output reg and wire declarations
+wire sli_rst;
+wire sli_refclk;
+wire sli_pclk;
+wire sli_div2_rate;
+wire sli_div11_rate;
+wire sli_gear_mode;
+wire [2:0] sli_cpri_mode;
+wire sli_pcie_mode;
+wire slo_plol;
+
+//-------------- Internal signals reg and wire declarations --------------------
+
+//Signals running on sli_refclk
+reg [15:0] rcount; //16-bit Counter
+reg rtc_pul; //Terminal count pulse
+reg rtc_pul_p1; //Terminal count pulse pipeline
+reg rtc_ctrl; //Terminal count pulse control
+
+reg [7:0] rhb_wait_cnt; //Heartbeat wait counter
+
+//Heatbeat synchronization and pipeline registers
+wire rhb_sync;
+reg rhb_sync_p2;
+reg rhb_sync_p1;
+
+//Pipeling registers for dynamic control mode
+wire rgear;
+wire rdiv2;
+wire rdiv11;
+reg rgear_p1;
+reg rdiv2_p1;
+reg rdiv11_p1;
+
+reg rstat_pclk; //Pclk presence/absence status
+
+reg [21:0] rcount_tc; //Tx_pclk terminal count register
+reg [15:0] rdiff_comp_lock; //Differential comparison value for Lock
+reg [15:0] rdiff_comp_unlock; //Differential compariosn value for Unlock
+
+wire rpcie_mode; //PCIe mode signal synchronized to refclk
+reg rpcie_mode_p1; //PCIe mode pipeline register
+
+wire rcpri_mod_ch_sync; //CPRI mode change synchronized to refclk
+reg rcpri_mod_ch_p1; //CPRI mode change pipeline register
+reg rcpri_mod_ch_p2; //CPRI mode change pipeline register
+reg rcpri_mod_ch_st; //CPRI mode change status
+
+reg [1:0] sll_state; //Current-state register for LOL FSM
+
+reg pll_lock; //PLL Lock signal
+
+//Signals running on sli_pclk
+//Synchronization and pipeline registers
+wire ppul_sync;
+reg ppul_sync_p1;
+reg ppul_sync_p2;
+reg ppul_sync_p3;
+
+wire pdiff_sync;
+reg pdiff_sync_p1;
+
+reg [21:0] pcount; //22-bit counter
+reg [21:0] pcount_diff; //Differential value between Tx_pclk counter and theoritical value
+
+//Heartbeat counter and heartbeat signal running on pclk
+reg [2:0] phb_cnt;
+reg phb;
+
+//CPRI dynamic mode releated signals
+reg [2:0] pcpri_mode;
+reg pcpri_mod_ch;
+
+//Assignment scheme changed mainly for simulation purpose
+wire [15:0] LRCLK_TC_w;
+assign LRCLK_TC_w = LRCLK_TC;
+
+reg unlock;
+reg lock;
+
+//Heartbeat synchronization
+sync # (.PDATA_RST_VAL(0)) phb_sync_inst (
+ .clk (sli_refclk),
+ .rst (sli_rst),
+ .data_in (phb),
+ .data_out(rhb_sync)
+ );
+
+
+//Terminal count pulse synchronization
+sync # (.PDATA_RST_VAL(0)) rtc_sync_inst (
+ .clk (sli_pclk),
+ .rst (sli_rst),
+ .data_in (rtc_pul),
+ .data_out(ppul_sync)
+ );
+
+//Differential value logic update synchronization
+sync # (.PDATA_RST_VAL(0)) pdiff_sync_inst (
+ .clk (sli_refclk),
+ .rst (sli_rst),
+ .data_in (ppul_sync),
+ .data_out(pdiff_sync)
+ );
+
+//Gear mode synchronization
+sync # (.PDATA_RST_VAL(0)) gear_sync_inst (
+ .clk (sli_refclk),
+ .rst (sli_rst),
+ .data_in (sli_gear_mode),
+ .data_out(rgear)
+ );
+
+//Div2 synchronization
+sync # (.PDATA_RST_VAL(0)) div2_sync_inst (
+ .clk (sli_refclk),
+ .rst (sli_rst),
+ .data_in (sli_div2_rate),
+ .data_out(rdiv2)
+ );
+
+//Div11 synchronization
+sync # (.PDATA_RST_VAL(0)) div11_sync_inst (
+ .clk (sli_refclk),
+ .rst (sli_rst),
+ .data_in (sli_div11_rate),
+ .data_out(rdiv11)
+ );
+
+//CPRI mode change synchronization
+sync # (.PDATA_RST_VAL(0)) cpri_mod_sync_inst (
+ .clk (sli_refclk),
+ .rst (sli_rst),
+ .data_in (pcpri_mod_ch),
+ .data_out(rcpri_mod_ch_sync)
+ );
+
+//PCIe mode change synchronization
+sync # (.PDATA_RST_VAL(0)) pcie_mod_sync_inst (
+ .clk (sli_refclk),
+ .rst (sli_rst),
+ .data_in (sli_pcie_mode),
+ .data_out(rpcie_mode)
+ );
+
+// =============================================================================
+// Synchronized Lock/Unlock signals
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+ if (sli_rst == 1'b1) begin
+ unlock <= 1'b0;
+ lock <= 1'b0;
+ pdiff_sync_p1 <= 1'b0;
+ end
+ else begin
+ pdiff_sync_p1 <= pdiff_sync;
+ if (unlock) begin
+ unlock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : unlock;
+ end
+ else begin
+ unlock <= pdiff_sync ? (pcount_diff[21:0] > {6'd0, rdiff_comp_unlock}) : 1'b0;
+ end
+ if (lock) begin
+ lock <= ~pdiff_sync && pdiff_sync_p1 ? 1'b0 : lock;
+ end
+ else begin
+ lock <= pdiff_sync ? (pcount_diff[21:0] <= {6'd0, rdiff_comp_lock}) : 1'b0;
+ end
+ end
+end
+
+// =============================================================================
+// Refclk Counter, pulse generation logic and Heartbeat monitor logic
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+ if (sli_rst == 1'b1) begin
+ rcount <= 16'd0;
+ rtc_pul <= 1'b0;
+ rtc_ctrl <= 1'b0;
+ rtc_pul_p1 <= 1'b0;
+ end
+ else begin
+ //Counter logic
+ if ((rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) || (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin
+ if (rtc_ctrl == 1'b1) begin
+ rcount <= LRCLK_TC_PUL_WIDTH;
+ end
+ end
+ else begin
+ if (rcount != LRCLK_TC_w) begin
+ rcount <= rcount + 1;
+ end
+ else begin
+ rcount <= 16'd0;
+ end
+ end
+
+ //Pulse control logic
+ if (rcount == LRCLK_TC_w - 1) begin
+ rtc_ctrl <= 1'b1;
+ end
+
+ //Pulse Generation logic
+ if (rtc_ctrl == 1'b1) begin
+ if ((rcount == LRCLK_TC_w) || (rcount < LRCLK_TC_PUL_WIDTH)) begin
+ rtc_pul <= 1'b1;
+ end
+ else begin
+ rtc_pul <= 1'b0;
+ end
+ end
+
+ rtc_pul_p1 <= rtc_pul;
+ end
+end
+
+
+// =============================================================================
+// Heartbeat synchronization & monitor logic and Dynamic mode pipeline logic
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+ if (sli_rst == 1'b1) begin
+ rhb_sync_p1 <= 1'b0;
+ rhb_sync_p2 <= 1'b0;
+ rhb_wait_cnt <= 8'd0;
+ rstat_pclk <= 1'b0;
+ rgear_p1 <= 1'b0;
+ rdiv2_p1 <= 1'b0;
+ rdiv11_p1 <= 1'b0;
+ rcpri_mod_ch_p1 <= 1'b0;
+ rcpri_mod_ch_p2 <= 1'b0;
+ rcpri_mod_ch_st <= 1'b0;
+ rpcie_mode_p1 <= 1'b0;
+
+ end
+ else begin
+ //Pipeline stages for the Heartbeat
+ rhb_sync_p1 <= rhb_sync;
+ rhb_sync_p2 <= rhb_sync_p1;
+
+ //Pipeline stages of the Dynamic rate control signals
+ rgear_p1 <= rgear;
+ rdiv2_p1 <= rdiv2;
+ rdiv11_p1 <= rdiv11;
+
+ //Pipeline stage for PCIe mode
+ rpcie_mode_p1 <= rpcie_mode;
+
+ //Pipeline stage for CPRI mode change
+ rcpri_mod_ch_p1 <= rcpri_mod_ch_sync;
+ rcpri_mod_ch_p2 <= rcpri_mod_ch_p1;
+
+ //CPRI mode change status logic
+ if (rcpri_mod_ch_p1^rcpri_mod_ch_sync == 1'b1) begin
+ rcpri_mod_ch_st <= 1'b1;
+ end
+
+ //Heartbeat wait counter and monitor logic
+ if (rtc_ctrl == 1'b1) begin
+ if (rhb_sync_p1 == 1'b1 && rhb_sync_p2 == 1'b0) begin
+ rhb_wait_cnt <= 8'd0;
+ rstat_pclk <= 1'b1;
+ end
+ else if (rhb_wait_cnt == LHB_WAIT_CNT) begin
+ rhb_wait_cnt <= 8'd0;
+ rstat_pclk <= 1'b0;
+ end
+ else begin
+ rhb_wait_cnt <= rhb_wait_cnt + 1;
+ end
+ end
+ end
+end
+
+
+// =============================================================================
+// Pipleline registers for the TC pulse and CPRI mode change logic
+// =============================================================================
+always @(posedge sli_pclk or posedge sli_rst) begin
+ if (sli_rst == 1'b1) begin
+ ppul_sync_p1 <= 1'b0;
+ ppul_sync_p2 <= 1'b0;
+ ppul_sync_p3 <= 1'b0;
+ pcpri_mode <= 3'b0;
+ pcpri_mod_ch <= 1'b0;
+ end
+ else begin
+ ppul_sync_p1 <= ppul_sync;
+ ppul_sync_p2 <= ppul_sync_p1;
+ ppul_sync_p3 <= ppul_sync_p2;
+
+ //CPRI mode change logic
+ pcpri_mode <= sli_cpri_mode;
+
+ if (pcpri_mode != sli_cpri_mode) begin
+ pcpri_mod_ch <= ~pcpri_mod_ch;
+ end
+ end
+end
+
+
+// =============================================================================
+// Terminal count logic
+// =============================================================================
+
+//For SDI protocol with Dynamic rate control enabled
+generate
+if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "SDI")) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+ if (sli_rst == 1'b1) begin
+ rcount_tc <= 22'd0;
+ rdiff_comp_lock <= 16'd0;
+ rdiff_comp_unlock <= 16'd0;
+ end
+ else begin
+ //Terminal count logic
+ //Div by 11 is enabled
+ if (rdiv11 == 1'b1) begin
+ //Gear mode is 16/20
+ if (rgear == 1'b1) begin
+ rcount_tc <= PPCLK_DIV11_TC;
+ rdiff_comp_lock <= PDIFF_DIV11_VAL_LOCK;
+ rdiff_comp_unlock <= PDIFF_DIV11_VAL_UNLOCK;
+ end
+ else begin
+ rcount_tc <= {PPCLK_DIV11_TC[20:0], 1'b0};
+ rdiff_comp_lock <= {PDIFF_DIV11_VAL_LOCK[14:0], 1'b0};
+ rdiff_comp_unlock <= {PDIFF_DIV11_VAL_UNLOCK[14:0], 1'b0};
+ end
+ end
+ //Div by 2 is enabled
+ else if (rdiv2 == 1'b1) begin
+ //Gear mode is 16/20
+ if (rgear == 1'b1) begin
+ rcount_tc <= {1'b0,PPCLK_TC[21:1]};
+ rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]};
+ rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]};
+ end
+ else begin
+ rcount_tc <= PPCLK_TC;
+ rdiff_comp_lock <= PDIFF_VAL_LOCK;
+ rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+ end
+ end
+ //Both div by 11 and div by 2 are disabled
+ else begin
+ //Gear mode is 16/20
+ if (rgear == 1'b1) begin
+ rcount_tc <= PPCLK_TC;
+ rdiff_comp_lock <= PDIFF_VAL_LOCK;
+ rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+ end
+ else begin
+ rcount_tc <= {PPCLK_TC[20:0],1'b0};
+ rdiff_comp_lock <= {PDIFF_VAL_LOCK[14:0],1'b0};
+ rdiff_comp_unlock <= {PDIFF_VAL_UNLOCK[14:0],1'b0};
+ end
+ end
+ end
+end
+end
+endgenerate
+
+//For G8B10B protocol with Dynamic rate control enabled
+generate
+if ((PDYN_RATE_CTRL == "ENABLED") && (PPROTOCOL == "G8B10B")) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+ if (sli_rst == 1'b1) begin
+ rcount_tc <= 22'd0;
+ rdiff_comp_lock <= 16'd0;
+ rdiff_comp_unlock <= 16'd0;
+ end
+ else begin
+ //Terminal count logic
+ //Div by 2 is enabled
+ if (rdiv2 == 1'b1) begin
+ rcount_tc <= {1'b0,PPCLK_TC[21:1]};
+ rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]};
+ rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]};
+ end
+ else begin
+ rcount_tc <= PPCLK_TC;
+ rdiff_comp_lock <= PDIFF_VAL_LOCK;
+ rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+ end
+ end
+end
+end
+endgenerate
+
+
+//For CPRI protocol with Dynamic rate control is disabled
+generate
+if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "CPRI")) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+ if (sli_rst == 1'b1) begin
+ rcount_tc <= 22'd0;
+ rdiff_comp_lock <= 16'd0;
+ rdiff_comp_unlock <= 16'd0;
+ end
+ else begin
+ //Terminal count logic for CPRI protocol
+ //Only if there is a change in the rate mode from the default
+ if (rcpri_mod_ch_st == 1'b1) begin
+ if (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) begin
+ case(sli_cpri_mode)
+ 3'd0 : begin //For 0.6Gbps
+ rcount_tc <= LPCLK_TC_0;
+ case(PLOL_SETTING)
+ 'd0 : begin
+ rdiff_comp_lock <= LPDIFF_LOCK_00;
+ rdiff_comp_unlock <= LPDIFF_UNLOCK_00;
+ end
+
+ 'd1 : begin
+ rdiff_comp_lock <= LPDIFF_LOCK_01;
+ rdiff_comp_unlock <= LPDIFF_UNLOCK_01;
+ end
+
+ 'd2 : begin
+ rdiff_comp_lock <= LPDIFF_LOCK_02;
+ rdiff_comp_unlock <= LPDIFF_UNLOCK_02;
+ end
+
+ 'd3 : begin
+ rdiff_comp_lock <= LPDIFF_LOCK_03;
+ rdiff_comp_unlock <= LPDIFF_UNLOCK_03;
+ end
+
+ default : begin
+ rdiff_comp_lock <= LPDIFF_LOCK_00;
+ rdiff_comp_unlock <= LPDIFF_UNLOCK_00;
+ end
+ endcase
+ end
+
+ 3'd1 : begin //For 1.2Gbps
+ rcount_tc <= LPCLK_TC_1;
+ case(PLOL_SETTING)
+ 'd0 : begin
+ rdiff_comp_lock <= LPDIFF_LOCK_10;
+ rdiff_comp_unlock <= LPDIFF_UNLOCK_10;
+ end
+
+ 'd1 : begin
+ rdiff_comp_lock <= LPDIFF_LOCK_11;
+ rdiff_comp_unlock <= LPDIFF_UNLOCK_11;
+ end
+
+ 'd2 : begin
+ rdiff_comp_lock <= LPDIFF_LOCK_12;
+ rdiff_comp_unlock <= LPDIFF_UNLOCK_12;
+ end
+
+ 'd3 : begin
+ rdiff_comp_lock <= LPDIFF_LOCK_13;
+ rdiff_comp_unlock <= LPDIFF_UNLOCK_13;
+ end
+
+ default : begin
+ rdiff_comp_lock <= LPDIFF_LOCK_10;
+ rdiff_comp_unlock <= LPDIFF_UNLOCK_10;
+ end
+ endcase
+ end
+
+ 3'd2 : begin //For 2.4Gbps
+ rcount_tc <= LPCLK_TC_2;
+ case(PLOL_SETTING)
+ 'd0 : begin
+ rdiff_comp_lock <= LPDIFF_LOCK_20;
+ rdiff_comp_unlock <= LPDIFF_UNLOCK_20;
+ end
+
+ 'd1 : begin
+ rdiff_comp_lock <= LPDIFF_LOCK_21;
+ rdiff_comp_unlock <= LPDIFF_UNLOCK_21;
+ end
+
+ 'd2 : begin
+ rdiff_comp_lock <= LPDIFF_LOCK_22;
+ rdiff_comp_unlock <= LPDIFF_UNLOCK_22;
+ end
+
+ 'd3 : begin
+ rdiff_comp_lock <= LPDIFF_LOCK_23;
+ rdiff_comp_unlock <= LPDIFF_UNLOCK_23;
+ end
+
+ default : begin
+ rdiff_comp_lock <= LPDIFF_LOCK_20;
+ rdiff_comp_unlock <= LPDIFF_UNLOCK_20;
+ end
+ endcase
+ end
+
+ 3'd3 : begin //For 3.07Gbps
+ rcount_tc <= LPCLK_TC_3;
+ case(PLOL_SETTING)
+ 'd0 : begin
+ rdiff_comp_lock <= LPDIFF_LOCK_30;
+ rdiff_comp_unlock <= LPDIFF_UNLOCK_30;
+ end
+
+ 'd1 : begin
+ rdiff_comp_lock <= LPDIFF_LOCK_31;
+ rdiff_comp_unlock <= LPDIFF_UNLOCK_31;
+ end
+
+ 'd2 : begin
+ rdiff_comp_lock <= LPDIFF_LOCK_32;
+ rdiff_comp_unlock <= LPDIFF_UNLOCK_32;
+ end
+
+ 'd3 : begin
+ rdiff_comp_lock <= LPDIFF_LOCK_33;
+ rdiff_comp_unlock <= LPDIFF_UNLOCK_33;
+ end
+ endcase
+ end
+
+ 3'd4 : begin //For 4.9125bps
+ rcount_tc <= LPCLK_TC_4;
+ case(PLOL_SETTING)
+ 'd0 : begin
+ rdiff_comp_lock <= LPDIFF_LOCK_40;
+ rdiff_comp_unlock <= LPDIFF_UNLOCK_40;
+ end
+
+ 'd1 : begin
+ rdiff_comp_lock <= LPDIFF_LOCK_41;
+ rdiff_comp_unlock <= LPDIFF_UNLOCK_41;
+ end
+
+ 'd2 : begin
+ rdiff_comp_lock <= LPDIFF_LOCK_42;
+ rdiff_comp_unlock <= LPDIFF_UNLOCK_42;
+ end
+
+ 'd3 : begin
+ rdiff_comp_lock <= LPDIFF_LOCK_43;
+ rdiff_comp_unlock <= LPDIFF_UNLOCK_43;
+ end
+
+ default : begin
+ rdiff_comp_lock <= LPDIFF_LOCK_40;
+ rdiff_comp_unlock <= LPDIFF_UNLOCK_40;
+ end
+ endcase
+ end
+
+ default : begin
+ rcount_tc <= LPCLK_TC_0;
+ rdiff_comp_lock <= LPDIFF_LOCK_00;
+ rdiff_comp_unlock <= LPDIFF_UNLOCK_00;
+ end
+ endcase
+ end
+ end
+ else begin
+ //If there is no change in the CPRI rate mode from default
+ rcount_tc <= PPCLK_TC;
+ rdiff_comp_lock <= PDIFF_VAL_LOCK;
+ rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+ end
+ end
+end
+end
+endgenerate
+
+//For PCIe protocol with Dynamic rate control disabled
+generate
+if ((PDYN_RATE_CTRL == "DISABLED") && (PPROTOCOL == "PCIE")) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+ if (sli_rst == 1'b1) begin
+ rcount_tc <= 22'd0;
+ rdiff_comp_lock <= 16'd0;
+ rdiff_comp_unlock <= 16'd0;
+ end
+ else begin
+ //Terminal count logic
+ if (PPCIE_MAX_RATE == "2.5") begin
+ //2.5G mode is enabled
+ rcount_tc <= PPCLK_TC;
+ rdiff_comp_lock <= PDIFF_VAL_LOCK;
+ rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+ end
+ else begin
+ //5G mode is enabled
+ if (rpcie_mode == 1'b1) begin
+ rcount_tc <= PPCLK_TC;
+ rdiff_comp_lock <= PDIFF_VAL_LOCK;
+ rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+ end
+ else begin
+ //2.5G mode is enabled
+ rcount_tc <= {1'b0,PPCLK_TC[21:1]};
+ rdiff_comp_lock <= {1'b0,PDIFF_VAL_LOCK[15:1]};
+ rdiff_comp_unlock <= {1'b0,PDIFF_VAL_UNLOCK[15:1]};
+ end
+ end
+ end
+end
+end
+endgenerate
+
+//For all protocols other than CPRI & PCIe
+generate
+if ((PDYN_RATE_CTRL == "DISABLED") && ((PPROTOCOL != "CPRI") && (PPROTOCOL != "PCIE"))) begin
+always @(posedge sli_refclk or posedge sli_rst) begin
+ if (sli_rst == 1'b1) begin
+ rcount_tc <= 22'd0;
+ rdiff_comp_lock <= 16'd0;
+ rdiff_comp_unlock <= 16'd0;
+ end
+ else begin
+ //Terminal count logic for all protocols other than CPRI & PCIe
+ rcount_tc <= PPCLK_TC;
+ rdiff_comp_lock <= PDIFF_VAL_LOCK;
+ rdiff_comp_unlock <= PDIFF_VAL_UNLOCK;
+ end
+end
+end
+endgenerate
+
+
+// =============================================================================
+// Tx_pclk counter, Heartbeat and Differential value logic
+// =============================================================================
+always @(posedge sli_pclk or posedge sli_rst) begin
+ if (sli_rst == 1'b1) begin
+ pcount <= 22'd0;
+ pcount_diff <= 22'd65535;
+ phb_cnt <= 3'd0;
+ phb <= 1'b0;
+ end
+ else begin
+ //Counter logic
+ if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin
+ pcount <= 22'd0;
+ end
+ else begin
+ pcount <= pcount + 1;
+ end
+
+ //Heartbeat logic
+ phb_cnt <= phb_cnt + 1;
+
+ if ((phb_cnt < 3'd4) && (phb_cnt >= 3'd0)) begin
+ phb <= 1'b1;
+ end
+ else begin
+ phb <= 1'b0;
+ end
+
+ //Differential value logic
+ if (ppul_sync_p1 == 1'b1 && ppul_sync_p2 == 1'b0) begin
+ pcount_diff <= rcount_tc + ~(pcount) + 1;
+ end
+ else if (ppul_sync_p2 == 1'b1 && ppul_sync_p3 == 1'b0) begin
+ if (pcount_diff[21] == 1'b1) begin
+ pcount_diff <= ~(pcount_diff) + 1;
+ end
+ end
+ end
+end
+
+
+// =============================================================================
+// State transition logic for SLL FSM
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+ if (sli_rst == 1'b1) begin
+ sll_state <= LPLL_LOSS_ST;
+ end
+ else begin
+ //Reasons to declare an immediate loss - Absence of Tx_pclk, Dynamic rate change for SDI or CPRI
+ if ((rstat_pclk == 1'b0) || (rgear_p1^rgear == 1'b1) || (rdiv2_p1^rdiv2 == 1'b1) ||
+ (rdiv11_p1^rdiv11 == 1'b1) || (rcpri_mod_ch_p1^rcpri_mod_ch_p2 == 1'b1) || (rpcie_mode_p1^rpcie_mode == 1'b1)) begin
+ sll_state <= LPLL_LOSS_ST;
+ end
+ else begin
+ case(sll_state)
+ LPLL_LOSS_ST : begin
+ if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
+ if (unlock) begin
+ sll_state <= LPLL_LOSS_ST;
+ end
+ else if (lock) begin
+ if (PLOL_SETTING == 2'd0) begin
+ sll_state <= LPLL_PRELOCK_ST;
+ end
+ else begin
+ sll_state <= LPLL_LOCK_ST;
+ end
+ end
+ end
+ end
+
+ LPLL_LOCK_ST : begin
+ if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
+ if (lock) begin
+ sll_state <= LPLL_LOCK_ST;
+ end
+ else begin
+ if (PLOL_SETTING == 2'd0) begin
+ sll_state <= LPLL_LOSS_ST;
+ end
+ else begin
+ sll_state <= LPLL_PRELOSS_ST;
+ end
+ end
+ end
+ end
+
+ LPLL_PRELOCK_ST : begin
+ if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
+ if (lock) begin
+ sll_state <= LPLL_LOCK_ST;
+ end
+ else begin
+ sll_state <= LPLL_PRELOSS_ST;
+ end
+ end
+ end
+
+ LPLL_PRELOSS_ST : begin
+ if (rtc_pul_p1 == 1'b1 && rtc_pul == 1'b0) begin
+ if (unlock) begin
+ sll_state <= LPLL_PRELOSS_ST;
+ end
+ else if (lock) begin
+ sll_state <= LPLL_LOCK_ST;
+ end
+ end
+ end
+
+ default: begin
+ sll_state <= LPLL_LOSS_ST;
+ end
+ endcase
+ end
+ end
+end
+
+
+// =============================================================================
+// Logic for Tx PLL Lock
+// =============================================================================
+always @(posedge sli_refclk or posedge sli_rst) begin
+ if (sli_rst == 1'b1) begin
+ pll_lock <= 1'b0;
+ end
+ else begin
+ case(sll_state)
+ LPLL_LOSS_ST : begin
+ pll_lock <= 1'b0;
+ end
+
+ LPLL_LOCK_ST : begin
+ pll_lock <= 1'b1;
+ end
+
+ LPLL_PRELOSS_ST : begin
+ pll_lock <= 1'b0;
+ end
+
+ default: begin
+ pll_lock <= 1'b0;
+ end
+ endcase
+ end
+end
+
+assign slo_plol = ~(pll_lock);
+
+endmodule
+
+
+// ===========================================================================
+// >>>>>>>>>>>>>>>>>>>>>>> COPYRIGHT NOTICE <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
+// ---------------------------------------------------------------------------
+// Copyright (c) 2015 by Lattice Semiconductor Corporation
+// ALL RIGHTS RESERVED
+// ------------------------------------------------------------------
+//
+// Permission:
+//
+// Lattice SG Pte. Ltd. grants permission to use this code
+// pursuant to the terms of the Lattice Reference Design License Agreement.
+//
+//
+// Disclaimer:
+//
+// This VHDL or Verilog source code is intended as a design reference
+// which illustrates how these types of functions can be implemented.
+// It is the user's responsibility to verify their design for
+// consistency and functionality through the use of formal
+// verification methods. Lattice provides no warranty
+// regarding the use or functionality of this code.
+//
+// ---------------------------------------------------------------------------
+//
+// Lattice SG Pte. Ltd.
+// 101 Thomson Road, United Square #07-02
+// Singapore 307591
+//
+//
+// TEL: 1-800-Lattice (USA and Canada)
+// +65-6631-2000 (Singapore)
+// +1-503-268-8001 (other locations)
+//
+// web: http://www.latticesemi.com/
+// email: techsupport@latticesemi.com
+//
+// ---------------------------------------------------------------------------
+//
+// =============================================================================
+// FILE DETAILS
+// Project : Synchronizer Logic
+// File : sync.v
+// Title : Synchronizer module
+// Description :
+// =============================================================================
+// REVISION HISTORY
+// Version : 1.0
+// Author(s) : AV
+// Mod. Date : July 7, 2015
+// Changes Made : Initial Creation
+// -----------------------------------------------------------------------------
+// Version : 1.1
+// Author(s) : EB
+// Mod. Date : March 21, 2017
+// Changes Made :
+// =============================================================================
+
+`ifndef PCS_SYNC_MODULE
+`define PCS_SYNC_MODULE
+module sync (
+ clk,
+ rst,
+ data_in,
+ data_out
+ );
+
+input clk; //Clock in which the async data needs to be synchronized to
+input rst; //Active high reset
+input data_in; //Asynchronous data
+output data_out; //Synchronized data
+
+parameter PDATA_RST_VAL = 0; //Reset value for the registers
+
+reg data_p1;
+reg data_p2;
+
+// =============================================================================
+// Synchronization logic
+// =============================================================================
+always @(posedge clk or posedge rst) begin
+ if (rst == 1'b1) begin
+ data_p1 <= PDATA_RST_VAL;
+ data_p2 <= PDATA_RST_VAL;
+ end
+ else begin
+ data_p1 <= data_in;
+ data_p2 <= data_p1;
+ end
+end
+
+assign data_out = data_p2;
+
+endmodule
+`endif
+
generated by cgit v1.2.3-8-gadcc (git 2.29.0) at 2024-04-28 04:02:42 +0000

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