diff options
Diffstat (limited to 'clarity/pcs/sgmii0/sgmii0.lpc')
| -rw-r--r-- | clarity/pcs/sgmii0/sgmii0.lpc | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/clarity/pcs/sgmii0/sgmii0.lpc b/clarity/pcs/sgmii0/sgmii0.lpc index 0aea3d2..5c06b05 100644 --- a/clarity/pcs/sgmii0/sgmii0.lpc +++ b/clarity/pcs/sgmii0/sgmii0.lpc @@ -11,11 +11,11 @@ CoreName=PCS CoreRevision=8.2 CoreStatus=Demo CoreType=LPM -Date=02/08/2019 +Date=03/21/2020 ModuleName=sgmii0 ParameterFileVersion=1.0 SourceFormat=verilog -Time=18:42:05 +Time=21:48:39 VendorName=Lattice Semiconductor Corporation [Parameters] ;ACHARA=0 00H @@ -25,8 +25,8 @@ VendorName=Lattice Semiconductor Corporation CDRLOLACTION=Full Recalibration CDRLOLRANGE=0 CDR_MAX_RATE=1.25 -CDR_MULT=25X -CDR_REF_RATE=50.0000 +CDR_MULT=10X +CDR_REF_RATE=125.0000 CH_MODE=Rx and Tx Destination=Synplicity EDIF=1 @@ -44,7 +44,7 @@ PROTOCOL=GbE PWAIT_RX_RDY=3000 PWAIT_TX_RDY=3000 RCSRC=Disabled -REFCLK_RATE=50.0000 +REFCLK_RATE=125.0000 RSTSEQSEL=Disabled RX8B10B=Enabled RXCOMMAA=1010000011 @@ -80,7 +80,7 @@ TXFIFO_ENABLE=Enabled TXINVPOL=Invert TXLDR=Off TXPLLLOLTHRESHOLD=0 -TXPLLMULT=25X +TXPLLMULT=10X TX_DATA_WIDTH=8/10-Bit TX_FICLK_RATE=125.0000 TX_LINE_RATE=1.2500 |