initial commit, all basic functions work on Darsena V02

1 files changed, 110 insertions, 0 deletions

diff --git a/source/sync_fifo.v b/source/sync_fifo.v
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+++ b/source/sync_fifo.v
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+/*
+ *       sync_fifo.v
+ *
+ *   Copyright (C) 2018, 2019 Mind Chasers Inc.
+ *
+ *   Licensed under the Apache License, Version 2.0 (the "License");
+ *   you may not use this file except in compliance with the License.
+ *   You may obtain a copy of the License at
+ *
+ *       http://www.apache.org/licenses/LICENSE-2.0
+ *
+ *   Unless required by applicable law or agreed to in writing, software
+ *   distributed under the License is distributed on an "AS IS" BASIS,
+ *   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ *   See the License for the specific language governing permissions and
+ *   limitations under the License.
+ *
+ *	function: FIFO / data store between RX and TX for each path
+ *
+ */
+
+`timescale 1ns /10ps
+
+module	sync_fifo	#(parameter	FIFO_PTR = 11,
+					FIFO_WIDTH = 9,
+					FIFO_DEPTH = 2048 )
+(
+	input	rstn,
+	input	clk,
+	
+
+	// input
+	input	we,
+	input	[FIFO_WIDTH-1:0]	d_in,
+
+	// output
+	input 	re,
+	output	[FIFO_WIDTH-1:0]	d_out,		
+	output	empty,
+	output almost_full,
+	
+	// fifo_control
+	input reset_ptrs,
+	
+	// debug
+	output active
+
+);
+	
+`include "ethernet_params.v"
+
+reg	[FIFO_PTR-1:0] 	wr_ptr;
+reg	[FIFO_PTR-1:0] 	rd_ptr;
+reg [FIFO_PTR-1:0] wr_bytes_available;			// use for size calculation below
+
+
+always @(posedge clk, negedge rstn)
+	if( !rstn )
+		wr_ptr <= 'd0;
+	else if ( reset_ptrs )
+		wr_ptr <= 'd0;
+	else if ( we )
+		wr_ptr <= wr_ptr + 1;
+		
+/* 
+ * 	rd_ptr
+ * 	use empty flat to make sure rd_ptr doesn't advance when empty ( error condition )
+ */
+always @(posedge clk, negedge rstn)
+	if( !rstn )
+		rd_ptr <= 'd0;
+	else if ( reset_ptrs )
+		rd_ptr <= 'd0;
+	else if ( re && !empty )
+		rd_ptr <= rd_ptr + 1;
+
+assign empty = ( rd_ptr == wr_ptr ) ? 1'b1 : 1'b0;
+assign almost_full = wr_bytes_available < MTU ? 1'b1 : 1'b0;
+
+always @(posedge clk, negedge rstn)
+	if( !rstn )
+		wr_bytes_available <= FIFO_DEPTH-1;
+	else if ( wr_ptr >= rd_ptr )
+		wr_bytes_available <= FIFO_DEPTH-1 - (wr_ptr - rd_ptr);
+	else
+		wr_bytes_available <= rd_ptr - wr_ptr;
+	
+assign active = ~empty;
+		
+
+dpram dpram_fifo(
+	.rstn(  rstn  ),
+	.a_clk( clk ),
+	.a_clk_e( 1'b1 ),
+	.a_we( we ),
+	.a_oe( 1'b0 ),
+	.a_addr( wr_ptr ),
+	.a_din( d_in ),
+	.a_dout( ),
+	// port B
+	.b_clk(  clk ),
+	.b_clk_e( re ),
+	.b_we( 1'b0 ),
+	.b_oe( re  ),
+	.b_addr( rd_ptr ),
+	.b_din( 9'h0 ),
+	.b_dout( d_out )
+);
+
+endmodule