diff options
| author | mindchasers <privateisland@mindchasers.com> | 2020-11-19 22:26:59 -0500 |
|---|---|---|
| committer | mindchasers <privateisland@mindchasers.com> | 2020-11-19 22:26:59 -0500 |
| commit | f5ad249daef5d214e9dfcf2a8111f7ccdb00a6ef (patch) | |
| tree | 4d8d223c5eb573f03585f35867847b364f86feed /manufacturer/lattice/ecp5um/boards | |
| parent | 0b2b931a6324c03b9a38fb4926cb7e64e6ebf6f2 (diff) | |
lattice: clean up project files to match latest top
Diffstat (limited to 'manufacturer/lattice/ecp5um/boards')
| -rw-r--r-- | manufacturer/lattice/ecp5um/boards/darsena/darsena_v02.lpf | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/manufacturer/lattice/ecp5um/boards/darsena/darsena_v02.lpf b/manufacturer/lattice/ecp5um/boards/darsena/darsena_v02.lpf index 98c999b..3633976 100644 --- a/manufacturer/lattice/ecp5um/boards/darsena/darsena_v02.lpf +++ b/manufacturer/lattice/ecp5um/boards/darsena/darsena_v02.lpf @@ -24,10 +24,10 @@ BANK 8 VCCIO 3.3 V; LOCATE COMP "rstn" SITE "F1" ;// GSRN ping LOCATE COMP "i2c_scl" SITE "B1" ; LOCATE COMP "i2c_sda" SITE "C1" ; -LOCATE COMP "fpga_spics" SITE "H1" ; -LOCATE COMP "fpga_mclk" SITE "H2" ; -LOCATE COMP "fpga_mosi" SITE "G1" ; -LOCATE COMP "fpga_miso" SITE "F2" ; +LOCATE COMP "spi_cs" SITE "H1" ; +LOCATE COMP "spi_clk" SITE "H2" ; +LOCATE COMP "spi_mosi" SITE "G1" ; +LOCATE COMP "spi_miso" SITE "F2" ; LOCATE COMP "fpga_int" SITE "E2" ; LOCATE COMP "uart_txd" SITE "D2" ; LOCATE COMP "uart_rxd" SITE "E1" ; @@ -121,7 +121,7 @@ IOBUF PORT "ard_txd1" IO_TYPE=LVCMOS33 ; IOBUF PORT "ard_txd2" IO_TYPE=LVCMOS33 ; IOBUF PORT "ard_txd3" IO_TYPE=LVCMOS33 ; IOBUF PORT "phy_mdc" IO_TYPE=LVCMOS33 ; -IOBUF PORT "fpga_miso" IO_TYPE=LVCMOS33 PULLMODE=NONE ; +IOBUF PORT "spi_miso" IO_TYPE=LVCMOS33 PULLMODE=NONE ; IOBUF PORT "pe0" IO_TYPE=LVCMOS33 ; IOBUF PORT "pe1" IO_TYPE=LVCMOS33 ; IOBUF PORT "pe3" IO_TYPE=LVCMOS33 ; @@ -149,6 +149,6 @@ IOBUF PORT "fpga_jtag_e" IO_TYPE=LVCMOS33 ; IOBUF PORT "fpga_gpio" IO_TYPE=LVCMOS33 ; IOBUF PORT "phy1_intn" IO_TYPE=LVCMOS33 ; IOBUF PORT "phy0_intn" IO_TYPE=LVCMOS33 ; -IOBUF PORT "fpga_mclk" IO_TYPE=LVCMOS33 ; -IOBUF PORT "fpga_spics" IO_TYPE=LVCMOS33 ; -IOBUF PORT "fpga_mosi" IO_TYPE=LVCMOS33 ; +IOBUF PORT "spi_clk" IO_TYPE=LVCMOS33 ; +IOBUF PORT "spi_cs" IO_TYPE=LVCMOS33 ; +IOBUF PORT "spi_mosi" IO_TYPE=LVCMOS33 ; |
