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authormindchasers <privateisland@mindchasers.com>2020-09-27 20:54:08 -0400
committermindchasers <privateisland@mindchasers.com>2020-09-27 20:54:08 -0400
commit1c7478194daae4be777a21552295133a735082cb (patch)
treee55d68f643b4b5ab375fe3942728dc931c8ef1ad /clarity/pcs/refclk0
parentbbe7e48ee202c2e1075ea6a69733d030b8bf3ddf (diff)
clarity: update SERDES/PCS block to be compatible with Diamond 3.11
Diffstat (limited to 'clarity/pcs/refclk0')
-rw-r--r--clarity/pcs/refclk0/refclk0.lpc4
-rw-r--r--clarity/pcs/refclk0/refclk0.v2
2 files changed, 3 insertions, 3 deletions
diff --git a/clarity/pcs/refclk0/refclk0.lpc b/clarity/pcs/refclk0/refclk0.lpc
index 4e2184e..1894b2d 100644
--- a/clarity/pcs/refclk0/refclk0.lpc
+++ b/clarity/pcs/refclk0/refclk0.lpc
@@ -11,11 +11,11 @@ CoreName=EXTREF
CoreRevision=1.1
CoreStatus=Demo
CoreType=LPM
-Date=10/17/2017
+Date=03/06/2020
ModuleName=refclk0
ParameterFileVersion=1.0
SourceFormat=verilog
-Time=18:21:09
+Time=20:20:44
VendorName=Lattice Semiconductor Corporation
[Parameters]
Destination=Synplicity
diff --git a/clarity/pcs/refclk0/refclk0.v b/clarity/pcs/refclk0/refclk0.v
index 7fe46e2..edeb81f 100644
--- a/clarity/pcs/refclk0/refclk0.v
+++ b/clarity/pcs/refclk0/refclk0.v
@@ -1,5 +1,5 @@
// Verilog netlist produced by program ASBGen: Ports rev. 2.30, Attr. rev. 2.65
-// Netlist written on Tue Oct 17 18:22:54 2017
+// Netlist written on Fri Mar 06 20:20:57 2020
//
// Verilog Description of module refclk0
//

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