Mind Chasers Inc.
Mind Chasers Inc.

Private Island External Register and Memory Interface

Documentation of FPGA'S memory and register interface

Overview

The FPGA architecture relies on an external micro controller (µC) for supervisory functions and provides it access to the FPGA's internal Ethernet switch for network functions. The FPGA has its own internal controller module that interfaces with the external µC via the I2C bus, and the supported command and data sequences are described below.

The FPGA also provides access to the µC of various memory blocks within the FPGA (e.g, Ethernet MAC TX and RX DPRAMs for accessing the Ethernet switch) via SPI Accesses. This protocol and the memory map are described in the following article: SPI Basics and Protocol for FPGA Open Source Network Processor.

I2C data transfer

The figure below depicts the write and read protocol between the µC and the FPGA. The FPGA module that implements the I2C driver interface is i2c.v. The µC is always the master and initiates each transfer. The FPGA internally counts bits, which are shown as numbers in the figure (8, 17, and 26).

It is provisioned that the FPGA can respond to multiple I2C device addresses (targets inside the FPGA). However, at the time of this writing, only a controller command set is implemented.

I2C writes are a sequence of device address, controller command, followed by one or more bytes. The actual number of bytes written depends on the command being sent. An I2C read cycle can follow a write if the FPGA responded to the I2C write by writing response data to the internal FIFO, which is read out during an I2C read. All accesses are terminated according to the I2C protocol (STOP).

I2C Data Transfer Protocol

I2C Commands and Register Definitions

Notes:

  • Some register writes initiate an MDIO controller sequence and are marked as mdio_cmd below.
  • Other register writes initiate an immediate controller response and are marked as cont_cmd below.
  • Other writes simply set write-only registers.
  • Four Ethernet ports are provisioned and specified in the following order during writes and reads: PHY[3], PHY[2], PHY[1], PHY[0].

c : Set DCU Channel Resets

Configures PCS block reset bits as shown in the table below. Each channel maps to a PHY or expansion port:

  • DCU0[0] maps to PHY0
  • DCU0[1] maps to PHY1
  • DCU1[0] maps to PHY2/EXP2
  • DCU1[1] maps to PHY3/EXP3
D2 D1 D0
tx_pcs_rst rx_serdes_rst rx_pcs_rst

notes:

  • Default is all resets asserted.

Example Usage: Assert all resets for PHY0 and PHY1, c0077

d : Dump Page

Dumps out 11 registers at specified page

notes:

  • mdio cmd
  • mdio_routine_addr: 25
  • Specify page with 5 hex bits

Example Usage: dump page 16, d10

l : Link Status

Returns: port_up[2:0]

notes:

  • cont_cmd
  • No data follows command

i : Init Selected PHY

Initialize selected PHY

Returns: Mode Register 0x7 for RGMII (Page 18, Register 20), Mode Register 0x1 for SGMII (Page 18, Register 20)

notes:

  • mdio cmd
  • mdio_routine_addr: 0
  • No data follows the command

j : Specify FPGA JTAG Configuration

j JTAG Enable µC UART Routing
0 0: FPGA JTAG is isolated from FT2232 µC UART is routed to FT2232
1 z (default): FPGA JTAG is routed to FT2232 µC UART is routed to Expansion Header

m : set mdio_mux_sel

Steers MDIO and LEDs

notes:

  • lower two bits of nibble to select one of the three PHYs.

Example Usage: Select PHY2 for MDIO activity, m2

p : get PCS status

Returns four bytes:

15:6 5:4 3:0
0 pll_lol[1:0] rx_error[3:0]

notes:

  • cont_cmd
  • rx_error is an FPGA combinatorial function of !LSM || CV_ERR || LOL || LOS
  • Power on reset default: TBD
  • Expected value during normal operation is TBD

r : MDIO Read Register

Read 16-bit value from MDIO register

notes:

  • Set MDIO page with 'd' before reading
  • Sets MDIO register address

s : Get PHY Status

Executes subroutine to read PHY status register

notes:

  • read the live copper status on page 0, reg 17

t : Transmit Metrics

Transmit metrics packet

notes:

  • maps to sgmii_cont1

u : DCU Reset

Sets DCU-related reset bits

D2 D1 D0
pcs_rst_dual serdes_rst_dual tx_serdes_rst

notes:

  • Command followed by two nibbles:
  • DCU1 followed by DCU0
  • ex: u70 asserts all resets for DCU1

x : Configuration and Reset

Sets reset bits as shown in the table below

D1 D0
phy_reset sgmii_cont_reset

notes:

  • Specify 3 fields / PHYS [2,1,0].
  • Example: remove PHY1 reset only: x313

Example Usage: x000

w : MDI Write Register

  • Set page with 'd' and MDIO register address with 'r' before writing
  • Write 16-bit word

Example Initialization of FPGA and PHYS via I2C

  1. take phys out of reset: x311
  2. SGMII init: i, p1, i, p0
  3. Remove DCU reset: u07
  4. Remove SERDES channel resets: c755
  5. Remove PCS Reset: c700
  6. Take SGMII controllers out of reset: x300

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