Mind Chasers Inc.
Mind Chasers Inc.

Design and Fabrication of Gigabit Ethernet Shield for FPGA Network Processor

We review the design and PCB fabrication of our new GigE Ethernet Shield for our FPGA-based development board

Overview

This article reviews the design and fabrication of our new Gigabit Ethernet Shield for Darsena. If you haven't seen the stages of PCB production before, you'll probably enjoy this article.

Our GigE Shield is one of two shield designs that we're in the process of releasing as open source. This board provides a third Ethernet port for Darsena plus optional RF SMA connectors. The Ethernet PHY is the Texas Instruments DP83867. This design is our first attempt at using a surface mount (SMT) RJ-45 connector. We have been designing in through hole (TH) RJ-45s for many years, so we're eager to put this jack through various testing.

3D Rendering

The first figure shows a 3D rendering of our GigE Shield generated from our Altium CAE program. The board has the specific shape and connector arrangement in order to pick up 3.3V power and LVDS / SERDES pairs from the Arduino form-factor base. Plus, it has lots of available expansion I/O.

Figure 1. 3D Rendering of GigE Shield

Figure 2 below shows our PCB after being drilled. Note that this is a standard 1.6 mm thick, 4 layer PCB using a quick turn process. This is not a controlled impedance design.

The starting copper thickness is 0.5 oz (~18 µm) and will be built up to 1 oz during plating.

Figure 2. PCB After Drilling

The next figure shows the board after being laminated & processed with UV light with a photosensitive material that represents our submitted art work. The bluish regions of copper will be removed during a subsequent chemical bath / stripping process.

Note the copper thieving (arrays of round pads) left behind in the area of the board that will be discarded. It is our understanding that this is to evenly distribute the subsequent tin plating, which makes the resist easier and more reliable to strip properly.

Figure 3. PCB After UV Exposure Process

Figure 4 shows the PCB after stripping away the laminate and tin coating. The copper tracks / traces can now be clearly seen, and the absence of copper on the top layer is the FR4 fiberglass weave.

Also note that the image shows the area where the board will be routed (cut) and also where the ground plane is segmented (layer 2 of the 4 layer board). In other words, the green regions represent no copper on either layer 1 or layer 2.

Figure 4. PCB After Stripping

Figure 5 shows the PCB after application of solder mask and silk screen printing. The traces and pads shown are the original copper foil.

Figure 5. PCB After Curing

Figure 6 shows the PCB after the surface finish has been applied.

We have worked with various finishes over the years and have developed a preference for ENIG (Nickel Gold), which is shown in the figure. This finish is virtually flat (unlike the more common HASL) and lends itself to reliable reflow (good centering and wetting) with challenging QFN/SON packages.

Figure 6. PCB After ENIG Surface Finish

Of course, the board still needs to be routed (cut to the final dimensions).

The last figure shows a first article board on our lab bench working great as a shield to Darsena

Figure 7. First Article!

Didn't find an answer to your question? Post your issue below or in our new FORUM, and we'll try our best to help you find a solution.

And please note that we update our site daily with new content related to our open source approach to network security and system design. If you would like to be notified about these changes, then please follow us on Twitter and join our mailing list.

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