ECP5UM PCS/SERDES Usage for Private Island

A high level overview of the usage and configuration of the ECP5UM DCU (PCS/SERDES) for Private Island

Overview

This article describes the usage and configuration of the Lattice ECP5UM SERDES/PCS block for our Private Island system. The ECP5UM provides two embedded SERDES/PCS channels per Dual-Channel Unit (DCU) and two DCU's per device. As depicted in the figure below, Private Island utilizes three of the four channels for Ethernet channel processing via Gigabit Ethernet PHYs with the additional channel provisioned as a spare and routed to the expansion / accelerator board connector.

Figure 1. High Level Use of PCS/SERDES Blocks
High Level Use of PCS/SERDES Blocks

This article refers to Lattice's "ECP5 and ECP5-5G SERDES/PCS Usage Guide" TN1261, and it is suggested that the reader have it open while reading this article.

The ECP5UM DCU is a hard macrocell, and it provides a great deal of flexibility for various protocols. For Private Island, the DCUs are configured for 1000-BaseT operation via SGMII PHYs, and the settings are summarized in the table below.

Table 1: DCU Parameters for GbE1
DCU (PCS/SERDES) Parameter Setting
Protocol GbE
TX/RX serial data rates 1.25 Gbps
TxPLL/CDR PLL Multiplier 25x
REFCLK (DCU0 only)2 50 MHz
DCU / FPGA data interface width 8-bit
FPGA PCS Clock Rate 125 MHz
Receive CTC Enabled
Receive FIFO Enabled
Transmit FIFO Enabled
Reset Sequence Disabled3
1: The spare channel (DC1, channel 1) isn't configured by default.
2: EXTREF0 drives both DCU0 and DCU1
3: The DCU reset sequence is supervised by the micro controller.

DCU I/O Definition

The Verilog definition for the DCU module is provided in "ecp5um.v", which can be found within the Lattice Diamond installation. For Diamond 3.10 on Windows 10, the path is <diamond install path>\3.10_x64\synpbase\lib\lucent. In some cases, the module I/O names do not match the signal names provided in the TN1261 documentation. Therefore, a mapping for many of the utilized signals is provided in the tables below.

Table 2: DCU Dual I/O
DCUA Definition signal name I/O Notes
D_FFC_DUAL_RST rst_dual_c I AUX channel
D_FFC_MACRO_RST serdes_rst_dual_c I AUX channel
D_FFC_MACROPDB serdes_pdb I AUX channel
D_FFC_TRST tx_serdes_rst_c I Only one for both TX channels
D_REFCLKI refclko I TX PLL reference clock from EXTREF
D_FFS_PLOL pll_lol O Don't use. Use soft logic generated by Clarity instead
Table 3: Channel I/O
DCUA Definition signal name I/O Notes
CHX_RX_REFCLK1 refclko I CDR reference clock from EXTREF
CHX_FF_RXI_CLK txi_clk I RX FIFO clock from FPGA
CHX_FF_TXI_CLK txi_clk2 I TX FIFO clock from FPGA
CHX_FF_EBRD_CLK txi_clk2 I CTC FIFO clock from FPGA
CHX_FF_TX_D_[0:7] txdata[0:7] I Transmit data bus
CHX_FF_TX_D_8 tx_k I Assert for special code-groups
CHX_FF_TX_D_10 xmit I Auto negotiation / idle insert
CHX_FF_TX_D_11 tx_disp_correct I Assert for DCU to correct disaparity
CHX_FFC_SIGNAL_DETECT signal_detect_c I Enable RX link state machine
CHX_FFC_LANE_TX_RST tx_pcs_rst_c I Reset TX channel PCS logic
CHX_FFC_LANE_RX_RST rx_pcs_rst_c I Reset RX channel PCS logic
CHX_FFC_RRST rx_serdes_rst_c I Reset digital logic in SERDES RX channel
CHX_FFC_TXPWDNB tx_pwrup_c I TX Channel power up
CHX_FFC_RXPWDNB rx_pwrup_c I RX Channel power up
CHX_FF_TX_PCLK tx_pclk O Transmit Primary Clock
CHX_FF_RX_D_[0:7] rxdata[0:7] O Receive data bus
CHX_FF_RX_D_8 rx_k O Asserted for special code-groups
CHX_FF_RX_D_9 rx_disp_err O RX disparity error
CHX_FF_RX_D_10 rx_cv_err O code violation
CHX_FFS_RLOS rx_los_low_s O Loss of signal (LO THRESHOLD RANGE) detection
CHX_FFS_LS_SYNC_STATUS lsm_status_s O Channel is synced with commas
CHX_FFS_RLOL rx_cdr_lol_s O CDR loss loss of lock
CHX_FFS_CC_UNDERRUN() ctc_urun_s O CTC status flag
CHX_FFS_CC_OVERRUN() ctc_orun_s O CTC status flag
CHX_FFS_SKP_ADDED ctc_ins_s O CTC status flag
CHX_FFS_SKP_DELETED ctc_del_s O CTC status flag
1: Where CHX is CH[0:2].
2: The Clarity generated files for sgmii<N>.v are manually modified to route txi_clk to ebrd_clk and rxi_clk.

SERDES Client Interface

This interface supports both an alternative method to static configuration of the DCU block as well as some dynamic configuration. Private Island supports run-time modification of the SCI registers via the system micro controller.

Table 4: SCI Dual I/O
DCUA Definition signal name I/O Notes
D_SCIWDATA[0:7] sci_wrdata[0:7] I
D_SCIADDR[0:5] sci_addr[0:5] I
D_SCIENAUX sci_en_dual I Not defined in TN1261
D_SCISELAUX sci_sel_dual I
D_SCIRD sci_rd I
D_SCIWSTN sci_wrn I
D_SCIRDATA[0:7] sci_rddata[0:7] O
D_SCIINT sci_int O
Table 5: SCI Channel I/O
DCUA Definition signal name I/O Notes
CHX_SCIEN sci_en I Not defined in TN1261
CHX_SCISEL sci_sel I

DCU Clocking

The figure below shows the clocking architecture for DCU0, channel 0, and it is similar to Figure 4 in TN1261. The output of the TxPLL is routed to the FPGA fabric as tx_pclk and used globally to clock the DCU FPGA Bridge circuits (RX FIFO, TX FIFO, and CTC FIFO) for both DCU0 and DCU1. In other words, the output of the DCU0 TXPLL is used globally to clock all Ethernet circuits in the FPGA soft logic and both DCU FPGA bridge circuits. Therefore, the other tx_pclk signals and all recovered RX CDR outputs are left floating.

Figure 2. FPGA / DCU Clocking
High Level Use of PCS/SERDES Blocks

Issues that we're working to resolve

  • We need to confirm that ebrd_clk clocks both the PCS CTC FIFO and the FPGA Bridge RX FIFO as shown in Figure 2 above.
  • Clarity does not support disabling the RX and TX FPGA Bridge FIFOS, and it's not clear that they are always required.
  • As shown in figure 9 of TN1261, the output of the TXPLL on DCU0 can be shared with DCU1. This isn't supported by Clarity, but we are investigating making this change manually in the Verilog.
  • We use the DCU GbE mode. There is also an SGMII mode, and this requires further investigation to determine whether this other mode has any advantages.
  • We would like to identify which SCI registers can be modified during runtime without requiring a reset. We also need clarification on the use of the SCI enable signal.
  • Need more information on what defines an error for the FPGA Bridge RX and TX FIFOs

Terms

  • SB: SERDES Bridge
  • DCU: Dual Channel Unit
  • FB: FPGA Bridge
  • FF: FPGA Fabric
  • FPGA: Field Programmable Gate Array
  • PHY: Physical Layer Device
  • PCS: Physical Coding Sublayer
  • SCI: SERDES Client Interface
  • SERDES: Serializer (SER) / Deserializer (DES)

Additional References

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