| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2019-07-08 | ldf: update project file to include reveal files for lab exercises | mindchasers | |
| also update .gitignore and prune boards directory to remove *.trc from repo since it's not a source file. | |||
| 2019-07-08 | reveal: add labs reveal files to support lab exercises | mindchasers | |
| 2019-05-01 | initial commit, all basic functions work on Darsena V02 | mindchasers | |
 |
index : privateisland | |
| FPGA network processor | Private Island Networks Inc. |
| summaryrefslogtreecommitdiffhomepage |
path: root/.gitignore
Highly Recommended Verilog Books
