/* * metrics.v * * Copyright (C) 2018, 2019 Mind Chasers Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. * You may obtain a copy of the License at * * http://www.apache.org/licenses/LICENSE-2.0 * * Unless required by applicable law or agreed to in writing, software * distributed under the License is distributed on an "AS IS" BASIS, * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. * * function: Collect metrics here and register them for transmit * * */ `timescale 1ns /10ps module metrics( input rstn, input clk, input mode_100Mbit, // input data for gathering metrics input [3:0] rx_mac_keep, input rx_pf_keep_01, input rx_pf_keep_02, input rx_pf_keep_10, input rx_pf_keep_12, input rx_pf_keep_20, input rx_pf_keep_21, input rx_pf_keep_23, input [3:0] rx_eop, input [3:0] rx_sop, input [3:0] tx_eop, input [3:0] tx_sop, // metric outputs input metrics_start, output reg [8:0] metrics_d ); reg [7:0] rx_pkt_cnt; reg [7:0] tx_pkt_cnt; reg [7:0] rx0_drop_cnt; reg [7:0] rx1_drop_cnt; reg [3:0] bit_cnt; reg [3:0] addr; always @(posedge clk or negedge rstn) if (!rstn) begin bit_cnt <= 4'h0; addr <= 4'h0; end else if ( metrics_start ) begin bit_cnt <= 4'h0; addr <= 4'h0; end else if ( !mode_100Mbit || ( mode_100Mbit && bit_cnt == 4'h9 ) ) begin bit_cnt <= 4'h0; addr <= addr + 1; end else bit_cnt <= bit_cnt + 1; always @(posedge clk or negedge rstn) if (!rstn) rx_pkt_cnt <= 'h0; else if (rx_eop[2]) rx_pkt_cnt <= rx_pkt_cnt + 1; always @(posedge clk or negedge rstn) if (!rstn) tx_pkt_cnt <= 'h0; else if (tx_eop[2]) tx_pkt_cnt <= tx_pkt_cnt + 1; always @(posedge clk or negedge rstn) if (!rstn) metrics_d <= 9'h100; else begin case(addr) 'h0: metrics_d <= { 1'b0, rx_pkt_cnt }; 'h1: metrics_d <= { 1'b0, tx_pkt_cnt }; 'h2: metrics_d <= { 1'b0, rx0_drop_cnt }; 'h3: metrics_d <= { 1'b1, rx1_drop_cnt }; default: metrics_d <= 9'h100; endcase end endmodule