/*
 *      interrupts.v
 *
 *   Copyright (C) 2018, 2019 Mind Chasers Inc.
 *
 *   Licensed under the Apache License, Version 2.0 (the "License");
 *   you may not use this file except in compliance with the License.
 *   You may obtain a copy of the License at
 *
 *       http://www.apache.org/licenses/LICENSE-2.0
 *
 *   Unless required by applicable law or agreed to in writing, software
 *   distributed under the License is distributed on an "AS IS" BASIS,
 *   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 *   See the License for the specific language governing permissions and
 *   limitations under the License.
 *
 *	function: uC Interrupt Controller
 *
 */

`timescale 1ns /10ps


module interrupts (
	input rstn,
	input clk,
	input uc_clk,


// uC interface
	input   sel,
	input 	we,
	input 	addr,
	input 	[6:0]	d_in,
	output  [6:0]	d_out,
	
	// interrupt sources
	input cont_int,
	input [3:0] phy_int,
	input [3:0] mac_int,
	
	// int out
	output int_o
);
	
localparam	INT_CONTROLLER = 'h01,
			INT_PHY0 = 'h02,
			INT_PHY1 = 'h04,
			INT_MAC0 = 'h08,
			INT_MAC1 = 'h10,
			INT_MAC2 = 'h20,
			INT_MAC3 = 'h40;
	
reg [6:0] int_enable;
reg [6:0] int_src;

assign d_out = addr ? int_src : int_enable;
assign int_o = int_src[6] & int_enable[6] | int_src[5] & int_enable[5] | int_src[4] & int_enable[4] | int_src[3] & int_enable[3] |
				int_src[2] & int_enable[2] | int_src[1] & int_enable[1] | int_src[0] & int_enable[0];

always @(posedge uc_clk or negedge rstn)
	if (!rstn)
		int_enable <= INT_MAC2 | INT_MAC3;
	else if (sel && we && !addr)
		int_enable <= d_in;

always @(posedge uc_clk or negedge rstn)
	if (!rstn)
		int_src <= 7'h0;
	else if (sel && we && addr)
		int_src <= d_in;
	else 
		int_src <= int_src | { mac_int, phy_int[1:0], cont_int };

	
endmodule