/*	
 * 	dpram.v
 * 
 *   Copyright (C) 2018, 2019 Mind Chasers Inc.
 *
 *   Licensed under the Apache License, Version 2.0 (the "License");
 *   you may not use this file except in compliance with the License.
 *   You may obtain a copy of the License at
 *
 *       http://www.apache.org/licenses/LICENSE-2.0
 *
 *   Unless required by applicable law or agreed to in writing, software
 *   distributed under the License is distributed on an "AS IS" BASIS,
 *   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 *   See the License for the specific language governing permissions and
 *   limitations under the License.
 *
 *	function: DPRAM wrapper
 * 
 */

`timescale 1ns /10ps


module dpram(
	input  rstn,
	
	// port A
	input a_clk,
	input a_clk_e,
	input a_we,
	input a_oe,
	input [10:0] a_addr,
	input [8:0]  a_din,
	output [8:0] a_dout,
	
	// port B
	input b_clk,
	input b_clk_e,
	input b_we,
	input b_oe,
	input [10:0] b_addr,
	input [8:0]  b_din,
	output [8:0] b_dout
);


DP16KD dp16kd_inst(
	// input data port A
	.DIA17( 1'b0 ), .DIA16( 1'b0  ), .DIA15( 1'b0  ), .DIA14( 1'b0  ), .DIA13( 1'b0  ), 
	.DIA12(  1'b0 ), .DIA11( 1'b0  ), .DIA10( 1'b0  ), .DIA9( 1'b0  ), .DIA8( a_din[8]  ), 
	.DIA7( a_din[7] ), .DIA6( a_din[6]  ), .DIA5( a_din[5]  ), .DIA4( a_din[4] ), 
	.DIA3( a_din[3]  ), .DIA2( a_din[2]  ), .DIA1(  a_din[1] ), .DIA0(  a_din[0]  ),
	
	// input address bus port A
	.ADA13( a_addr[10] ), .ADA12( a_addr[9] ), 
	.ADA11( a_addr[8] ), .ADA10(  a_addr[7]), .ADA9(  a_addr[6] ), .ADA8( a_addr[5] ),
	.ADA7( a_addr[4] ), .ADA6( a_addr[3] ), .ADA5( a_addr[2] ), .ADA4( a_addr[1] ), .ADA3( a_addr[0] ),
	.ADA2( 1'b0 ), .ADA1( 1'b0 ), .ADA0( 1'b0 ), 
	
	.CEA( a_clk_e ), 	// clock enable
	.OCEA( a_oe ), 	// output clock enable
	.CLKA( a_clk ), // clock for port A
	.WEA( a_we ), 	// write enable 
	.CSA2( 1'b0 ), .CSA1( 1'b0 ), .CSA0( 1'b0 ), // chip selects 
	.RSTA( ~rstn ),	// reset for port A
	
	// outputs
	.DOA17(), .DOA16(), .DOA15(), .DOA14(), .DOA13(), .DOA12(), .DOA11(), .DOA10(), .DOA9( ),
	.DOA8( a_dout[8] ), .DOA7( a_dout[7] ), .DOA6( a_dout[6] ), .DOA5( a_dout[5] ), .DOA4( a_dout[4] ), 
	.DOA3( a_dout[3] ), .DOA2( a_dout[2] ), .DOA1( a_dout[1] ), .DOA0( a_dout[0] ),
	
	// input data port B
	.DIB17( 1'b0 ), .DIB16( 1'b0 ), .DIB15( 1'b0 ), .DIB14( 1'b0 ), .DIB13( 1'b0 ), 
	.DIB12( 1'b0 ), .DIB11( 1'b0 ), .DIB10( 1'b0 ), .DIB9( 1'b0 ),
	.DIB8( b_din[8] ), .DIB7( b_din[7] ), .DIB6( b_din[6] ), .DIB5( b_din[5] ), 
	.DIB4(  b_din[4] ), .DIB3(  b_din[3] ), .DIB2( b_din[2] ), .DIB1( b_din[1] ), .DIB0( b_din[0] ),
	
	// input address bus port B
	.ADB13( b_addr[10] ), .ADB12( b_addr[9] ), .ADB11( b_addr[8] ), .ADB10( b_addr[7] ), .ADB9( b_addr[6] ), 
	.ADB8( b_addr[5] ), .ADB7( b_addr[4] ), .ADB6( b_addr[3] ), .ADB5( b_addr[2] ),
	.ADB4( b_addr[1] ), .ADB3( b_addr[0] ), .ADB2( 1'b0 ), .ADB1(  1'b0 ), .ADB0(  1'b0 ),
	
	.CEB( b_clk_e ), // clock enable
	.OCEB( b_oe ), // output clock enable
	.CLKB( b_clk ), // clock for port B
	.WEB( b_we ), // write enable 
	.CSB2( 1'b0 ), .CSB1( 1'b0 ), .CSB0( 1'b0 ), // chip selects 
	.RSTB( ~rstn ),	// reset for port B
	
	// outputs
	
	.DOB17(), .DOB16(), .DOB15(), .DOB14(), .DOB13(), .DOB12(), .DOB11(), .DOB10(), .DOB9( ),
	.DOB8( b_dout[8] ), .DOB7( b_dout[7] ), .DOB6( b_dout[6] ), .DOB5( b_dout[5] ), 
	.DOB4( b_dout[4] ), .DOB3( b_dout[3] ), .DOB2( b_dout[2] ), .DOB1( b_dout[1] ), .DOB0( b_dout[0] ) 
	
); 
// defparam dp16kd_inst.INITVAL_00 = "0x123456789abcdef0123456789abcdef0123456789abcdef0123456789abcaa9980123456789abcde";
defparam dp16kd_inst.DATA_WIDTH_A = 9;
defparam dp16kd_inst.DATA_WIDTH_B = 9;

endmodule