/*
 *       clk_gen.v
 *
 *   Copyright (C) 2018, 2019 Mind Chasers Inc.
 *
 *   Licensed under the Apache License, Version 2.0 (the "License");
 *   you may not use this file except in compliance with the License.
 *   You may obtain a copy of the License at
 *
 *       http://www.apache.org/licenses/LICENSE-2.0
 *
 *   Unless required by applicable law or agreed to in writing, software
 *   distributed under the License is distributed on an "AS IS" BASIS,
 *   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 *   See the License for the specific language governing permissions and
 *   limitations under the License.
 *
 *	function: Generate system / controller clocks from internal oscillator
 *	
 */

`timescale 1ns /10ps

module clk_gen(
	input rstn,
	output	clk_10,
	output 	clk_5,
	output	clk_2_5,
	output	clk_1_25,
	output  clk_slow
);


	wire clk;
	reg [8:0] clk_cnt;
	wire clk_0_625, clk_0_3125, clk_75K, clk_37_5K, clk_150K;
	
	/* 
	+/- 15% variation in output frequency 
	128 is the default for a 2.5 MHz clock, +/- 15% 
	32 is 9.7 MHz
	16 for 19.4 MHz.
	*/
	OSCG oscg_inst(.OSC(clk));
	defparam oscg_inst.DIV = 32;	

	always @ (posedge clk or negedge rstn) 
	begin 
	   if  ( !rstn )
		   clk_cnt <= 0;
	   else
		   clk_cnt <= clk_cnt + 1;
	end

	assign clk_10 = clk;			// 10 MHz system clock
	assign clk_5 = clk_cnt[0];
	assign clk_2_5 = clk_cnt[1];
	assign clk_1_25 = clk_cnt[2];	// 1.22MHz
	assign clk_0_625 = clk_cnt[3];
	assign clk_0_3125 = clk_cnt[4];
	assign clk_150K = clk_cnt[5];
	assign clk_75K = clk_cnt[6];
	assign clk_37_5K = clk_cnt[7];

	assign clk_slow = clk_37_5K;
	
endmodule