From 5723ec1a34181f1cfef9b8e870ab2e9a0362487c Mon Sep 17 00:00:00 2001 From: mindchasers Date: Wed, 1 May 2019 18:16:45 -0400 Subject: initial commit, all basic functions work on Darsena V02 --- clarity/pcs/sgmii2/sgmii2.lpc | 97 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 clarity/pcs/sgmii2/sgmii2.lpc (limited to 'clarity/pcs/sgmii2/sgmii2.lpc') diff --git a/clarity/pcs/sgmii2/sgmii2.lpc b/clarity/pcs/sgmii2/sgmii2.lpc new file mode 100644 index 0000000..5e8a34b --- /dev/null +++ b/clarity/pcs/sgmii2/sgmii2.lpc @@ -0,0 +1,97 @@ +[Device] +Family=ecp5um +OperatingCondition=COM +Package=CABGA381 +PartName=LFE5UM-45F-8BG381C +PartType=LFE5UM-45F +SpeedGrade=8 +Status=P +[IP] +CoreName=PCS +CoreRevision=8.2 +CoreStatus=Demo +CoreType=LPM +Date=03/15/2019 +ModuleName=sgmii2 +ParameterFileVersion=1.0 +SourceFormat=verilog +Time=18:46:19 +VendorName=Lattice Semiconductor Corporation +[Parameters] +;ACHARA=0 00H +;ACHARB=0 00H +;ACHARM=0 00H +;RXMCAENABLE=Disabled +CDRLOLACTION=Full Recalibration +CDRLOLRANGE=0 +CDR_MAX_RATE=1.25 +CDR_MULT=25X +CDR_REF_RATE=50.0000 +CH_MODE=Rx and Tx +Destination=Synplicity +EDIF=1 +Expression=BusA(0 to 7) +IO=0 +IO_TYPE=GbE +LEQ=0 +LOOPBACK=Disabled +LOSPORT=Enabled +NUM_CHS=1 +Order=Big Endian [MSB:LSB] +PPORT_RX_RDY=Disabled +PPORT_TX_RDY=Disabled +PROTOCOL=GbE +PWAIT_RX_RDY=3000 +PWAIT_TX_RDY=3000 +RCSRC=Disabled +REFCLK_RATE=50.0000 +RSTSEQSEL=Disabled +RX8B10B=Enabled +RXCOMMAA=1010000011 +RXCOMMAB=0101111100 +RXCOMMAM=1111111111 +RXCOUPLING=AC +RXCTC=Enabled +RXCTCBYTEN=0 00H +RXCTCBYTEN1=0 00H +RXCTCBYTEN2=1 BCH +RXCTCBYTEN3=0 50H +RXCTCMATCHPATTERN=M2-S2 +RXDIFFTERM=50 ohms +RXFIFO_ENABLE=Enabled +RXINVPOL=Non-invert +RXLDR=Off +RXLOSTHRESHOLD=4 +RXLSM=Enabled +RXSC=K28P5 +RXWA=Barrel Shift +RX_DATA_WIDTH=8/10-Bit +RX_FICLK_RATE=125.0000 +RX_LINE_RATE=1.2500 +RX_RATE_DIV=Full Rate +SCIPORT=Enabled +SOFTLOL=Enabled +TX8B10B=Enabled +TXAMPLITUDE=400 +TXDEPOST=Disabled +TXDEPRE=Disabled +TXDIFFTERM=50 ohms +TXFIFO_ENABLE=Enabled +TXINVPOL=Non-invert +TXLDR=Off +TXPLLLOLTHRESHOLD=0 +TXPLLMULT=25X +TX_DATA_WIDTH=8/10-Bit +TX_FICLK_RATE=125.0000 +TX_LINE_RATE=1.2500 +TX_MAX_RATE=1.25 +TX_RATE_DIV=Full Rate +VHDL=0 +Verilog=1 +[FilesGenerated] +sgmii2.pp=pp +sgmii2.sym=sym +sgmii2.tft=tft +sgmii2.txt=pcs_module +[SYSTEMPNR] +LN0=DCU1_CH0 -- cgit v1.2.3-8-gadcc