From 1c7478194daae4be777a21552295133a735082cb Mon Sep 17 00:00:00 2001
From: mindchasers <privateisland@mindchasers.com>
Date: Sun, 27 Sep 2020 20:54:08 -0400
Subject: clarity: update SERDES/PCS block to be compatible with Diamond 3.11

---
 clarity/pcs/refclk0/refclk0.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'clarity/pcs/refclk0/refclk0.v')

diff --git a/clarity/pcs/refclk0/refclk0.v b/clarity/pcs/refclk0/refclk0.v
index 7fe46e2..edeb81f 100644
--- a/clarity/pcs/refclk0/refclk0.v
+++ b/clarity/pcs/refclk0/refclk0.v
@@ -1,5 +1,5 @@
 // Verilog netlist produced by program ASBGen: Ports rev. 2.30, Attr. rev. 2.65
-// Netlist written on Tue Oct 17 18:22:54 2017
+// Netlist written on Fri Mar 06 20:20:57 2020
 //
 // Verilog Description of module refclk0
 //
-- 
cgit v1.2.3-8-gadcc