From da76ee103bf89c28c7d6027371e4a420ada41932 Mon Sep 17 00:00:00 2001 From: mindchasers Date: Mon, 16 Nov 2020 13:59:15 -0500 Subject: project: rename sim folder, update README --- README | 26 -------------------------- 1 file changed, 26 deletions(-) delete mode 100644 README (limited to 'README') diff --git a/README b/README deleted file mode 100644 index 90b78b4..0000000 --- a/README +++ /dev/null @@ -1,26 +0,0 @@ -# privateisland - -Open Source FPGA Network Processor for Security, IoT, and Control. - -See LICENSE in this folder and reference to LICENSE in header of each Verilog source file. - -Contributors must agree to Contributor License Agreement (to be added). - -Brief Overview: - -FPGAs are amazing! - -Multi-port Etherent MAC, network switch, classifier, filter and more. - -Define the operation of your own device. Do things truly in parallel. See packets like you never thought possible. - -The initial version of this project targets a Lattice ECP5UM FPGA. - -Project is Veriog only. Test benches are Verilog / System Verilog and will be added to project soon. - -Build bit image using Lattice Diamond. Project files are based on Windws 10 at C:\projects\lattice\privateisland\ - -The FPGA architecture assumes an external micro controller / processor. The Darsena board uses an NXP K02. Test code for the K02 will be available in a separate github repo. - -Please see further documentation at https://mindchasers.com/dev/private-island and additional related documentation referenced from this page. - -- cgit v1.2.3-8-gadcc