From 56f32ac8d528c573165fa72d207eb467ecfaebf5 Mon Sep 17 00:00:00 2001 From: mindchasers Date: Tue, 2 Mar 2021 13:26:07 -0500 Subject: top: remap shield I/O to use GPIO rather than specific names, default is now network tap, misc cleanup --- manufacturer/lattice/ecp5um/source/top.v | 262 +++++++++++++++---------------- 1 file changed, 129 insertions(+), 133 deletions(-) diff --git a/manufacturer/lattice/ecp5um/source/top.v b/manufacturer/lattice/ecp5um/source/top.v index 5ef9727..d23ea1b 100644 --- a/manufacturer/lattice/ecp5um/source/top.v +++ b/manufacturer/lattice/ecp5um/source/top.v @@ -1,7 +1,7 @@ /* * top.v * - * Copyright (C) 2018, 2019, 2020 Mind Chasers Inc. + * Copyright (C) 2018, 2019, 2020, 2021 Mind Chasers Inc. * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -64,20 +64,6 @@ module top( inout phy1_mdio, input [1:0] phy1_gpio, input phy1_intn, - -`ifdef SHIELD_GIGE_SMA - output phy2_resetn, - output phy2_mdc, - inout phy2_mdio, -`elsif SHIELD_SFP_SMA - input sfp_tx_fault, // high indicates a laser fault of some kind. - output sfp_tx_disable, // high disables the transmitter - input sfp_pres_n, // (mod-def 0): grounded by the module to indicate that the module is present) - inout sfp_i2c_sda, // (mod-def 2) - output sfp_i2c_scl, // (mod-def 1) - input sfp_los, // Low indicates normal operation - output sfp_rate_select, // high for full bandwidth -`endif // Microcontroller SPI and bit banging input spi_cs, @@ -104,27 +90,24 @@ module top( output [2:0] led, - output ard_sda, - output ard_scl, - -`ifdef SHIELD_SFP_SMA - output sfp_led1, // TXD3 - output sfp_led2, // RXD3 - output sfp_led3, // TXD2 - output sfp_led4, // RXD2 - output sfp_led5, // TXD1 - output sfp_led6, // RXD1 -`endif - - input pe0, // - output pe1, // - output pe3, - output pe4, - output pe5, - output pg5, - input ph3, // UART RX for SFP Testing - output ph4, // UART TX for SFP Testing - inout [9:0] pa + // Arduino Compatible GPIO + inout ard_sda, + inout ard_scl, + inout ard_rxd1, + inout ard_txd1, + inout ard_rxd2, + inout ard_txd2, + inout ard_rxd3, + inout ard_txd3, + inout pe0, // + inout pe1, // + inout pe3, + inout pe4, + inout pe5, + inout pg5, + inout ph3, // UART RX for SFP Testing + inout ph4, // UART TX for SFP Testing + inout [9:0] pa ); @@ -174,6 +157,13 @@ wire mdio_ld, mdio_run; wire mdio_rwn; wire bin_to_ascii_run; +`ifdef SHIELD_GIGE_SMA + wire phy2_resetn, phy2_mdc; + wire phy2_mdio_o, phy2_mdio_i, phy2_mdio_oe; +`elsif SHIELD_SFP_SMA + wire sfp_los, sfp_rate_select, sfp_pres_n, sfp_i2c_scl, sfp_tx_fault, sfp_tx_disable, sfp_i2c_sda; +`endif + // MDIO Data block wire [MDIO_ROM_ADDR_SZ-1:0] rom_a; wire [7:0] rom_d; @@ -185,15 +175,11 @@ wire [4:0] mdio_page_set; wire sda_oe, scl_oe, sda_o, scl_o; wire i2c_fifo_priority; -// UART -wire uart_rx_done; -wire read_fifo_we; -wire [8:0] fifo_r_d; -wire [6:0] d_uart_rx; - // bin to ASCII wire [15:0] bin_to_ascii_d_in; wire [6:0] cont_rd; +wire read_fifo_we; +wire [8:0] fifo_r_d; // PCS, mac wire pcs_pclk; @@ -214,7 +200,7 @@ wire [3:0] ipv4_pkt_complete; reg cont_fifo_re_m1, cont_fifo_re_m2; wire cont_fifo_empty; -wire i2c_fifo_re, uart_fifo_re; +wire i2c_fifo_re; wire i2c_cont_we, i2c_cont_done; wire i_cont_fifo_re; wire bin_to_ascii_we, mdio_rd_we, cont_rd_we; @@ -313,6 +299,7 @@ wire [8:0] rx_uc_fifo_d_u2; wire rx_sf_almost_full_01, rx_sf_almost_full_02, rx_sf_almost_full_03; wire rx_sf_almost_full_10, rx_sf_almost_full_12, rx_sf_almost_full_13; wire rx_sf_almost_full_20, rx_sf_almost_full_21, rx_sf_almost_full_23; +wire [2:0] tx_src_sel0, tx_src_sel1, tx_src_sel2, tx_src_sel3; // between switch and mac @@ -329,11 +316,6 @@ wire [3:0] tx_sc_done; // 100 Mbit wire[3:0] mode_100Mbit; -// Flexbus -wire fb_ad_oe; -wire[9:0] fb_ad_o; -reg[9:0] fb_d; - wire pkt_filter_sel_01, pkt_filter_sel_02, pkt_filter_sel_03; wire pkt_filter_sel_10, pkt_filter_sel_12, pkt_filter_sel_13; wire pkt_filter_sel_20, pkt_filter_sel_21, pkt_filter_sel_23, pkt_filter_sel_2u; @@ -422,7 +404,7 @@ clk_gen clk_gen_0( * main controller * * controls worker blocks -* interfaces with uC via I2C / UART +* interfaces with uC via I2C * */ controller #(.ADDR_SZ( MDIO_ROM_ADDR_SZ ))controller_0 @@ -469,7 +451,7 @@ controller #(.ADDR_SZ( MDIO_ROM_ADDR_SZ ))controller_0 .mdio_mux_sel( mdio_mux_sel ), .i2c_fifo_priority( i2c_fifo_priority ), // TX custom packet - .tx_metrics( tx_custom ) + .tx_custom( tx_custom ) ); @@ -570,46 +552,47 @@ mac mac_0( .phy_resetn ( phy_resetn[0] ), .clk( pcs_pclk ), .tap_port ( 1'b0 ), + // PCS / SERDES health + .rx_lsm( sgmii_lsm_status[0] ), + .rx_cv_err ( sgmii_rx_cv_err[0] ), + .rx_disp_err( sgmii_rx_disp_err[0] ), + .rx_cdr_lol( sgmii_rx_cdr_lol[0] ), + .rx_los ( sgmii_rx_los_low[0] ), // AN .phy_type(2'b00), // SGMII=0 - .an_disable( 1'b0 ), .pulse_1_6ms(pulse_1_6ms), .pulse_10ms(pulse_10ms), .fixed_speed(SGMII_SPEED_AN), + .an_disable( 1'b0 ), .an_duplex( ), - .mode_100Mbit( mode_100Mbit[0] ), .phy_up( phy_up[0] ), + .mode_100Mbit( mode_100Mbit[0] ), // Switch I/F .tx_mode( tx_sw_mode0 ), .tx_f( tx_sc_done[0] ), - // PCS / SERDES health - .rx_lsm( sgmii_lsm_status[0] ), - .rx_cv_err ( sgmii_rx_cv_err[0] ), - .rx_disp_err( sgmii_rx_disp_err[0] ), - .rx_cdr_lol( sgmii_rx_cdr_lol[0] ), - .rx_los ( sgmii_rx_los_low[0] ), // PCS data I/F .rx_k( sgmii_rx_k[0] ), .rx_data( rx_data0 ), .tx_k( sgmii_tx_k[0] ), .tx_data( tx_data0 ), .tx_disp_correct( sgmii_tx_disp_correct[0] ), - // Flags and Interrupts - .keep( rx_mac_keep[0] ), // TX FCS .fcs_init( fcs_init[0] ), .fcs_enable( fcs_enable[0] ), .fcs_addr( fcs_addr0 ), .fcs_dout( fcs_din0 ), .fcs_din( fcs_dout0 ), - // SGMII RX / FIFO Write + // MAC RX / FIFO Write .rx_fifo_we( rx_sc_fifo_we[0] ), .rx_fifo_d( rx_sc_fifo_d0 ), .rx_error( rx_sc_error[0] ), + .rx_keep( rx_mac_keep[0] ), .rx_wr_done( rx_sc_wr_done[0] ), .rx_byte_cnt(rx0_byte_cnt), - // SGMII TX / FIFO Read + .rx_mode(), + // MAC TX / FIFO Read .tx_byte_cnt_i(tx0_byte_cnt), + .tx_src_sel(tx_src_sel0), .tx_fifo_re( tx_sc_fifo_re[0] ), .tx_fifo_d( tx_sw_fifo_d0 ), .tx_fifo_empty( tx_sw_fifo_empty[0] ), @@ -617,8 +600,6 @@ mac mac_0( .rx_sample( rx_sample[0] ), .ipv4_pkt_start( ipv4_pkt_start[0] ), .trigger( ), - .rx_enet_bcast( rx_enet_bcast[0] ), - .rx_ipv4_arp( rx_ipv4_arp[0] ), .rx_k_m1( rx0_k_m1 ), .rx_k_m2( rx0_k_m2 ), .rx_k_m3( rx0_k_m3), @@ -633,7 +614,9 @@ mac mac_0( .dpr_ce( param_phy0_ce ), .dpr_di( param_phy0_din ), .dpr_do( param_phy0_dout ), - // Metrics and Interrupts + // Flags, Metrics, Interrupts, and Debug + .rx_enet_bcast( rx_enet_bcast[0] ), + .rx_ipv4_arp( rx_ipv4_arp[0] ), .mac_int( mac_int[0] ), .rx_sop( rx_sop[0] ), .rx_eop( rx_eop[0] ), @@ -868,46 +851,47 @@ mac mac_1( .phy_resetn ( phy_resetn[1] ), .clk( pcs_pclk ), .tap_port ( 1'b0 ), + // PCS / SERDES health + .rx_lsm( sgmii_lsm_status[1] ), + .rx_cv_err ( sgmii_rx_cv_err[1] ), + .rx_disp_err( sgmii_rx_disp_err[1] ), + .rx_cdr_lol( sgmii_rx_cdr_lol[1] ), + .rx_los ( sgmii_rx_los_low[1] ), // AN .phy_type(2'b00), // SGMII==0 - .an_disable( 1'b0 ), .pulse_1_6ms(pulse_1_6ms), .pulse_10ms(pulse_10ms), .fixed_speed(SGMII_SPEED_AN), + .an_disable( 1'b0 ), .an_duplex( ), - .mode_100Mbit( mode_100Mbit[1] ), .phy_up( phy_up[1] ), + .mode_100Mbit( mode_100Mbit[1] ), // Switch I/F .tx_mode( tx_sw_mode1 ), .tx_f( tx_sc_done[1] ), - // PCS / SERDES health - .rx_lsm( sgmii_lsm_status[1] ), - .rx_cv_err ( sgmii_rx_cv_err[1] ), - .rx_disp_err( sgmii_rx_disp_err[1] ), - .rx_cdr_lol( sgmii_rx_cdr_lol[1] ), - .rx_los ( sgmii_rx_los_low[1] ), // PCS data I/F .rx_k( sgmii_rx_k[1] ), .rx_data( rx_data1 ), .tx_k( sgmii_tx_k[1] ), .tx_data( tx_data1 ), .tx_disp_correct( sgmii_tx_disp_correct[1] ), - // Flags and Interrupts - .keep( rx_mac_keep[1] ), // FCS .fcs_init( fcs_init[1] ), .fcs_enable( fcs_enable[1] ), .fcs_addr( fcs_addr1 ), .fcs_dout( fcs_din1 ), .fcs_din( fcs_dout1 ), - // SGMII RX / FIFO Write + // MAC RX / FIFO Write .rx_fifo_we( rx_sc_fifo_we[1] ), .rx_fifo_d( rx_sc_fifo_d1 ), .rx_error( rx_sc_error[1] ), + .rx_keep( rx_mac_keep[1] ), .rx_wr_done( rx_sc_wr_done[1] ), .rx_byte_cnt(rx1_byte_cnt), - // SGMII TX / FIFO Read + .rx_mode(), + // MAC TX / FIFO Read .tx_byte_cnt_i(tx1_byte_cnt), + .tx_src_sel(tx_src_sel1), .tx_fifo_re( tx_sc_fifo_re[1] ), .tx_fifo_d( tx_sw_fifo_d1 ), .tx_fifo_empty( tx_sw_fifo_empty[1] ), @@ -915,8 +899,6 @@ mac mac_1( .rx_sample( ), .ipv4_pkt_start( ipv4_pkt_start[1] ), .trigger( ), - .rx_enet_bcast( rx_enet_bcast[1] ), - .rx_ipv4_arp( rx_ipv4_arp[1] ), .rx_k_m1( rx1_k_m1 ), .rx_k_m2( rx1_k_m2 ), .rx_k_m3( rx1_k_m3), @@ -931,7 +913,9 @@ mac mac_1( .dpr_ce(param_phy1_ce ), .dpr_di(param_phy1_din), .dpr_do(param_phy1_dout), - // Metrics and Interrupts + // Flags, Metrics, Interrupts, and Debug + .rx_enet_bcast( rx_enet_bcast[1] ), + .rx_ipv4_arp( rx_ipv4_arp[1] ), .mac_int( mac_int[1] ), .rx_sop( rx_sop[1] ), .rx_eop( rx_eop[1] ), @@ -1184,53 +1168,52 @@ metrics metrics_2( .metrics_d( metrics_d ) ); - -// GEODSS MAC mac mac_2( .rstn(~mac_reset[2]), .phy_resetn ( phy_resetn[2] ), .clk( pcs_pclk ), .tap_port ( 1'b0 ), - // SGMII AN + // PCS / SERDES health + .rx_lsm( 1'b1 ), // TODO: Fix LSM for SFP + .rx_cv_err ( sgmii_rx_cv_err[2] ), + .rx_disp_err( sgmii_rx_disp_err[2] ), + .rx_cdr_lol( sgmii_rx_cdr_lol[2] ), + .rx_los ( sgmii_rx_los_low[2] ), + // AN .phy_type(2'b01), // SX==1 - .an_disable( 1'b1 ), .pulse_1_6ms(pulse_1_6ms), .pulse_10ms(pulse_10ms), .fixed_speed(SGMII_SPEED_1GBIT), + .an_disable( 1'b0 ), .an_duplex( ), - .mode_100Mbit( mode_100Mbit[2] ), .phy_up( phy_up[2] ), + .mode_100Mbit( mode_100Mbit[2] ), // Switch I/F .tx_mode( tx_sw_mode2 ), .tx_f( tx_sc_done[2] ), - // PCS / SERDES health - .rx_lsm( 1'b1 ), // TODO: Fix LSM for SFP - .rx_cv_err ( sgmii_rx_cv_err[2] ), - .rx_disp_err( sgmii_rx_disp_err[2] ), - .rx_cdr_lol( sgmii_rx_cdr_lol[2] ), - .rx_los ( sgmii_rx_los_low[2] ), // PCS data I/F .rx_k( sgmii_rx_k[2] ), .rx_data( rx_data2 ), .tx_k( sgmii_tx_k[2] ), .tx_data( tx_data2 ), .tx_disp_correct( sgmii_tx_disp_correct[2] ), - // Flags and Interrupts - .keep( rx_mac_keep[2] ), // FCS .fcs_init( fcs_init[2] ), .fcs_enable( fcs_enable[2] ), .fcs_addr( fcs_addr2 ), .fcs_dout( fcs_din2 ), .fcs_din( fcs_dout2 ), - // SGMII RX / FIFO Write + // MAC RX / FIFO Write .rx_fifo_we( rx_sc_fifo_we[2] ), .rx_fifo_d(rx_sc_fifo_d2), .rx_error( rx_sc_error[2] ), + .rx_keep( rx_mac_keep[2] ), .rx_wr_done( rx_sc_wr_done[2] ), .rx_byte_cnt(rx2_byte_cnt), - // SGMII TX / FIFO Read + .rx_mode(), + // MAC TX / FIFO Read .tx_byte_cnt_i(tx2_byte_cnt), + .tx_src_sel(tx_src_sel2), .tx_fifo_re( tx_sc_fifo_re[2] ), .tx_fifo_d( tx_sw_fifo_d2 ), .tx_fifo_empty( tx_sw_fifo_empty[2]), @@ -1238,8 +1221,6 @@ mac mac_2( .rx_sample( ), .ipv4_pkt_start( ipv4_pkt_start[2] ), .trigger( ), - .rx_enet_bcast( rx_enet_bcast[2] ), - .rx_ipv4_arp( rx_ipv4_arp[2] ), .rx_k_m1( rx2_k_m1 ), .rx_k_m2( rx2_k_m2 ), .rx_k_m3( rx2_k_m3), @@ -1254,7 +1235,9 @@ mac mac_2( .dpr_ce( param_phy2_ce ), .dpr_di( param_phy2_din ), .dpr_do( param_phy2_dout ), - // Metrics and Interrupts + // Flags, Metrics, Interrupts, and Debug + .rx_enet_bcast( rx_enet_bcast[2] ), + .rx_ipv4_arp( rx_ipv4_arp[2] ), .mac_int( mac_int[2] ), .rx_sop( rx_sop[2] ), .rx_eop( rx_eop[2] ), @@ -1262,7 +1245,6 @@ mac mac_2( .tx_eop( tx_eop[2] ), .metrics_start ( metrics_start ), .metrics_d( metrics_d ), - // Debug .rx_active( mac_rx_active[2] ), .tx_active( mac_tx_active[2] ) ); @@ -1464,30 +1446,29 @@ fcs fcs_2( .dout( fcs_dout2 ) ); -// GEODSS SMA (MAC is bypassed) mac mac_3( .rstn( ~mac_reset[3] & ~sgmii_rx_los_low[3] ), .phy_resetn ( phy_resetn[3] ), .clk( pcs_pclk ), .tap_port ( 1'b0 ), - // SGMII AN + // PCS / SERDES health + .rx_lsm( sgmii_lsm_status[3] ), + .rx_cv_err ( sgmii_rx_cv_err[3] ), + .rx_disp_err( sgmii_rx_disp_err[3] ), + .rx_cdr_lol( sgmii_rx_cdr_lol[3] ), + .rx_los ( sgmii_rx_los_low[3] ), + // MAC AN .phy_type(2'b11), // SMA=3 - .an_disable(1'b1), .pulse_1_6ms(pulse_1_6ms), .pulse_10ms(pulse_10ms), .fixed_speed(SGMII_SPEED_1GBIT), + .an_disable(1'b1), .an_duplex( ), - .mode_100Mbit( mode_100Mbit[3] ), .phy_up( phy_up[3] ), + .mode_100Mbit( mode_100Mbit[3] ), // Switch I/F .tx_mode( tx_sw_mode3 ), .tx_f( tx_sc_done[3] ), - // PCS / SERDES health - .rx_lsm( sgmii_lsm_status[3] ), - .rx_cv_err ( sgmii_rx_cv_err[3] ), - .rx_disp_err( sgmii_rx_disp_err[3] ), - .rx_cdr_lol( sgmii_rx_cdr_lol[3] ), - .rx_los ( sgmii_rx_los_low[3] ), // PCS data I/F .rx_k( sgmii_rx_k[3] ), .rx_data( rx_data3 ), @@ -1495,21 +1476,23 @@ mac mac_3( .tx_data( tx_data3 ), .tx_disp_correct( sgmii_tx_disp_correct[3] ), // Flags and Interrupts - .keep( rx_mac_keep[3] ), + .rx_keep( rx_mac_keep[3] ), // TX FCS .fcs_init( fcs_init[3] ), .fcs_enable( fcs_enable[3] ), .fcs_addr( fcs_addr3 ), .fcs_dout( fcs_din3 ), .fcs_din( fcs_dout3 ), - // SGMII RX / FIFO Write + // MAC RX / FIFO Write .rx_fifo_we( rx_sc_fifo_we[3] ), .rx_fifo_d( rx_sc_fifo_d3 ), .rx_error( rx_sc_error[3] ), .rx_wr_done( rx_sc_wr_done[3] ), .rx_byte_cnt(rx3_byte_cnt), - // SGMII TX / FIFO Read + .rx_mode(), + // MAC TX / FIFO Read .tx_byte_cnt_i(tx3_byte_cnt), + .tx_src_sel(tx_src_sel3), .tx_fifo_re( tx_sc_fifo_re[3] ), .tx_fifo_d( tx_sw_fifo_d3 ), .tx_fifo_empty( tx_sw_fifo_empty[3] ), @@ -1517,8 +1500,6 @@ mac mac_3( .rx_sample( rx_sample[3] ), .ipv4_pkt_start( ipv4_pkt_start[3] ), .trigger( ), - .rx_enet_bcast( rx_enet_bcast[3] ), - .rx_ipv4_arp( rx_ipv4_arp[3] ), .rx_k_m1( rx3_k_m1 ), .rx_k_m2( rx3_k_m2 ), .rx_k_m3( rx3_k_m3), @@ -1533,7 +1514,9 @@ mac mac_3( .dpr_ce( ), .dpr_di( 9'h0), .dpr_do( ), - // Metrics and Interrupts + // Flags, Metrics, Interrupts, and Debug + .rx_enet_bcast( rx_enet_bcast[3] ), + .rx_ipv4_arp( rx_ipv4_arp[3] ), .mac_int( mac_int[3] ), .rx_sop( rx_sop[3] ), .rx_eop( rx_eop[3] ), @@ -1541,10 +1524,8 @@ mac mac_3( .tx_eop( tx_eop[3] ), .metrics_start ( ), .metrics_d ( 9'h0 ), - // Debug .rx_active( mac_rx_active[3] ), .tx_active( mac_tx_active[3] ) - ); @@ -2067,14 +2048,15 @@ always @(*) begin case (mdio_mux_sel) 2'b00: mdi = phy0_mdio; 2'b01: mdi = phy1_mdio; - 2'b10: mdi = phy2_mdio; // compile as 0 if GIGE_SHIELD isn't defined + 2'b10: mdi = phy2_mdio_i; // compile as 0 if GIGE_SHIELD isn't defined 2'b11: mdi = 1'b1; endcase end assign phy0_mdio = (mdo_oe & ~mdio_mux_sel[1] & ~mdio_mux_sel[0]) ? mdo : 1'bz; assign phy1_mdio = (mdo_oe & ~mdio_mux_sel[1] & mdio_mux_sel[0]) ? mdo : 1'bz; -assign phy2_mdio = (mdo_oe & mdio_mux_sel[1] & ~mdio_mux_sel[0]) ? mdo : 1'bz; +assign phy2_mdio_oe = (mdo_oe & mdio_mux_sel[1] & ~mdio_mux_sel[0]); +assign phy2_mdio_o = mdo; mdio mdio_0( .rstn(rstn), @@ -2208,8 +2190,6 @@ i2c i2c_0( /* * ext_sys_fifo delays and enables: -* we need the re delay since we need to generate a re pulse from the -* uart block, which is clocked at a slower rate. * we need the mdio_we delay since the fifo is clocked twice: high and low data * */ @@ -2222,12 +2202,12 @@ always@ ( posedge clk_10 or negedge rstn ) end else begin - cont_fifo_re_m1 <= uart_fifo_re | i2c_fifo_re; + cont_fifo_re_m1 <= i2c_fifo_re; cont_fifo_re_m2 <= cont_fifo_re_m1; end end -// create a single re pulse since uart runs slow. +// create a single re pulse assign i_cont_fifo_re = cont_fifo_re_m1 & ~cont_fifo_re_m2; assign bin_to_ascii_we = mdio_rd_we | cont_rd_we; @@ -2235,7 +2215,7 @@ assign bin_to_ascii_d_in = read_fifo_mux_sel ? mdio_rd : cont_rd; /* * Input: MDIO writes - * Output: UART/I2C read FIFO + * Output: I2C read FIFO */ bin_to_ascii bin_to_ascii_0( .rstn( rstn ), @@ -2255,7 +2235,7 @@ bin_to_ascii bin_to_ascii_0( /* * Input: bin_to_ascii - * Output: I2C or UART read + * Output: I2C read */ sync_fifo ext_sys_fifo_0( .rstn( rstn ), @@ -2342,20 +2322,36 @@ assign led[2] = phy_up[1]; assign pe5 = phy1_gpio[1]; assign pg5 = 1'bz; assign pe3 = fpga_gpio; - + +`ifdef SHIELD_GIGE_SMA + assign pa[0] = phy2_mdc; + assign pa[1] = phy2_mdio_oe ? phy2_mdio_o : 1'bz; + assign phy2_mdio_i = pa[1]; + assign pa[2] = phy2_resetn; +`else + assign phy2_mdio_i = 1'b0; +`endif + `ifdef SHIELD_SFP_SMA - // SFP UART testing assign uart_rxd = ph3; assign ph4 = uart_txd; + assign sfp_los = pa[1]; + assign pa[2] = sfp_rate_select; + assign sfp_pres_n = pa[3]; + assign pa[4] = sfp_i2c_scl; + assign sfp_tx_fault = pa[5]; + assign pa[6] = sfp_tx_disable; + assign sfp_i2c_sda = pa[7]; + // SFP LEDS - assign sfp_led1 = !sfp_pres_n; - assign sfp_led2 = !sfp_tx_fault; - assign sfp_led3 = !sfp_los; - assign sfp_led4 = !pcs_error[2]; - assign sfp_led5 = phy_up[0]; - assign sfp_led6 = !mac_tx_active[0]; + assign ard_txd3 = !sfp_pres_n; // LED1 + assign ard_rxd3 = !sfp_tx_fault; // LED2 + assign ard_txd2 = !sfp_los; // LED3 + assign ard_rxd2 = !pcs_error[2]; // LED4 + assign ard_txd1 = phy_up[0]; // LED5 + assign ard_rxd1 = !mac_tx_active[0];// LED6 `endif assign fpga_int = pcs_error[2] | pcs_error[3]; -- cgit v1.2.3-8-gadcc