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Diffstat (limited to 'manufacturer/lattice/ecp5um/source/top.v')
| -rw-r--r-- | manufacturer/lattice/ecp5um/source/top.v | 2432 |
1 files changed, 2432 insertions, 0 deletions
diff --git a/manufacturer/lattice/ecp5um/source/top.v b/manufacturer/lattice/ecp5um/source/top.v new file mode 100644 index 0000000..4944bae --- /dev/null +++ b/manufacturer/lattice/ecp5um/source/top.v @@ -0,0 +1,2432 @@ +/* + * top.v + * + * Copyright (C) 2018, 2019, 2020 Mind Chasers Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * Private Island Top for Darsena / ECP5UM + * + */ + +module top( + input rstn, + + // REFCLK + input refclkp_d0, refclkn_d0, + input refclkp_d1, refclkn_d1, + + // SGMII0 + input sgmii0_hdinp, + input sgmii0_hdinn, + output sgmii0_hdoutp, + output sgmii0_hdoutn, + + // SGMII1 + input sgmii1_hdinp, + input sgmii1_hdinn, + output sgmii1_hdoutp, + output sgmii1_hdoutn, + + // SGMII2 + input sgmii2_hdinp, + input sgmii2_hdinn, + output sgmii2_hdoutp, + output sgmii2_hdoutn, + + // SGMII3 + input sgmii3_hdinp, + input sgmii3_hdinn, + output sgmii3_hdoutp, + output sgmii3_hdoutn, + + // PHYs + output phy_mdc, + + output phy0_resetn, + inout phy0_mdio, + input [1:0] phy0_gpio, + input phy0_intn, + + output phy1_resetn, + inout phy1_mdio, + input [1:0] phy1_gpio, + input phy1_intn, + +`ifdef SHIELD_GIGE_SMA + output phy2_resetn, + output phy2_mdc, + inout phy2_mdio, +`elsif SHIELD_SFP_SMA + input sfp_tx_fault, // high indicates a laser fault of some kind. + output sfp_tx_disable, // high disables the transmitter + input sfp_pres_n, // (mod-def 0): grounded by the module to indicate that the module is present) + inout sfp_i2c_sda, // (mod-def 2) + output sfp_i2c_scl, // (mod-def 1) + input sfp_los, // Low indicates normal operation + output sfp_rate_select, // high for full bandwidth +`endif + + // Microcontroller SPI and bit banging + input spi_cs, + input spi_clk, + output spi_miso, + input spi_mosi, + output fpga_int, + input fpga_gpio, + + // I2C + inout i2c_scl, + inout i2c_sda, + + // K02 UART + input uart_txd, + output uart_rxd, + +`ifdef DARSENA_V02 + output fpga_jtag_e, + // FTDI UART signals muxed with JTAG + input ftdi_tck_txd, + output ftdi_tdi_rxd, +`endif + + output [2:0] led, + + output ard_sda, + output ard_scl, + +`ifdef SHIELD_SFP_SMA + output sfp_led1, // TXD3 + output sfp_led2, // RXD3 + output sfp_led3, // TXD2 + output sfp_led4, // RXD2 + output sfp_led5, // TXD1 + output sfp_led6, // RXD1 +`endif + + input pe0, // + output pe1, // + output pe3, + output pe4, + output pe5, + output pg5, + input ph3, // UART RX for SFP Testing + output ph4, // UART TX for SFP Testing + inout [9:0] pa +); + +`include "directives.v" +`include "sgmii_params.v" +`include "ethernet_params.v" + +`ifdef DARSENA_V01 + wire fb_clk; + wire fb_ale; + wire fb_oen; + wire fb_rwn; + wire fb_csn; + wire fb_cregs_sel; + wire [9:0] fb_ad; +`endif + +/* PARAMS */ +localparam MDIO_ROM_ADDR_SZ = 7; + +/* nets and variables */ + +// clocks +wire clk_slow, clk_1_25, clk_10, clk_20; +wire clk_100; +wire refclko; + +// pulses +wire pulse_10ms, pulse_1_6ms; + +// misc resets +wire [3:0] phy_resetn; // bit[0] will get pruned out for now +wire [3:0] mac_reset; + +// dcu resets +wire [1:0] pcs_rst_dual; +wire [1:0] serdes_rst_dual; +wire [1:0] tx_serdes_rst; + +// channel resets +wire [3:0] rx_pcs_rst; +wire [3:0] rx_serdes_rst; +wire [3:0] tx_pcs_rst; + +// MDIO controller and driver +wire mdio_cont_work_start, mdio_cont_work_run; +wire mdio_cont_work_done; +wire [MDIO_ROM_ADDR_SZ-1:0] mdio_routine_addr; +wire [1:0] mdio_mux_sel; +wire mdio_done, mdo_oe; +wire mdo; +reg mdi; +wire [15:0] mdio_wd; +wire [15:0] mdio_rd; +wire [4:0] mdio_reg_addr; +wire mdio_ld, mdio_run; +wire mdio_rwn; +wire bin_to_ascii_run; + +// MDIO Data block +wire [MDIO_ROM_ADDR_SZ-1:0] rom_a; +wire [7:0] rom_d; +wire [4:0] mdio_reg_addr_set; +wire [7:0] mdio_w_data_h_set, mdio_w_data_l_set; +wire [4:0] mdio_page_set; + +// I2C +wire sda_oe, scl_oe, sda_o, scl_o; +wire i2c_fifo_priority; + +// UART +wire uart_rx_done; +wire read_fifo_we; +wire [8:0] fifo_r_d; +wire [6:0] d_uart_rx; + +// bin to ASCII +wire [15:0] bin_to_ascii_d_in; +wire [6:0] cont_rd; + +// PCS, mac +wire pcs_pclk; +wire [1:0] pll_lol; +wire sgmii_rx_k[0:3], sgmii_tx_k[0:3]; +wire sgmii_tx_disp_correct[0:3]; +wire sgmii_rx_cv_err[0:3], sgmii_rx_disp_err[0:3], sgmii_rx_cdr_lol[0:3]; +wire sgmii_lsm_status[0:3], sgmii_rx_los_low[0:3]; +wire [7:0] rx_data0, rx_data1, rx_data2, rx_data3; +wire [7:0] tx_data0, tx_data1, tx_data2, tx_data3; +wire [6:0] read_fifo_d_i; +wire [3:0] rx_sample; +wire [3:0] pcs_error; + +// ipv4 +wire [3:0] ipv4_pkt_start; +wire [3:0] ipv4_pkt_complete; + +reg cont_fifo_re_m1, cont_fifo_re_m2; +wire cont_fifo_empty; +wire i2c_fifo_re, uart_fifo_re; +wire i2c_cont_we, i2c_cont_done; +wire i_cont_fifo_re; +wire bin_to_ascii_we, mdio_rd_we, cont_rd_we; +wire [3:0] phy_up; + +// Interrupts +wire [6:0] int_do; +wire [3:0] mac_int; +wire int_sel; + +// Common Internal Memory Bus +wire[10:0] mem_addr; +wire [8:0] mem_d_i; +reg [8:0] mem_d_o; +wire mem_we, mem_oe; +wire [4:0] mem_do_mux_sel; + +// DPRAM +wire [10:0] param_phy0_addr, param_phy1_addr, param_phy2_addr, param_phy3_addr; +wire [8:0] param_phy0_din, param_phy1_din, param_phy2_din, param_phy3_din; +wire [8:0] param_phy0_dout, param_phy1_dout, param_phy2_dout, param_phy3_dout; +wire param_phy0_ce, param_phy1_ce, param_phy2_ce, param_phy3_ce; +wire param_phy0_we, param_phy1_we, param_phy2_we, param_phy3_we; +wire [8:0] param_ram_0_do, param_ram_1_do, param_ram_2_do, param_ram_3_do; + +wire [7:0] i2c_d_o; +wire [8:0] micro_fifo_do; +wire sys_mem_rx_ce, sys_mem_tx_ce, sys_mem_ptrs_sel; +wire [3:0] param_sel; + +// drop_fifos and filter +wire rx0_k_m1, rx0_k_m2, rx0_k_m3, rx0_k_m4; +wire [7:0] rx0_data_m1, rx0_data_m2, rx0_data_m3, rx0_data_m4; + +wire rx1_k_m1, rx1_k_m2, rx1_k_m3, rx1_k_m4; +wire [7:0] rx1_data_m1, rx1_data_m2, rx1_data_m3, rx1_data_m4; + +wire rx2_k_m1, rx2_k_m2, rx2_k_m3, rx2_k_m4; +wire [7:0] rx2_data_m1, rx2_data_m2, rx2_data_m3, rx2_data_m4; + +wire rx3_k_m1, rx3_k_m2, rx3_k_m3, rx3_k_m4; +wire [7:0] rx3_data_m1, rx3_data_m2, rx3_data_m3, rx3_data_m4; + +wire [3:0] rx_mac_keep; +wire [3:0] rx_sc_wr_done; + +// drop filter outputs +wire rx_df_fifo_we_01, rx_df_fifo_we_02, rx_df_fifo_we_03; +wire rx_df_fifo_we_10, rx_df_fifo_we_12, rx_df_fifo_we_13; +wire rx_df_fifo_we_20, rx_df_fifo_we_21, rx_df_fifo_we_23, rx_df_fifo_we_2u; +wire rx_df_fifo_we_30, rx_df_fifo_we_31, rx_df_fifo_we_32; +wire rx_df_fifo_we_u2; + +wire [8:0] rx_df_fifo_d_01, rx_df_fifo_d_02, rx_df_fifo_d_03; +wire [8:0] rx_df_fifo_d_10, rx_df_fifo_d_12, rx_df_fifo_d_13; +wire [8:0] rx_df_fifo_d_20, rx_df_fifo_d_21, rx_df_fifo_d_23, rx_df_fifo_d_2u; +wire [8:0] rx_df_fifo_d_30, rx_df_fifo_d_31, rx_df_fifo_d_32; +wire [8:0] rx_df_fifo_d_u2; + +// pkt filter +wire [3:0] trigger; +wire [3:0] rx_enet_bcast; +wire [3:0] rx_ipv4_arp; +wire rx_pf_keep_01; +wire rx_pf_keep_02; +wire rx_pf_keep_03; +wire rx_pf_keep_10; +wire rx_pf_keep_12; +wire rx_pf_keep_13; +wire rx_pf_keep_20; +wire rx_pf_keep_21; +wire rx_pf_keep_23; +wire rx_pf_keep_2u; +wire rx_pf_keep_30; +wire rx_pf_keep_31; +wire rx_pf_keep_32; +wire rx_pf_keep_u2; + +// rx_fifos +wire [3:0] rx_sc_fifo_we; +wire rx_sw_fifo_re_01, rx_sw_fifo_re_02, rx_sw_fifo_re_03; +wire rx_sf_fifo_empty_01, rx_sf_fifo_empty_02, rx_sf_fifo_empty_03; +wire rx_sw_fifo_re_10, rx_sw_fifo_re_12, rx_sw_fifo_re_13; +wire rx_sf_fifo_empty_10, rx_sf_fifo_empty_12, rx_sf_fifo_empty_13; +wire rx_sw_fifo_re_20, rx_sw_fifo_re_21, rx_sw_fifo_re_23, rx_sw_fifo_re_2u; +wire rx_sf_fifo_empty_20, rx_sf_fifo_empty_21, rx_sf_fifo_empty_23, rx_sf_fifo_empty_2u; +wire rx_sw_fifo_re_30, rx_sw_fifo_re_31, rx_sw_fifo_re_32; +wire rx_sf_fifo_empty_30, rx_sf_fifo_empty_31, rx_sf_fifo_empty_32; +wire rx_sw_fifo_re_u2, rx_uc_fifo_empty_u2; +wire [8:0] rx_sc_fifo_d0, rx_sc_fifo_d1, rx_sc_fifo_d2, rx_sc_fifo_d3; +wire [8:0] rx_sf_fifo_d_01, rx_sf_fifo_d_02, rx_sf_fifo_d_03; +wire [8:0] rx_sf_fifo_d_10, rx_sf_fifo_d_12, rx_sf_fifo_d_13; +wire [8:0] rx_sf_fifo_d_20, rx_sf_fifo_d_21, rx_sf_fifo_d_23, rx_sf_fifo_d_2u; +wire [8:0] rx_sf_fifo_d_30, rx_sf_fifo_d_31, rx_sf_fifo_d_32; +wire [8:0] rx_uc_fifo_d_u2; +wire rx_sf_almost_full_01, rx_sf_almost_full_02, rx_sf_almost_full_03; +wire rx_sf_almost_full_10, rx_sf_almost_full_12, rx_sf_almost_full_13; +wire rx_sf_almost_full_20, rx_sf_almost_full_21, rx_sf_almost_full_23; + + +// between switch and mac +wire [8:0] tx_sw_fifo_d0, tx_sw_fifo_d1, tx_sw_fifo_d2, tx_sw_fifo_d3, tx_sw_fifo_du; +wire [3:0] tx_sc_fifo_re; +wire tx_uc_fifo_re; +wire [3:0] tx_sw_fifo_empty; +wire tx_sw_fifo_we; + +wire [2:0] tx_sw_mode0, tx_sw_mode1, tx_sw_mode2, tx_sw_mode3; +wire tx_sw_modeu; +wire [3:0] tx_sc_done; + +// 100 Mbit +wire[3:0] mode_100Mbit; + +// Flexbus +wire fb_ad_oe; +wire[9:0] fb_ad_o; +reg[9:0] fb_d; + +wire pkt_filter_sel_01, pkt_filter_sel_02, pkt_filter_sel_03; +wire pkt_filter_sel_10, pkt_filter_sel_12, pkt_filter_sel_13; +wire pkt_filter_sel_20, pkt_filter_sel_21, pkt_filter_sel_23, pkt_filter_sel_2u; +wire pkt_filter_sel_u2; + +// FCS +wire [1:0] fcs_addr0, fcs_addr1, fcs_addr2, fcs_addr3; +wire [7:0] fcs_din0, fcs_din1, fcs_din2, fcs_din3; +wire [7:0] fcs_dout0, fcs_dout1, fcs_dout2, fcs_dout3; +wire[3:0] fcs_init, fcs_enable; + +// half FIFO / DPRAM interface for uP +wire hfifo_we, hfifo_re; +wire [8:0] hfifo_tx_d, hfifo_rx_d; +wire hfifo_empty; +wire micro_fifo_int; +wire tx_uc_block; + +// SCI +wire[1:0] sci_sel_dual; +wire[3:0] sci_sel_ch; +wire[7:0] sci_rddata0, sci_rddata1 ; +wire[1:0] sci_int; + +// Metrics +wire tx_custom, metrics_start; +wire [8:0] metrics_d; + +// Network Debug & Metrics +reg [3:0] rx_active, tx_active; +wire [3:0] mac_rx_active; +wire [3:0] drop_rx0_active, drop_rx1_active, drop_rx2_active, drop_rx3_active; +wire [3:0] sync_rx0_active, sync_rx1_active, sync_rx2_active, sync_rx3_active; +wire [3:0] mac_tx_active; +wire [3:0] rx_sc_error; +wire [3:0] rx_eop, rx_sop; +wire [3:0] tx_eop, tx_sop; +wire [10:0] rx0_byte_cnt, rx1_byte_cnt, rx2_byte_cnt, rx3_byte_cnt; +wire [10:0] tx0_byte_cnt, tx1_byte_cnt, tx2_byte_cnt, tx3_byte_cnt; + +// Debug LEDs +reg lsm_status, rx_cdr_lol, rx_los_low; + +// Misc Debug +wire ext_sci_int; + +/**************************** + * + * Logic Begins Below + * + ***************************/ + +/* Lattice requires GSR to be in top-level module and be named GSR_INST */ +GSR GSR_INST(.GSR(rstn)); +PUR PUR_INST(.PUR(1'b1)); + +assign phy_mdc = clk_10; + +assign phy0_resetn = phy_resetn[0]; +assign phy1_resetn = phy_resetn[1]; + +`ifdef SHIELD_GIGE_SMA + assign phy2_resetn = phy_resetn[2]; + assign phy2_mdc = clk_10; +`elsif SHIELD_SFP_SMA + assign sfp_tx_disable = 1'b0; + assign sfp_i2c_scl = 1'b1; + assign sfp_rate_select = 1'b1; +`endif + + +/* + * Clocks derived from the internal OSCG + */ +clk_gen clk_gen_0( + .rstn( rstn ), + .clk_10( clk_10 ), + .clk_5( ), + .clk_2_5( ), + .clk_1_25( clk_1_25 ), + .clk_slow( clk_slow ) +); + + +/* +* main controller +* +* controls worker blocks +* interfaces with uC via I2C / UART +* +*/ +controller #(.ADDR_SZ( MDIO_ROM_ADDR_SZ ))controller_0 +( + .rstn( rstn ), + .clk( clk_10 ), + .init(1'b1), + .pulse_100ms( 1'b0 ), + // PCS status lines + .pcs_rx_error( pcs_error ), + .pll_lol( pll_lol ), + // link status + .port_up( phy_up ), +// .sfp_los(sfp_los), + // mdio_controller interface + .mdio_cont_start(mdio_cont_work_start), + .mdio_cont_done(mdio_cont_work_done), + .mdio_routine_addr( mdio_routine_addr ), + .mdio_run( mdio_run ), + // mdio_data params + .mdio_page( mdio_page_set ), + .mdio_reg_addr( mdio_reg_addr_set ), + .mdio_w_data_h( mdio_w_data_h_set ), + .mdio_w_data_l( mdio_w_data_l_set ), + // bin_to_ascii interface + .bin_to_ascii_run( bin_to_ascii_run ), + // ext_sys_fifo interface: controller to external I/F FIFO + .fifo_mux_sel( read_fifo_mux_sel ), + .fifo_we( cont_rd_we ), + .read_fifo_d_o( cont_rd ), + // i2c interface + .i2c_rx_we ( i2c_cont_we ), + .i2c_rx_done ( i2c_cont_done ), + .i2c_d_in( i2c_d_o ), + // reset and config + .pcs_rst_dual( pcs_rst_dual ), + .serdes_rst_dual( serdes_rst_dual ), + .tx_serdes_rst( tx_serdes_rst ), + .phy_resetn( phy_resetn ), + .mac_reset( mac_reset ), + .tx_pcs_rst( tx_pcs_rst ), + .rx_serdes_rst( rx_serdes_rst ), + .rx_pcs_rst( rx_pcs_rst ), + .mdio_mux_sel( mdio_mux_sel ), + .i2c_fifo_priority( i2c_fifo_priority ), + // TX custom packet + .tx_metrics( tx_custom ) + +); + +/* + * Controls the routing of data and transmit modes + */ +switch switch_0( + .rstn( rstn ), + .clk( pcs_pclk ), + // PHY status + .phy_up( phy_up ), + .mode_100Mbit ( mode_100Mbit ), + // FIFO input data from RX FIFOs + .rx_d_01( rx_sf_fifo_d_01 ), + .rx_d_02( rx_sf_fifo_d_02 ), + .rx_d_03( rx_sf_fifo_d_03 ), + .rx_d_10( rx_sf_fifo_d_10 ), + .rx_d_12( rx_sf_fifo_d_12 ), + .rx_d_13( rx_sf_fifo_d_13 ), + .rx_d_20( rx_sf_fifo_d_20 ), + .rx_d_21( rx_sf_fifo_d_21 ), + .rx_d_23( rx_sf_fifo_d_23 ), + .rx_d_2u( rx_sf_fifo_d_2u ), + .rx_d_30( rx_sf_fifo_d_30 ), + .rx_d_31( rx_sf_fifo_d_31 ), + .rx_d_32( rx_sf_fifo_d_32 ), + .rx_d_u2( rx_uc_fifo_d_u2 ), + // RX FIFO read enables + .rx_fifo_re_01( rx_sw_fifo_re_01 ), + .rx_fifo_re_02( rx_sw_fifo_re_02 ), + .rx_fifo_re_03( rx_sw_fifo_re_03 ), + .rx_fifo_re_10( rx_sw_fifo_re_10 ), + .rx_fifo_re_12( rx_sw_fifo_re_12 ), + .rx_fifo_re_13( rx_sw_fifo_re_13 ), + .rx_fifo_re_20( rx_sw_fifo_re_20 ), + .rx_fifo_re_21( rx_sw_fifo_re_21 ), + .rx_fifo_re_23( rx_sw_fifo_re_23 ), + .rx_fifo_re_2u( rx_sw_fifo_re_2u ), + .rx_fifo_re_30( rx_sw_fifo_re_30 ), + .rx_fifo_re_31( rx_sw_fifo_re_31 ), + .rx_fifo_re_32( rx_sw_fifo_re_32 ), + .rx_fifo_re_u2( rx_sw_fifo_re_u2 ), + // RX FIFO Empty flags + .rx_fifo_empty_01( rx_sf_fifo_empty_01 ), + .rx_fifo_empty_02( rx_sf_fifo_empty_02 ), + .rx_fifo_empty_03( rx_sf_fifo_empty_03 ), + .rx_fifo_empty_10( rx_sf_fifo_empty_10 ), + .rx_fifo_empty_12( rx_sf_fifo_empty_12 ), + .rx_fifo_empty_13( rx_sf_fifo_empty_13 ), + .rx_fifo_empty_20( rx_sf_fifo_empty_20 ), + .rx_fifo_empty_21( rx_sf_fifo_empty_21 ), + .rx_fifo_empty_23( rx_sf_fifo_empty_23 ), + .rx_fifo_empty_2u( rx_sf_fifo_empty_2u ), + .rx_fifo_empty_30( rx_sf_fifo_empty_30 ), + .rx_fifo_empty_31( rx_sf_fifo_empty_31 ), + .rx_fifo_empty_32( rx_sf_fifo_empty_32 ), + .rx_fifo_empty_u2( rx_uc_fifo_empty_u2 ), + // RX Byte Count + .rx_wr_done(rx_sc_wr_done), + .rx0_byte_cnt(rx0_byte_cnt), + .rx1_byte_cnt(rx1_byte_cnt), + .rx2_byte_cnt(rx2_byte_cnt), + .rx3_byte_cnt(rx3_byte_cnt), + // TX FIFO output from internal muxes + .tx_d0( tx_sw_fifo_d0), + .tx_d1( tx_sw_fifo_d1 ), + .tx_d2( tx_sw_fifo_d2 ), + .tx_d3( tx_sw_fifo_d3 ), + .tx_du( tx_sw_fifo_du ), + // TX FIFO read enable inputs (need to route to RX output FIFOs) + .tx_fifo_re( tx_sc_fifo_re ), + .tx_fifo_we_u ( tx_sw_fifo_we ), + // TX FIFO Empty Flags (need to route to RX output FIFOs) + .tx_fifo_empty( tx_sw_fifo_empty ), + // TX modes for the PHYs and uc + .tx_mode0( tx_sw_mode0 ), + .tx_mode1( tx_sw_mode1 ), + .tx_mode2( tx_sw_mode2 ), + .tx_mode3( tx_sw_mode3 ), + .tx_modeu( tx_modeu ), + // TX byte cnt + .tx0_byte_cnt(tx0_byte_cnt), + .tx1_byte_cnt(tx1_byte_cnt), + .tx2_byte_cnt(tx2_byte_cnt), + .tx3_byte_cnt(tx3_byte_cnt), + // TX state machine done flag + .tx_f( tx_sc_done ), + // TX custom packet + .tx_custom ( tx_custom ) +); + + +/* + * RX and TX controller logic tied to PCS/SGMII protocol + */ +mac mac_0( + .rstn( ~mac_reset[0] ), + .phy_resetn ( phy_resetn[0] ), + .clk( pcs_pclk ), + .tap_port ( 1'b0 ), + // AN + .phy_type(2'b00), // SGMII=0 + .an_disable( 1'b0 ), + .pulse_1_6ms(pulse_1_6ms), + .pulse_10ms(pulse_10ms), + .fixed_speed(SGMII_SPEED_AN), + .an_duplex( ), + .mode_100Mbit( mode_100Mbit[0] ), + .phy_up( phy_up[0] ), + // Switch I/F + .tx_mode( tx_sw_mode0 ), + .tx_f( tx_sc_done[0] ), + // PCS / SERDES health + .rx_lsm( sgmii_lsm_status[0] ), + .rx_cv_err ( sgmii_rx_cv_err[0] ), + .rx_disp_err( sgmii_rx_disp_err[0] ), + .rx_cdr_lol( sgmii_rx_cdr_lol[0] ), + .rx_los ( sgmii_rx_los_low[0] ), + // PCS data I/F + .rx_k( sgmii_rx_k[0] ), + .rx_data( rx_data0 ), + .tx_k( sgmii_tx_k[0] ), + .tx_data( tx_data0 ), + .tx_disp_correct( sgmii_tx_disp_correct[0] ), + // Flags and Interrupts + .keep( rx_mac_keep[0] ), + // TX FCS + .fcs_init( fcs_init[0] ), + .fcs_enable( fcs_enable[0] ), + .fcs_addr( fcs_addr0 ), + .fcs_dout( fcs_din0 ), + .fcs_din( fcs_dout0 ), + // SGMII RX / FIFO Write + .rx_fifo_we( rx_sc_fifo_we[0] ), + .rx_fifo_d( rx_sc_fifo_d0 ), + .rx_error( rx_sc_error[0] ), + .rx_wr_done( rx_sc_wr_done[0] ), + .rx_byte_cnt(rx0_byte_cnt), + // SGMII TX / FIFO Read + .tx_byte_cnt_i(tx0_byte_cnt), + .tx_fifo_re( tx_sc_fifo_re[0] ), + .tx_fifo_d( tx_sw_fifo_d0 ), + .tx_fifo_empty( tx_sw_fifo_empty[0] ), + // Packet Filter + .rx_sample( rx_sample[0] ), + .ipv4_pkt_start( ipv4_pkt_start[0] ), + .trigger( ), + .rx_enet_bcast( rx_enet_bcast[0] ), + .rx_ipv4_arp( rx_ipv4_arp[0] ), + .rx_k_m1( rx0_k_m1 ), + .rx_k_m2( rx0_k_m2 ), + .rx_k_m3( rx0_k_m3), + .rx_k_m4( rx0_k_m4 ), + .rx_data_m1( rx0_data_m1 ), + .rx_data_m2( rx0_data_m2 ), + .rx_data_m3( rx0_data_m3), + .rx_data_m4( rx0_data_m4 ), + // Param RAM + .dpr_ad( param_phy0_addr ), + .dpr_we( param_phy0_we ), + .dpr_ce( param_phy0_ce ), + .dpr_di( param_phy0_din ), + .dpr_do( param_phy0_dout ), + // Metrics and Interrupts + .mac_int( mac_int[0] ), + .rx_sop( rx_sop[0] ), + .rx_eop( rx_eop[0] ), + .tx_sop( tx_sop[0] ), + .tx_eop( tx_eop[0] ), + .metrics_start ( ), + .metrics_d ( 9'h0 ), + .rx_active( mac_rx_active[0] ), + .tx_active( mac_tx_active[0] ) +); + + +ipv4_rx ipv4_rx_0( + .rstn( rstn ), + .clk( pcs_pclk ), + // control + .phy_resetn ( phy_resetn[0] ), + .phy_up( phy_up[0] ), + // packet data + .pkt_start( ipv4_pkt_start[0] ), + .rx_eop( rx_eop[0] ), + .rx_data_m1( rx0_data_m1 ), + .rx_data_m2( rx0_data_m2 ), + .rx_data_m3( rx0_data_m3), + .rx_data_m4( rx0_data_m4 ), + // flags + .pkt_complete(ipv4_pkt_complete[0]), + .trigger_src_addr( ), + .trigger_dst_addr( trigger[0] ), + .keep( ) + ); + + +pkt_filter pkt_filter_01( + .rstn( rstn ), + .clk( pcs_pclk ), + // input for programming + .sel( pkt_filter_sel_01 ), + .we( mem_we ), + .addr( mem_addr[3:0] ), + .d_in( mem_d_i[7:0] ), + // registered data + .rx_data_m1( rx0_data_m1 ), + .rx_data_m2( rx0_data_m2 ), + .rx_data_m3( rx0_data_m3), + .rx_data_m4( rx0_data_m4 ), + // filter + .new_frame ( rx_sop[0] ), + .block( 1'b0 ), + .invert( 1'b1 ), + .trigger( trigger[0] ), + .keep( rx_pf_keep_01 ) +); + +drop_fifo drop_fifo_01( + .rstn( rstn ), + .clk ( pcs_pclk ), + .enable( 1'b1 ), + // control + .keep ( rx_pf_keep_01 | rx_mac_keep[0] ), + .passthrough( 1'b0 ), + // input + .we_in( rx_sc_fifo_we[0] ), + .wr_done( rx_sc_wr_done[0] ), + .d_in( rx_sc_fifo_d0 ), + // output + .we_out( rx_df_fifo_we_01 ), + .d_out( rx_df_fifo_d_01 ), + // debug + .active( drop_rx0_active[1] ) +); + +sync_fifo sync_fifo_rx_01( + .rstn( rstn ), + .clk ( pcs_pclk ), + // input + .we ( rx_df_fifo_we_01 & phy_up[1] ), + .d_in ( rx_df_fifo_d_01 ), + // output + .re ( rx_sw_fifo_re_01 ), + .d_out( rx_sf_fifo_d_01 ), + .empty( rx_sf_fifo_empty_01 ), + .almost_full( ), + .reset_ptrs( 1'b0 ), + // debug + .active( sync_rx0_active[1] ) +); + +pkt_filter pkt_filter_02( + .rstn( rstn ), + .clk( pcs_pclk ), + // input for programming + .sel( pkt_filter_sel_02 ), + .we( mem_we ), + .addr( mem_addr[3:0] ), + .d_in( mem_d_i[7:0] ), + // registered data + .rx_data_m1( rx0_data_m1 ), + .rx_data_m2( rx0_data_m2 ), + .rx_data_m3( rx0_data_m3), + .rx_data_m4( rx0_data_m4 ), + // filter + .new_frame ( rx_sop[0] ), + .block( rx_sf_almost_full_02 ), + .invert(1'b1), + .trigger(trigger[0]), + .keep( rx_pf_keep_02 ) +); + +drop_fifo drop_fifo_02( + .rstn( rstn ), + .clk ( pcs_pclk ), + .enable( 1'b1 ), + // control + .keep ( rx_pf_keep_02 | rx_mac_keep[0] ), + .passthrough( 1'b0 ), + // input + .we_in( rx_sc_fifo_we[0] ), + .wr_done( rx_sc_wr_done[0] ), + .d_in( rx_sc_fifo_d0 ), + // output + .we_out( rx_df_fifo_we_02 ), + .d_out( rx_df_fifo_d_02 ), + .active( drop_rx0_active[2] ) + ); + +sync_fifo sync_fifo_rx_02( + .rstn( rstn ), + .clk ( pcs_pclk ), + // input + .we ( rx_df_fifo_we_02 & phy_up[2] ), + .d_in ( rx_df_fifo_d_02 ), + // output + .re ( rx_sw_fifo_re_02 ), + .d_out( rx_sf_fifo_d_02 ), + .empty( rx_sf_fifo_empty_02 ), + .almost_full( rx_sf_almost_full_02 ), + .reset_ptrs( 1'b0 ), + // debug + .active(sync_rx0_active[2] ) +); + + +pkt_filter pkt_filter_03( + .rstn( rstn ), + .clk( pcs_pclk ), + // input for programming + .sel( pkt_filter_sel_03 ), + .we( mem_we ), + .addr( mem_addr[3:0] ), + .d_in( mem_d_i[7:0] ), + // registered data + .rx_data_m1( rx0_data_m1 ), + .rx_data_m2( rx0_data_m2 ), + .rx_data_m3( rx0_data_m3), + .rx_data_m4( rx0_data_m4 ), + // filter + .new_frame ( rx_sop[0] ), + .block( rx_sf_almost_full_03 ), + .invert( 1'b0 ), + .trigger( trigger[0] ), + .keep( rx_pf_keep_03 ) + ); + +drop_fifo drop_fifo_03( + .rstn( rstn ), + .clk ( pcs_pclk ), + .enable( 1'b0 ), + // control + .keep ( rx_pf_keep_03 | rx_mac_keep[0] ), + .passthrough( 1'b0 ), + // input + .we_in( rx_sc_fifo_we[0] ), + .wr_done( rx_sc_wr_done[0] ), + .d_in( rx_sc_fifo_d0 ), + // output + .we_out( rx_df_fifo_we_03 ), + .d_out( rx_df_fifo_d_03 ), + .active( drop_rx0_active[3] ) + ); + +sync_fifo sync_fifo_rx_03( + .rstn( rstn ), + .clk ( pcs_pclk ), + // input + .we ( rx_df_fifo_we_03 & phy_up[3] ), + .d_in ( rx_df_fifo_d_03 ), + // output + .re ( rx_sw_fifo_re_03 ), + .d_out( rx_sf_fifo_d_03 ), + .empty( rx_sf_fifo_empty_03 ), + .almost_full( rx_sf_almost_full_03 ), + .reset_ptrs( 1'b0 ), + // debug + .active( sync_rx0_active[3] ) + ); + +fcs fcs_0( + .rstn( rstn ), + .clk( pcs_pclk ), + .init( fcs_init[0] ), + .enable( fcs_enable[0] ), + .addr( fcs_addr0 ), + .din( fcs_din0 ), + .dout( fcs_dout0 ) +); + +/* + * Param RAM + */ +dpram param_ram_0( + .rstn(rstn), + .a_clk(clk_10), + .a_clk_e(param_sel[0]), + .a_we(mem_we), + .a_oe(mem_oe), + .a_addr(mem_addr), + .a_din(mem_d_i[8:0]), + .a_dout(param_ram_0_do), + // port B + .b_clk( pcs_pclk), + .b_clk_e(param_phy0_ce), + .b_we(param_phy0_we), + .b_oe( 1'b1 ), + .b_addr( param_phy0_addr ), + .b_din( param_phy0_dout ), + .b_dout( param_phy0_din ) + ); + +mac mac_1( + .rstn( ~mac_reset[1] ), + .phy_resetn ( phy_resetn[1] ), + .clk( pcs_pclk ), + .tap_port ( 1'b0 ), + // AN + .phy_type(2'b00), // SGMII==0 + .an_disable( 1'b0 ), + .pulse_1_6ms(pulse_1_6ms), + .pulse_10ms(pulse_10ms), + .fixed_speed(SGMII_SPEED_AN), + .an_duplex( ), + .mode_100Mbit( mode_100Mbit[1] ), + .phy_up( phy_up[1] ), + // Switch I/F + .tx_mode( tx_sw_mode1 ), + .tx_f( tx_sc_done[1] ), + // PCS / SERDES health + .rx_lsm( sgmii_lsm_status[1] ), + .rx_cv_err ( sgmii_rx_cv_err[1] ), + .rx_disp_err( sgmii_rx_disp_err[1] ), + .rx_cdr_lol( sgmii_rx_cdr_lol[1] ), + .rx_los ( sgmii_rx_los_low[1] ), + // PCS data I/F + .rx_k( sgmii_rx_k[1] ), + .rx_data( rx_data1 ), + .tx_k( sgmii_tx_k[1] ), + .tx_data( tx_data1 ), + .tx_disp_correct( sgmii_tx_disp_correct[1] ), + // Flags and Interrupts + .keep( rx_mac_keep[1] ), + // FCS + .fcs_init( fcs_init[1] ), + .fcs_enable( fcs_enable[1] ), + .fcs_addr( fcs_addr1 ), + .fcs_dout( fcs_din1 ), + .fcs_din( fcs_dout1 ), + // SGMII RX / FIFO Write + .rx_fifo_we( rx_sc_fifo_we[1] ), + .rx_fifo_d( rx_sc_fifo_d1 ), + .rx_error( rx_sc_error[1] ), + .rx_wr_done( rx_sc_wr_done[1] ), + .rx_byte_cnt(rx1_byte_cnt), + // SGMII TX / FIFO Read + .tx_byte_cnt_i(tx1_byte_cnt), + .tx_fifo_re( tx_sc_fifo_re[1] ), + .tx_fifo_d( tx_sw_fifo_d1 ), + .tx_fifo_empty( tx_sw_fifo_empty[1] ), + // Packet Filter + .rx_sample( ), + .ipv4_pkt_start( ipv4_pkt_start[1] ), + .trigger( ), + .rx_enet_bcast( rx_enet_bcast[1] ), + .rx_ipv4_arp( rx_ipv4_arp[1] ), + .rx_k_m1( rx1_k_m1 ), + .rx_k_m2( rx1_k_m2 ), + .rx_k_m3( rx1_k_m3), + .rx_k_m4( rx1_k_m4 ), + .rx_data_m1( rx1_data_m1 ), + .rx_data_m2( rx1_data_m2 ), + .rx_data_m3( rx1_data_m3), + .rx_data_m4( rx1_data_m4 ), + // Param RAM + .dpr_ad( param_phy1_addr ), + .dpr_we( param_phy1_we), + .dpr_ce(param_phy1_ce ), + .dpr_di(param_phy1_din), + .dpr_do(param_phy1_dout), + // Metrics and Interrupts + .mac_int( mac_int[1] ), + .rx_sop( rx_sop[1] ), + .rx_eop( rx_eop[1] ), + .tx_sop( tx_sop[1] ), + .tx_eop( tx_eop[1] ), + .metrics_start ( ), + .metrics_d ( 9'h0 ), + .rx_active( mac_rx_active[1] ), + .tx_active( mac_tx_active[1] ) +); + +ipv4_rx ipv4_rx_1( + .rstn( rstn ), + .clk( pcs_pclk ), + // control + .phy_resetn ( phy_resetn[1] ), + .phy_up( phy_up[1] ), + // packet data + .pkt_start( ipv4_pkt_start[1] ), + .rx_eop( rx_eop[1] ), + .rx_data_m1( rx1_data_m1 ), + .rx_data_m2( rx1_data_m2 ), + .rx_data_m3( rx1_data_m3), + .rx_data_m4( rx1_data_m4 ), + // flags + .pkt_complete(ipv4_pkt_complete[1]), + .trigger_src_addr( ), + .trigger_dst_addr( trigger[1] ), + .keep( ) + ); + +pkt_filter #(.DEPTH(8), .DEPTHW(3), .WIDTH(32)) pkt_filter_10( + .rstn( rstn ), + .clk( pcs_pclk ), + // input for programming + .sel( pkt_filter_sel_10 ), + .we( mem_we ), + .addr( mem_addr[4:0] ), + .d_in( mem_d_i[7:0] ), + // registered data + .rx_data_m1( rx1_data_m1 ), + .rx_data_m2( rx1_data_m2 ), + .rx_data_m3( rx1_data_m3), + .rx_data_m4( rx1_data_m4 ), + // filter + .new_frame ( rx_sop[1] ), + .block( 1'b0 ), + .invert( 1'b1 ), + .trigger( trigger[1] ), + .keep( rx_pf_keep_10 ) + ); + +drop_fifo drop_fifo_10( + .rstn( rstn ), + .clk ( pcs_pclk ), + .enable( 1'b1 ), + // control + .keep ( rx_pf_keep_10 | rx_mac_keep[1] ), + .passthrough( 1'b0 ), + // input + .we_in( rx_sc_fifo_we[1] ), + .wr_done( rx_sc_wr_done[1] ), + .d_in( rx_sc_fifo_d1 ), + // output + .we_out( rx_df_fifo_we_10 ), + .d_out( rx_df_fifo_d_10 ), + // debug + .active( drop_rx1_active[0] ) + ); + +sync_fifo sync_fifo_rx_10( + .rstn( rstn ), + .clk ( pcs_pclk ), + // input / RX + .we ( rx_df_fifo_we_10 & phy_up[0] ), + .d_in ( rx_df_fifo_d_10 ), + // output / TX + .re ( rx_sw_fifo_re_10 ), + .d_out( rx_sf_fifo_d_10 ), + .empty( rx_sf_fifo_empty_10 ), + .almost_full( ), + .reset_ptrs( 1'b0 ), + // debug + .active( sync_rx1_active[0] ) +); + +pkt_filter pkt_filter_12( + .rstn( rstn ), + .clk( pcs_pclk ), + // input for programming + .sel( pkt_filter_sel_12 ), + .we( mem_we ), + .addr( mem_addr[3:0] ), + .d_in( mem_d_i[7:0] ), + // registered data + .rx_data_m1( rx1_data_m1 ), + .rx_data_m2( rx1_data_m2 ), + .rx_data_m3( rx1_data_m3), + .rx_data_m4( rx1_data_m4 ), + // filter + .new_frame ( rx_sop[1] ), + .block( rx_sf_almost_full_12 ), + .invert( 1'b1 ), + .trigger( trigger[1] ), + .keep( rx_pf_keep_12 ) + ); + +drop_fifo drop_fifo_12( + .rstn( rstn ), + .clk ( pcs_pclk ), + .enable(1'b1), + // control + .keep ( rx_pf_keep_12 | rx_mac_keep[1] ), + .passthrough( 1'b0 ), + // input + .we_in( rx_sc_fifo_we[1] ), + .wr_done( rx_sc_wr_done[1] ), + .d_in( rx_sc_fifo_d1 ), + // output + .we_out( rx_df_fifo_we_12 ), + .d_out( rx_df_fifo_d_12 ), + // debug + .active( drop_rx1_active[2] ) + ); + +sync_fifo sync_fifo_rx_12( + .rstn( rstn ), + .clk ( pcs_pclk ), + // input / RX + .we ( rx_df_fifo_we_12 & phy_up[2] ), + .d_in ( rx_df_fifo_d_12 ), + // output / TX + .re ( rx_sw_fifo_re_12 ), + .d_out( rx_sf_fifo_d_12 ), + .empty( rx_sf_fifo_empty_12 ), + .almost_full( rx_sf_almost_full_12 ), + .reset_ptrs( 1'b0 ), + // debug + .active( sync_rx1_active[2] ) +); + +pkt_filter pkt_filter_13( + .rstn( rstn ), + .clk( pcs_pclk ), + // input for programming + .sel( pkt_filter_sel_13 ), + .we( mem_we ), + .addr( mem_addr[3:0] ), + .d_in( mem_d_i[7:0] ), + // registered data + .rx_data_m1( rx1_data_m1 ), + .rx_data_m2( rx1_data_m2 ), + .rx_data_m3( rx1_data_m3), + .rx_data_m4( rx1_data_m4 ), + // filter + .new_frame ( rx_sop[1] ), + .block( 1'b0 ), + .invert( 1'b0 ), + .trigger( trigger[1] ), + .keep( rx_pf_keep_13 ) + ); + +drop_fifo drop_fifo_13( + .rstn( rstn ), + .clk ( pcs_pclk ), + .enable( 1'b0 ), + // control + .keep ( rx_pf_keep_13 | rx_mac_keep[1] ), + .passthrough( 1'b0 ), + // input + .we_in( rx_sc_fifo_we[1] ), + .wr_done( rx_sc_wr_done[1] ), + .d_in( rx_sc_fifo_d1 ), + // output + .we_out( rx_df_fifo_we_13 ), + .d_out( rx_df_fifo_d_13 ), + // debug + .active( drop_rx1_active[3] ) + ); + +sync_fifo sync_fifo_rx_13( + .rstn( rstn ), + .clk ( pcs_pclk ), + // input / RX + .we ( rx_df_fifo_we_13 & phy_up[3] ), + .d_in ( rx_df_fifo_d_13 ), + // output / TX + .re ( rx_sw_fifo_re_13 ), + .d_out( rx_sf_fifo_d_13 ), + .empty( rx_sf_fifo_empty_13 ), + .almost_full( ), + .reset_ptrs( 1'b0 ), + // debug + .active( sync_rx1_active[3] ) + ); + +fcs fcs_1( + .rstn( rstn ), + .clk( pcs_pclk ), + .init( fcs_init[1] ), + .enable( fcs_enable[1] ), + .addr( fcs_addr1 ), + .din( fcs_din1 ), + .dout( fcs_dout1 ) +); + +/* + * Param RAM + */ +dpram param_ram_1( + .rstn(rstn), + .a_clk(clk_10), + .a_clk_e(param_sel[0]), + .a_we(mem_we), + .a_oe(mem_oe), + .a_addr(mem_addr), + .a_din(mem_d_i[8:0]), + .a_dout(param_ram_1_do), + // port B + .b_clk( pcs_pclk), + .b_clk_e(param_phy1_ce), + .b_we(param_phy1_we), + .b_oe( 1'b1 ), + .b_addr( param_phy1_addr ), + .b_din( param_phy1_dout ), + .b_dout( param_phy1_din ) + ); + + +metrics metrics_2( + .rstn( rstn ), + .clk( pcs_pclk ), + .mode_100Mbit( mode_100Mbit[2] ), + // input data for gathering metrics + .rx_mac_keep( rx_mac_keep ), + .rx_pf_keep_01( rx_pf_keep_01 ), + .rx_pf_keep_02( rx_pf_keep_02 ), + .rx_pf_keep_10( rx_pf_keep_10 ), + .rx_pf_keep_12( rx_pf_keep_12 ), + .rx_pf_keep_20( rx_pf_keep_20 ), + .rx_pf_keep_21( rx_pf_keep_21 ), + .rx_pf_keep_23( rx_pf_keep_23 ), + + .rx_sop( rx_sop ), + .rx_eop( rx_eop ), + .tx_sop( tx_sop ), + .tx_eop( tx_eop ), + // metric outputs + .metrics_start ( metrics_start ), + .metrics_d( metrics_d ) +); + + +// GEODSS MAC +mac mac_2( + .rstn(~mac_reset[2]), + .phy_resetn ( phy_resetn[2] ), + .clk( pcs_pclk ), + .tap_port ( 1'b0 ), + // SGMII AN + .phy_type(2'b01), // SX==1 + .an_disable( 1'b1 ), + .pulse_1_6ms(pulse_1_6ms), + .pulse_10ms(pulse_10ms), + .fixed_speed(SGMII_SPEED_1GBIT), + .an_duplex( ), + .mode_100Mbit( mode_100Mbit[2] ), + .phy_up( phy_up[2] ), + // Switch I/F + .tx_mode( tx_sw_mode2 ), + .tx_f( tx_sc_done[2] ), + // PCS / SERDES health + .rx_lsm( 1'b1 ), // TODO: Fix LSM for SFP + .rx_cv_err ( sgmii_rx_cv_err[2] ), + .rx_disp_err( sgmii_rx_disp_err[2] ), + .rx_cdr_lol( sgmii_rx_cdr_lol[2] ), + .rx_los ( sgmii_rx_los_low[2] ), + // PCS data I/F + .rx_k( sgmii_rx_k[2] ), + .rx_data( rx_data2 ), + .tx_k( sgmii_tx_k[2] ), + .tx_data( tx_data2 ), + .tx_disp_correct( sgmii_tx_disp_correct[2] ), + // Flags and Interrupts + .keep( rx_mac_keep[2] ), + // FCS + .fcs_init( fcs_init[2] ), + .fcs_enable( fcs_enable[2] ), + .fcs_addr( fcs_addr2 ), + .fcs_dout( fcs_din2 ), + .fcs_din( fcs_dout2 ), + // SGMII RX / FIFO Write + .rx_fifo_we( rx_sc_fifo_we[2] ), + .rx_fifo_d(rx_sc_fifo_d2), + .rx_error( rx_sc_error[2] ), + .rx_wr_done( rx_sc_wr_done[2] ), + .rx_byte_cnt(rx2_byte_cnt), + // SGMII TX / FIFO Read + .tx_byte_cnt_i(tx2_byte_cnt), + .tx_fifo_re( tx_sc_fifo_re[2] ), + .tx_fifo_d( tx_sw_fifo_d2 ), + .tx_fifo_empty( tx_sw_fifo_empty[2]), + // Packet Filter + .rx_sample( ), + .ipv4_pkt_start( ipv4_pkt_start[2] ), + .trigger( ), + .rx_enet_bcast( rx_enet_bcast[2] ), + .rx_ipv4_arp( rx_ipv4_arp[2] ), + .rx_k_m1( rx2_k_m1 ), + .rx_k_m2( rx2_k_m2 ), + .rx_k_m3( rx2_k_m3), + .rx_k_m4( rx2_k_m4 ), + .rx_data_m1( rx2_data_m1 ), + .rx_data_m2( rx2_data_m2 ), + .rx_data_m3( rx2_data_m3), + .rx_data_m4( rx2_data_m4 ), + // Param RAM + .dpr_ad( param_phy2_addr ), + .dpr_we( param_phy2_we ), + .dpr_ce( param_phy2_ce ), + .dpr_di( param_phy2_din ), + .dpr_do( param_phy2_dout ), + // Metrics and Interrupts + .mac_int( mac_int[2] ), + .rx_sop( rx_sop[2] ), + .rx_eop( rx_eop[2] ), + .tx_sop( tx_sop[2] ), + .tx_eop( tx_eop[2] ), + .metrics_start ( metrics_start ), + .metrics_d( metrics_d ), + // Debug + .rx_active( mac_rx_active[2] ), + .tx_active( mac_tx_active[2] ) +); + +ipv4_rx ipv4_rx_2( + .rstn( rstn ), + .clk( pcs_pclk ), + // control + .phy_resetn ( phy_resetn[2] ), + .phy_up( phy_up[2] ), + // packet data + .pkt_start( ipv4_pkt_start[2] ), + .rx_eop( rx_eop[2] ), + .rx_data_m1( rx2_data_m1 ), + .rx_data_m2( rx2_data_m2 ), + .rx_data_m3( rx2_data_m3), + .rx_data_m4( rx2_data_m4 ), + // flags + .pkt_complete(ipv4_pkt_complete[2]), + .trigger_src_addr( ), + .trigger_dst_addr( trigger[2] ), + .keep( ) + ); + + +pkt_filter pkt_filter_20( + .rstn( rstn ), + .clk( pcs_pclk ), + // input for programming + .sel( pkt_filter_sel_20 ), + .we( mem_we ), + .addr( mem_addr[3:0] ), + .d_in( mem_d_i[7:0] ), + // registered data + .rx_data_m1( rx2_data_m1 ), + .rx_data_m2( rx2_data_m2 ), + .rx_data_m3( rx2_data_m3), + .rx_data_m4( rx2_data_m4 ), + // filter + .new_frame ( rx_sop[2] ), + .block( rx_sf_almost_full_20 ), + .invert( 1'b0 ), + .trigger( trigger[2] ), + .keep( rx_pf_keep_20 ) +); + +drop_fifo drop_fifo_20( + .rstn( rstn ), + .clk ( pcs_pclk ), + .enable( 1'b0 ), + // control + .keep ( rx_pf_keep_20 | rx_mac_keep[2] ), + .passthrough( 1'b0 ), + // input + .we_in( rx_sc_fifo_we[2] ), + .wr_done( rx_sc_wr_done[2] ), + .d_in( rx_sc_fifo_d2 ), + // output + .we_out( rx_df_fifo_we_20 ), + .d_out( rx_df_fifo_d_20 ), + // debug + .active( drop_rx2_active[0] ) + ); + +sync_fifo sync_fifo_rx_20( + .rstn( rstn ), + .clk ( pcs_pclk ), + // input / RX + .we ( rx_df_fifo_we_20 & phy_up[0]), + .d_in ( rx_df_fifo_d_20 ), + // output / TX + .re ( rx_sw_fifo_re_20 ), + .d_out( rx_sf_fifo_d_20 ), + .empty( rx_sf_fifo_empty_20 ), + .almost_full( rx_sf_almost_full_20 ), + .reset_ptrs( 1'b0 ), + // debug + .active( sync_rx2_active[0] ) +); + +pkt_filter pkt_filter_21( + .rstn( rstn ), + .clk( pcs_pclk ), + // input for programming + .sel( pkt_filter_sel_21 ), + .we( mem_we ), + .addr( mem_addr[3:0] ), + .d_in( mem_d_i[7:0] ), + // registered data + .rx_data_m1( rx2_data_m1 ), + .rx_data_m2( rx2_data_m2 ), + .rx_data_m3( rx2_data_m3), + .rx_data_m4( rx2_data_m4 ), + // filter + .new_frame ( rx_sop[2] ), + .block( 1'b0 ), + .invert( 1'b0 ), + .trigger( trigger[2] ), + .keep( rx_pf_keep_21 ) +); + +drop_fifo drop_fifo_21( + .rstn( rstn ), + .clk ( pcs_pclk ), + .enable( 1'b0 ), + // control + .keep ( rx_pf_keep_21 | rx_mac_keep[2] ), + .passthrough( 1'b0 ), + // input + .we_in( rx_sc_fifo_we[2] ), + .wr_done( rx_sc_wr_done[2] ), + .d_in( rx_sc_fifo_d2 ), + // output + .we_out( rx_df_fifo_we_21 ), + .d_out( rx_df_fifo_d_21 ), + // debug + .active( drop_rx2_active[1] ) + ); + +sync_fifo sync_fifo_rx_21( + .rstn( rstn ), + .clk ( pcs_pclk ), + // input / RX + .we ( rx_df_fifo_we_21 & phy_up[1] ), + .d_in ( rx_df_fifo_d_21 ), + // output + .re ( rx_sw_fifo_re_21 ), + .d_out( rx_sf_fifo_d_21 ), + .empty( rx_sf_fifo_empty_21 ), + .almost_full( ), + .reset_ptrs( 1'b0 ), + // debug + .active( sync_rx2_active[1] ) +); + +pkt_filter pkt_filter_2u( + .rstn( rstn ), + .clk( pcs_pclk ), + // input for programming + .sel( pkt_filter_sel_2u ), + .we( mem_we ), + .addr( mem_addr[3:0] ), + .d_in( mem_d_i[7:0] ), + // registered data + .rx_data_m1( rx2_data_m1 ), + .rx_data_m2( rx2_data_m2 ), + .rx_data_m3( rx2_data_m3), + .rx_data_m4( rx2_data_m4 ), + // filter + .new_frame ( rx_sop[2] ), + .block( tx_uc_block ), + .invert( 1'b0 ), + .trigger( trigger[2] ), + .keep( rx_pf_keep_2u ) + ); + +drop_fifo drop_fifo_2u( + .rstn( rstn ), + .clk ( pcs_pclk ), + .enable( 1'b0 ), + // control + .passthrough( 1'b0 ), + .keep ( rx_pf_keep_2u | rx_mac_keep[2] ), + // input + .we_in( rx_sc_fifo_we[2] ), + .wr_done( rx_sc_wr_done[2] ), + .d_in( rx_sc_fifo_d2 ), + // output + .we_out( rx_df_fifo_we_2u ), + .d_out( rx_df_fifo_d_2u ), + // debug + .active( ) + ); + +// TODO: add a flag on we to keep UC from being overwritten +sync_fifo sync_fifo_rx_2u( + .rstn( rstn ), + .clk ( pcs_pclk ), + // input / RX + .we ( rx_df_fifo_we_2u ), + .d_in ( rx_df_fifo_d_2u ), + // output + .re ( rx_sw_fifo_re_2u ), + .d_out( rx_sf_fifo_d_2u ), + .empty( rx_sf_fifo_empty_2u ), + .almost_full( ), + .reset_ptrs( 1'b0 ), + // debug + .active( ) +); + +fcs fcs_2( + .rstn( rstn ), + .clk( pcs_pclk ), + .init( fcs_init[2] ), + .enable( fcs_enable[2] ), + .addr( fcs_addr2 ), + .din( fcs_din2 ), + .dout( fcs_dout2 ) +); + +// GEODSS SMA (MAC is bypassed) +mac mac_3( + .rstn( ~mac_reset[3] & ~sgmii_rx_los_low[3] ), + .phy_resetn ( phy_resetn[3] ), + .clk( pcs_pclk ), + .tap_port ( 1'b0 ), + // SGMII AN + .phy_type(2'b11), // SMA=3 + .an_disable(1'b1), + .pulse_1_6ms(pulse_1_6ms), + .pulse_10ms(pulse_10ms), + .fixed_speed(SGMII_SPEED_1GBIT), + .an_duplex( ), + .mode_100Mbit( mode_100Mbit[3] ), + .phy_up( phy_up[3] ), + // Switch I/F + .tx_mode( tx_sw_mode3 ), + .tx_f( tx_sc_done[3] ), + // PCS / SERDES health + .rx_lsm( sgmii_lsm_status[3] ), + .rx_cv_err ( sgmii_rx_cv_err[3] ), + .rx_disp_err( sgmii_rx_disp_err[3] ), + .rx_cdr_lol( sgmii_rx_cdr_lol[3] ), + .rx_los ( sgmii_rx_los_low[3] ), + // PCS data I/F + .rx_k( sgmii_rx_k[3] ), + .rx_data( rx_data3 ), + .tx_k( sgmii_tx_k[3] ), + .tx_data( tx_data3 ), + .tx_disp_correct( sgmii_tx_disp_correct[3] ), + // Flags and Interrupts + .keep( rx_mac_keep[3] ), + // TX FCS + .fcs_init( fcs_init[3] ), + .fcs_enable( fcs_enable[3] ), + .fcs_addr( fcs_addr3 ), + .fcs_dout( fcs_din3 ), + .fcs_din( fcs_dout3 ), + // SGMII RX / FIFO Write + .rx_fifo_we( rx_sc_fifo_we[3] ), + .rx_fifo_d( rx_sc_fifo_d3 ), + .rx_error( rx_sc_error[3] ), + .rx_wr_done( rx_sc_wr_done[3] ), + .rx_byte_cnt(rx3_byte_cnt), + // SGMII TX / FIFO Read + .tx_byte_cnt_i(tx3_byte_cnt), + .tx_fifo_re( tx_sc_fifo_re[3] ), + .tx_fifo_d( tx_sw_fifo_d3 ), + .tx_fifo_empty( tx_sw_fifo_empty[3] ), + // Packet Filter + .rx_sample( rx_sample[3] ), + .ipv4_pkt_start( ipv4_pkt_start[3] ), + .trigger( ), + .rx_enet_bcast( rx_enet_bcast[3] ), + .rx_ipv4_arp( rx_ipv4_arp[3] ), + .rx_k_m1( rx3_k_m1 ), + .rx_k_m2( rx3_k_m2 ), + .rx_k_m3( rx3_k_m3), + .rx_k_m4( rx3_k_m4 ), + .rx_data_m1( rx3_data_m1 ), + .rx_data_m2( rx3_data_m2 ), + .rx_data_m3( rx3_data_m3), + .rx_data_m4( rx3_data_m4 ), + // Param RAM + .dpr_ad( ), + .dpr_we( ), + .dpr_ce( ), + .dpr_di( 9'h0), + .dpr_do( ), + // Metrics and Interrupts + .mac_int( mac_int[3] ), + .rx_sop( rx_sop[3] ), + .rx_eop( rx_eop[3] ), + .tx_sop( tx_sop[3] ), + .tx_eop( tx_eop[3] ), + .metrics_start ( ), + .metrics_d ( 9'h0 ), + // Debug + .rx_active( mac_rx_active[3] ), + .tx_active( mac_tx_active[3] ) + + ); + + +ipv4_rx ipv4_rx_3( + .rstn( rstn ), + .clk( pcs_pclk ), + // control + .phy_resetn ( phy_resetn[3] ), + .phy_up( phy_up[3] ), + // packet data + .pkt_start( ipv4_pkt_start[3] ), + .rx_eop( rx_eop[3] ), + .rx_data_m1( rx3_data_m1 ), + .rx_data_m2( rx3_data_m2 ), + .rx_data_m3( rx3_data_m3), + .rx_data_m4( rx3_data_m4 ), + // flags + .pkt_complete(ipv4_pkt_complete[3]), + .trigger_src_addr( ), + .trigger_dst_addr( trigger[3] ), + .keep( ) + ); + + + +pkt_filter pkt_filter_30( + .rstn( rstn ), + .clk( pcs_pclk ), + // input for programming + .sel( pkt_filter_sel_30 ), + .we( mem_we ), + .addr( mem_addr[3:0] ), + .d_in( mem_d_i[7:0] ), + // registered data + .rx_data_m1( rx3_data_m1 ), + .rx_data_m2( rx3_data_m2 ), + .rx_data_m3( rx3_data_m3), + .rx_data_m4( rx3_data_m4 ), + // filter + .new_frame ( rx_sop[3] ), + .block( 1'b0 ), + .invert( 1'b0 ), + .trigger( trigger[3] ), + .keep( rx_pf_keep_30 ) + ); + +drop_fifo drop_fifo_30( + .rstn( rstn ), + .clk ( pcs_pclk ), + .enable( 1'b0 ), + // control + .keep ( rx_pf_keep_30 | rx_mac_keep[3] ), + .passthrough( 1'b0 ), + // input + .we_in( rx_sc_fifo_we[3] ), + .wr_done( rx_sc_wr_done[3] ), + .d_in( rx_sc_fifo_d3 ), + // output + .we_out( rx_df_fifo_we_30 ), + .d_out( rx_df_fifo_d_30 ), + // debug + .active( drop_rx3_active[0] ) + ); + +sync_fifo sync_fifo_rx_30( + .rstn( rstn ), + .clk ( pcs_pclk ), + // input + .we ( rx_df_fifo_we_30 & phy_up[0] ), + .d_in ( rx_df_fifo_d_30 ), + // output + .re ( rx_sw_fifo_re_30 ), + .d_out( rx_sf_fifo_d_30 ), + .empty( rx_sf_fifo_empty_30 ), + .almost_full( ), + .reset_ptrs( 1'b0 ), + // debug + .active( sync_rx3_active[0] ) + ); + +pkt_filter pkt_filter_31( + .rstn( rstn ), + .clk( pcs_pclk ), + // input for programming + .sel( pkt_filter_sel_31 ), + .we( mem_we ), + .addr( mem_addr[3:0] ), + .d_in( mem_d_i[7:0] ), + // registered data + .rx_data_m1( rx3_data_m1 ), + .rx_data_m2( rx3_data_m2 ), + .rx_data_m3( rx3_data_m3), + .rx_data_m4( rx3_data_m4 ), + // filter + .new_frame ( rx_sop[3] ), + .block( 1'b0 ), + .invert( 1'b0 ), + .trigger( trigger[3] ), + .keep( rx_pf_keep_31 ) + ); + +drop_fifo drop_fifo_31( + .rstn( rstn ), + .clk ( pcs_pclk ), + .enable( 1'b0 ), + // control + .keep ( rx_pf_keep_31 | rx_mac_keep[3] ), + .passthrough( 1'b0 ), + // input + .we_in( rx_sc_fifo_we[3] ), + .wr_done( rx_sc_wr_done[3] ), + .d_in( rx_sc_fifo_d3 ), + // output + .we_out( rx_df_fifo_we_31 ), + .d_out( rx_df_fifo_d_31 ), + // debug + .active( drop_rx3_active[1] ) + ); + +sync_fifo sync_fifo_rx_31( + .rstn( rstn ), + .clk ( pcs_pclk ), + // input + .we ( rx_df_fifo_we_31 & phy_up[1] ), + .d_in ( rx_df_fifo_d_31 ), + // output + .re ( rx_sw_fifo_re_31 ), + .d_out( rx_sf_fifo_d_31 ), + .empty( rx_sf_fifo_empty_31 ), + .almost_full( ), + .reset_ptrs( 1'b0 ), + // debug + .active( sync_rx3_active[1] ) + ); + +fcs fcs_3( + .rstn( rstn ), + .clk( pcs_pclk ), + .init( fcs_init[3] ), + .enable( fcs_enable[3] ), + .addr( fcs_addr3 ), + .din( fcs_din3 ), + .dout( fcs_dout3 ) +); + +/* + * uCont i/f FIFO + * FIFO side connects to network switch + * RX: processor writes (data into switch) + * TX: processor reads (data from switch) + */ +half_fifo #(.DPRAM_DEPTH(9)) micro_fifo_0 ( + .rstn( rstn ), + .uc_clk(clk_10), + .fifo_clk(pcs_pclk), + // UC interrupt support + .fifo_we_int ( micro_fifo_int ), + // TX mode + .tx_mode(tx_sw_modeu), + // DPRAM common + .dpram_addr( mem_addr[8:0] ), + .dpram_din( mem_d_i[8:0] ), + .dpram_dout( micro_fifo_do ), + .dpram_we( mem_we ), + .dpram_oe( mem_oe ), + // UC select signals + .dpram_ptrs_sel( dpram_ptrs_sel ), + .dpram_rx_sel( dpram_rx_sel ), + .dpram_tx_sel( dpram_tx_sel ), + // FIFO TX (input) + .fifo_we( tx_sw_fifo_we ), + .fifo_d_in( tx_sw_fifo_du ), + // FIFO RX (output) + .fifo_re( rx_sw_fifo_re_u2 ), + .fifo_d_out( rx_uc_fifo_d_u2 ), + // FIFO flags + .rx_empty( rx_uc_fifo_empty_u2 ), + .tx_full ( tx_uc_block ) + ); + +/* + * Param RAM + */ +dpram param_ram_2( + .rstn(rstn), + .a_clk(clk_10), + .a_clk_e(param_sel[2]), + .a_we(mem_we), + .a_oe(mem_oe), + .a_addr(mem_addr), + .a_din(mem_d_i[8:0]), + .a_dout(param_ram_2_do), + // port B + .b_clk( pcs_pclk), + .b_clk_e(param_phy2_ce), + .b_we(param_phy2_we), + .b_oe( 1'b1 ), + .b_addr( param_phy2_addr ), + .b_din( param_phy2_dout ), + .b_dout( param_phy2_din ) +); + +//defparam param_ram_2.dp16kd_inst.INITVAL_00 = "00000000000000000000000000000000000000000000000000000000000000000022E10069F00800"; + + + +/* +* PCS Notes: +* All _c control signals are asynch in the SERDES/PCS +* All _s control signals are asynch and should be clocked before being used +* TxPLL provides system clock for FPGA logic +* tx_full_clk uses wire name 'txclk' and feeds both txi_clk and rxi_clk, as shown in Figure 9-27 +* For SGMII, tx_pclk is fed back internally to rxi_clk and ebrd_clk +* ebrd_clk: CTC FIFO Read Clock per Channel +* +*/ + +assign ext_sci_int = sci_int[0]; + +/* +PCSCLKDIV pcsclkdiv0 ( + .RST( ~rstn ), + .CLKI( refclko ), + .SEL2( 1'b1 ), // 101 is div by 8 + .SEL1( 1'b0 ), + .SEL0( 1'b1 ), + .CDIV1( ), + .CDIVX( ) +); +*/ + +/* + * PCS block that encapsulates two DCUs and the SCI block + */ + assign pcs_error[0] = sgmii_rx_cv_err[0] | sgmii_rx_cdr_lol[0] | !sgmii_lsm_status[0] | sgmii_rx_los_low[0]; + assign pcs_error[1] = sgmii_rx_cv_err[1] | sgmii_rx_cdr_lol[1] | !sgmii_lsm_status[1] | sgmii_rx_los_low[1]; + assign pcs_error[2] = sgmii_rx_cv_err[2] | sgmii_rx_cdr_lol[2] | sgmii_rx_los_low[2]; + assign pcs_error[3] = sgmii_rx_cv_err[3] | sgmii_rx_cdr_lol[3] | sgmii_rx_los_low[3]; + +pcs pcs_0 ( + + .refclk0_refclkn(refclkp_d0), + .refclk0_refclkp(refclkn_d0), + .refclk0_refclko( refclko ), + + // cross DCU tie offs + .sgmii0_cyawstn( 1'b0 ), + + //DCU0 CH0 to PHY0 + .sgmii0_hdinn(sgmii0_hdinn), + .sgmii0_hdinp(sgmii0_hdinp), + .sgmii0_hdoutn(sgmii0_hdoutn), + .sgmii0_hdoutp(sgmii0_hdoutp), + + // DCU resets + .sgmii0_tx_serdes_rst_c( tx_serdes_rst[0] ), // rset LOL signal in PLL TODO: change this + .sgmii0_rst_dual_c( pcs_rst_dual[0] ), // resets all serdes channels including aux and PCS + .sgmii0_serdes_rst_dual_c( serdes_rst_dual[0] ), // resets serdes dual gated by fpga_reset_enable + + // channel resets + .sgmii0_rx_pcs_rst_c( rx_pcs_rst[0] ), // reset channel PCS logic + .sgmii0_rx_serdes_rst_c( rx_serdes_rst[0] ), // reset digital logic in serdes rx + .sgmii0_tx_pcs_rst_c( tx_pcs_rst[0] ), // reset channel PCS logic + + .sgmii0_rx_pwrup_c(1'b1), // channel power up + .sgmii0_tx_pwrup_c(1'b1), // channel power up + + /* tx_pclk: Transmit Primary Clock. Direct connection to Primary + * clock network. When gearing is not enabled, this output + * equals the transmit full rate clock. When 2:1 gearing + * is enabled, it is a divide-by-2 half-rate clock. + */ + .sgmii0_tx_pclk( pcs_pclk ), // direct connection from primary clock network + .sgmii0_txi_clk( pcs_pclk ), // clocks the TX UI FIFOS (see Figure 27) + + .sgmii0_tx_disp_correct(sgmii_tx_disp_correct[0]), + .sgmii0_tx_k(sgmii_tx_k[0]), + .sgmii0_txdata( tx_data0 ), + .sgmii0_xmit(1'b0), //TODO: Auto Neg state machine + .sgmii0_signal_detect_c(1'b1), + .sgmii0_rx_cv_err( sgmii_rx_cv_err[0] ), // code violation with associated data, PCS will drive 0xEE and K=1 (Table 9-4) + .sgmii0_rx_disp_err( sgmii_rx_disp_err[0] ), + .sgmii0_rx_k( sgmii_rx_k[0] ), + .sgmii0_rxdata( rx_data0 ), + .sgmii0_lsm_status_s( sgmii_lsm_status[0] ), // lane is synced with commas ( 0 means no commas detected ) + .sgmii0_rx_cdr_lol_s( sgmii_rx_cdr_lol[0] ), // CDR Loss of lock + .sgmii0_rx_los_low_s( sgmii_rx_los_low[0] ), // Loss of signal (LO THRESHOLD RANGE) detection + + .sgmii0_ctc_ins_s(), // skip char added by CTC + .sgmii0_ctc_orun_s(), // CTC FIFO over run error + .sgmii0_ctc_urun_s(), // CTC FIFO under run error + .sgmii0_ctc_del_s(), // skip char deleted by CTC + .sgmii0_pll_lol( pll_lol[0] ), + + //DCU0 CH1 to PHY1 + .sgmii1_hdinn( sgmii1_hdinn ), + .sgmii1_hdinp( sgmii1_hdinp ), + .sgmii1_hdoutn( sgmii1_hdoutn ), + .sgmii1_hdoutp( sgmii1_hdoutp ), + + // DCU resets + .sgmii1_rst_dual_c( pcs_rst_dual[0] ), + .sgmii1_serdes_rst_dual_c( serdes_rst_dual[0] ), + .sgmii1_tx_serdes_rst_c( tx_serdes_rst[0] ), + + // Channel resets + .sgmii1_rx_pcs_rst_c( rx_pcs_rst[1] ), + .sgmii1_rx_serdes_rst_c( rx_serdes_rst[1] ), + .sgmii1_tx_pcs_rst_c( tx_pcs_rst[1] ), + + .sgmii1_rx_pwrup_c( 1'b1 ), + .sgmii1_tx_pwrup_c( 1'b1 ), + .sgmii1_serdes_pdb( 1'b1 ), + + .sgmii1_tx_pclk( ), + .sgmii1_txi_clk( pcs_pclk ), + + .sgmii1_rx_cv_err( sgmii_rx_cv_err[1] ), + .sgmii1_rx_disp_err( sgmii_rx_disp_err[1] ), + .sgmii1_rx_k( sgmii_rx_k[1] ), + .sgmii1_rxdata( rx_data1 ), + .sgmii1_tx_disp_correct( sgmii_tx_disp_correct[1] ), + .sgmii1_tx_k( sgmii_tx_k[1] ), + .sgmii1_txdata( tx_data1 ), + .sgmii1_xmit( 1'b0 ), // TODO: Auto Negotiation Bit + + .sgmii1_signal_detect_c( 1'b1 ), + + .sgmii1_ctc_del_s(), + .sgmii1_ctc_ins_s(), + .sgmii1_ctc_orun_s(), + .sgmii1_ctc_urun_s(), + + .sgmii1_lsm_status_s( sgmii_lsm_status[1] ), + .sgmii1_rx_cdr_lol_s( sgmii_rx_cdr_lol[1] ), + .sgmii1_rx_los_low_s( sgmii_rx_los_low[1] ), + + // DCU1 CH0 to Expansion + .sgmii2_hdinn( sgmii2_hdinn ), + .sgmii2_hdinp( sgmii2_hdinp ), + .sgmii2_hdoutn( sgmii2_hdoutn ), + .sgmii2_hdoutp( sgmii2_hdoutp ), + + // DCU Tie Offs + .sgmii2_cyawstn( 1'b0 ), + + // DCU resets + .sgmii2_rst_dual_c( pcs_rst_dual[1] ), + .sgmii2_serdes_rst_dual_c( serdes_rst_dual[1] ), + .sgmii2_tx_serdes_rst_c( tx_serdes_rst[1] ), + + // Channel resets + .sgmii2_rx_pcs_rst_c( rx_pcs_rst[2] ), + .sgmii2_rx_serdes_rst_c( rx_serdes_rst[2] ), + .sgmii2_tx_pcs_rst_c( tx_pcs_rst[2] ), + + .sgmii2_rx_pwrup_c( 1'b1 ), + .sgmii2_tx_pwrup_c( 1'b1 ), + .sgmii2_serdes_pdb( 1'b1 ), + + .sgmii2_tx_pclk( ), + .sgmii2_txi_clk( pcs_pclk ), + + .sgmii2_rx_cv_err( sgmii_rx_cv_err[2] ), + .sgmii2_rx_disp_err( sgmii_rx_disp_err[2] ), + .sgmii2_rx_k( sgmii_rx_k[2] ), + .sgmii2_rxdata( rx_data2 ), + .sgmii2_tx_disp_correct( sgmii_tx_disp_correct[2] ), + .sgmii2_tx_k( sgmii_tx_k[2] ), + .sgmii2_txdata( tx_data2 ), + .sgmii2_xmit( 1'b0 ), + + .sgmii2_signal_detect_c( 1'b1 ), + + .sgmii2_ctc_del_s(), + .sgmii2_ctc_ins_s(), + .sgmii2_ctc_orun_s(), + .sgmii2_ctc_urun_s(), + + .sgmii2_lsm_status_s( sgmii_lsm_status[2] ), + .sgmii2_rx_cdr_lol_s( sgmii_rx_cdr_lol[2] ), + .sgmii2_rx_los_low_s( sgmii_rx_los_low[2] ), + + .sgmii2_pll_lol( pll_lol[1] ), + + // DCU1 CH1 to Expansion + .sgmii3_hdinn( sgmii3_hdinn ), + .sgmii3_hdinp( sgmii3_hdinp ), + .sgmii3_hdoutn( sgmii3_hdoutn ), + .sgmii3_hdoutp( sgmii3_hdoutp ), + + // DCU resets + .sgmii3_rst_dual_c( pcs_rst_dual[1] ), + .sgmii3_serdes_rst_dual_c( serdes_rst_dual[1] ), + .sgmii3_tx_serdes_rst_c( tx_serdes_rst[1] ), + + // Channel resets + .sgmii3_rx_pcs_rst_c( rx_pcs_rst[3] ), + .sgmii3_rx_serdes_rst_c( rx_serdes_rst[3] ), + .sgmii3_tx_pcs_rst_c( tx_pcs_rst[3] ), + + .sgmii3_rx_pwrup_c( 1'b1 ), + .sgmii3_tx_pwrup_c( 1'b1 ), + + .sgmii3_tx_pclk( ), + .sgmii3_txi_clk( pcs_pclk ), + + .sgmii3_rx_cv_err( sgmii_rx_cv_err[3] ), + .sgmii3_rx_disp_err( sgmii_rx_disp_err[3] ), + .sgmii3_rx_k( sgmii_rx_k[3] ), + .sgmii3_rxdata( rx_data3 ), + .sgmii3_tx_disp_correct( sgmii_tx_disp_correct[3] ), +`ifdef SHIELD_SFP_SMA + .sgmii3_tx_k(rx2_k_m1), // MAC 2 RX k + .sgmii3_txdata(rx2_data_m1), // MAC 2 RX data +`else + .sgmii3_tx_k( sgmii_tx_k[3] ), + .sgmii3_txdata( tx_data3 ), +`endif + .sgmii3_xmit( 1'b0 ), // TODO: Auto Negotiation Bit + .sgmii3_signal_detect_c( 1'b1 ), + + .sgmii3_ctc_del_s(), + .sgmii3_ctc_ins_s(), + .sgmii3_ctc_orun_s(), + .sgmii3_ctc_urun_s(), + + .sgmii3_lsm_status_s( sgmii_lsm_status[3] ), + .sgmii3_rx_cdr_lol_s( sgmii_rx_cdr_lol[3] ), + .sgmii3_rx_los_low_s( sgmii_rx_los_low[3] ), + + + // DCU0 SCI + .sgmii0_sci_sel_dual( sci_sel_dual[0] ), + .sgmii0_sci_en_dual( 1'b1 ), + .sgmii0_sci_addr( mem_addr[5:0] ), // SCI Register Address Bits + .sgmii0_sci_rddata( sci_rddata0 ), + .sgmii0_sci_wrdata( mem_d_i[7:0] ), + .sgmii0_sci_rd( ~fb_oen ), + .sgmii0_sci_wrn( fb_rwn ), + + + .sgmii0_sci_sel( sci_sel_ch[0] ), + .sgmii0_sci_en( 1'b1 ), + + .sgmii1_sci_sel( sci_sel_ch[1] ), + .sgmii1_sci_en( 1'b1 ), + + .sgmii0_sci_int( sci_int[1] ), + + // DCU1 SCI + .sgmii2_sci_sel_dual( sci_sel_dual[1] ), + .sgmii2_sci_en_dual( 1'b1 ), + .sgmii2_sci_addr( mem_addr[5:0] ), // SCI Register Address Bits + .sgmii2_sci_rddata( sci_rddata1 ), + .sgmii2_sci_wrdata( mem_d_i[7:0] ), + .sgmii2_sci_rd( ~fb_oen ), + .sgmii2_sci_wrn( fb_rwn ), + + .sgmii2_sci_sel( sci_sel_ch[2] ), + .sgmii2_sci_en( 1'b1 ), + + .sgmii2_sci_int( sci_int[0] ), + + .sgmii3_sci_sel( sci_sel_ch[3] ) + +); + +// Link Timer for AN +link_timer link_timer_0( + .rstn(rstn), + .clk(pcs_pclk), + .pulse_1_6ms(pulse_1_6ms), + .pulse_10ms(pulse_10ms) +); + +mdio_controller #(.ADDR_SZ( MDIO_ROM_ADDR_SZ )) mdio_controller_0 +( + .rstn(rstn), + .clk(clk_10), + .work_start(mdio_cont_work_start), + .work_run(mdio_cont_work_run), + .work_done(mdio_cont_work_done), + .routine_addr( mdio_routine_addr ), + .buffer_full(1'b0), + .addr(rom_a), + .di(rom_d), + .reg_addr(mdio_reg_addr), + .dout(mdio_wd), + .ld(mdio_ld), + .rwn(mdio_rwn), + .done(mdio_done) +); + +`ifdef PHY_MARVELL +mdio_data_mvl #(.ADDR_SZ( MDIO_ROM_ADDR_SZ )) mdio_data_mvl_0( + .ad( rom_a ), + .page( mdio_page_set ), + .reg_addr( mdio_reg_addr_set ), + .data_in_h( mdio_w_data_h_set ), + .data_in_l( mdio_w_data_l_set ), + .d( rom_d ), + .oe( ~mdio_mux_sel[1] ) +); +`endif + +mdio_data_ti #(.ADDR_SZ( MDIO_ROM_ADDR_SZ )) mdio_data_ti_0( + .ad( rom_a ), + .page( mdio_page_set ), + .reg_addr( mdio_reg_addr_set ), + .data_in_h( mdio_w_data_h_set ), + .data_in_l( mdio_w_data_l_set ), + .d( rom_d ), + .oe( 1'b1 ) +); + + +/* MDIO mux and output enables */ +always @(*) begin + case (mdio_mux_sel) + 2'b00: mdi = phy0_mdio; + 2'b01: mdi = phy1_mdio; + 2'b10: mdi = phy2_mdio; // compile as 0 if GIGE_SHIELD isn't defined + 2'b11: mdi = 1'b1; + endcase +end + +assign phy0_mdio = (mdo_oe & ~mdio_mux_sel[1] & ~mdio_mux_sel[0]) ? mdo : 1'bz; +assign phy1_mdio = (mdo_oe & ~mdio_mux_sel[1] & mdio_mux_sel[0]) ? mdo : 1'bz; +assign phy2_mdio = (mdo_oe & mdio_mux_sel[1] & ~mdio_mux_sel[0]) ? mdo : 1'bz; + +mdio mdio_0( + .rstn(rstn), + .mdc(clk_10), + // MDIO + .mdi(mdi), + .mdo(mdo), + .mdo_oe(mdo_oe), + // mdio controller interface + .rwn(mdio_rwn), + .phy_addr(5'h00), + .reg_addr(mdio_reg_addr), + .di(mdio_wd), + .ld(mdio_ld), + .run( mdio_run ), + .done(mdio_done), // signal controller that mdio xfer is done + // output port to converter + .dout(mdio_rd), + .we( mdio_rd_we ) +); + + +spi spi_0 ( + .rstn(rstn), + .clk(clk_10), + // spi signals + .spi_cs( spi_cs ), + .spi_clk( spi_clk ), + .spi_d_in( spi_mosi), + .spi_d_o( spi_do ), + .spi_d_oe(spi_do_e ), + // internal FPGA memory + .mem_addr( mem_addr ), + .mux_sel ( mem_do_mux_sel ), + .d_i( mem_d_o ), + .d_o( mem_d_i ), + // individual memory selects + .we( mem_we ), + .oe( mem_oe ), + .dpram_tx_sel( dpram_tx_sel ), + .dpram_rx_sel( dpram_rx_sel ), + .dpram_ptrs_sel( dpram_ptrs_sel ), + .param_sel( param_sel ), + .pkt_filter_sel_01( pkt_filter_sel_01 ), + .pkt_filter_sel_02( pkt_filter_sel_02 ), + .pkt_filter_sel_03( pkt_filter_sel_03 ), + .pkt_filter_sel_10( pkt_filter_sel_10 ), + .pkt_filter_sel_12( pkt_filter_sel_12 ), + .pkt_filter_sel_13( pkt_filter_sel_13 ), + .pkt_filter_sel_20( pkt_filter_sel_20 ), + .pkt_filter_sel_21( pkt_filter_sel_21 ), + .pkt_filter_sel_23( pkt_filter_sel_23 ), + .pkt_filter_sel_2u( pkt_filter_sel_2u ), + .pkt_filter_sel_30( pkt_filter_sel_30 ), + .pkt_filter_sel_31( pkt_filter_sel_31 ), + .pkt_filter_sel_32( pkt_filter_sel_32 ), + .pkt_filter_sel_u2( pkt_filter_sel_u2 ), + .interrupts_sel( int_sel ), + .sci_sel_dual( sci_sel_dual ), + .sci_sel_ch( sci_sel_ch ) +); + +assign spi_miso = spi_do_e ? spi_do : 1'bz; + +/* data mux out of internal memories */ +always@(*) +begin + case(mem_do_mux_sel) + 5'b00000: mem_d_o = { 2'b0, sci_rddata1 }; + 5'b00001: mem_d_o = { 2'b0, sci_rddata0 }; + 5'b00010: mem_d_o = { 1'b0, micro_fifo_do }; + 5'b00011: mem_d_o = { 1'b0, micro_fifo_do }; + 5'b00100: mem_d_o = { 1'b0, micro_fifo_do }; + 5'b01000: mem_d_o = param_ram_0_do; + 5'b01001: mem_d_o = param_ram_1_do; + 5'b01010: mem_d_o = param_ram_2_do; + 5'b01011: mem_d_o = param_ram_3_do; + 5'b10000: mem_d_o = { 2'b0, int_do }; + default: mem_d_o = 9'h0; + endcase +end + +`ifdef DARSENA_V01 + +// only drive the FB AD bus when OE is asserted +assign fb_ad = fb_ad_oe ? fb_d : 10'bz; + + +always@(*) + begin + case({fb_cregs_sel,mem_do_mux_sel}) + 6'b000000: fb_d = { 2'b0, sci_rddata1 }; + 6'b000001: fb_d = { 2'b0, sci_rddata0 }; + 6'b000010: fb_d = { 1'b0, micro_fifo_do }; + 6'b000011: fb_d = { 1'b0, micro_fifo_do }; + 6'b000100: fb_d = { 1'b0, micro_fifo_do }; + 6'b010000: fb_d = { 2'b0, int_do }; + default: fb_d = fb_ad_o; + endcase + end + + +flexbus flexbus_0( + .clk( fb_clk ), + .rstn( rstn ), + // strobes + .fb_ale( fb_ale ), + .fb_oen( fb_oen ), + .fb_rwn( fb_rwn ), + .fb_csn( fb_csn ), + // control + .cregs_sel( fb_cregs_sel ), + // muxed addr and data + .fb_ad_i( fb_ad ), + .fb_ad_o( fb_ad_o ), + .fb_ad_oe( fb_ad_oe ), + // sys mem + .mem_addr( mem_addr ), + .mux_sel ( mem_do_mux_sel ), + // dpram controls + .dpram_we( mem_we ), + .dpram_oe( mem_oe ), + .dpram_tx_sel( dpram_tx_sel ), + .dpram_rx_sel( dpram_rx_sel ), + .dpram_ptrs_sel( dpram_ptrs_sel ), + .param_sel( param_sel ), + .pkt_filter_sel_01( pkt_filter_sel_01 ), + .pkt_filter_sel_02( pkt_filter_sel_02 ), + .pkt_filter_sel_10( pkt_filter_sel_10 ), + .pkt_filter_sel_12( pkt_filter_sel_12 ), + .pkt_filter_sel_20( pkt_filter_sel_20 ), + .pkt_filter_sel_21( pkt_filter_sel_21 ), + .pkt_filter_sel_23( pkt_filter_sel_23 ), + .interrupts_sel( int_sel ), + // SCI I/F + .sci_sel_dual( sci_sel_dual ), + .sci_sel_ch( sci_sel_ch ) +); + +`endif + +interrupts interrupts_0( + .rstn( rstn ), + .clk( pcs_pclk ), + .uc_clk( clk_10 ), + // uC interface + .sel( int_sel ), + .we( mem_we ), + .addr( mem_addr[0] ), + .d_in( mem_d_i[6:0] ), + .d_out( int_do ), + // interrupt sources + .cont_int( micro_fifo_int ), + .phy_int ( { 2'b0, phy1_intn, phy0_intn }), + .mac_int ( { mac_int[3], mac_int[2], mac_int[1], mac_int[0] } ), + .int_o( ) +); + + +assign i2c_sda = sda_oe ? sda_o : 1'bz; +assign i2c_scl = scl_oe ? scl_o : 1'bz; + +i2c i2c_0( + .rstn( rstn ), + .clk( clk_10 ), + // external I2C I/O + .scl_i( i2c_scl ), + .scl_o( scl_o ), + .scl_oe( scl_oe ), + .sda_i( i2c_sda ), + .sda_o( sda_o ), + .sda_oe( sda_oe ), + // shared memory and controller data output + .mem_do( i2c_d_o ), + // dedicated memory interface + .mem_ad( ), + .mem_we( ), + .mem_ce( ), + .mem_di( 8'haa ), + // dedicated controller write interface + .cont_we( i2c_cont_we ), + .cont_done( i2c_cont_done ), + // Controller->FIFO input interface + .fifo_re( i2c_fifo_re ), + .tx_fifo_empty( cont_fifo_empty ), + .fifo_di( fifo_r_d[6:0] ) +); + + +/* +* ext_sys_fifo delays and enables: +* we need the re delay since we need to generate a re pulse from the +* uart block, which is clocked at a slower rate. +* we need the mdio_we delay since the fifo is clocked twice: high and low data +* +*/ +always@ ( posedge clk_10 or negedge rstn ) + begin + if ( !rstn ) + begin + cont_fifo_re_m1 <= 1'b0; + cont_fifo_re_m2 <= 1'b0; + end + else + begin + cont_fifo_re_m1 <= uart_fifo_re | i2c_fifo_re; + cont_fifo_re_m2 <= cont_fifo_re_m1; + end + end + +// create a single re pulse since uart runs slow. +assign i_cont_fifo_re = cont_fifo_re_m1 & ~cont_fifo_re_m2; + +assign bin_to_ascii_we = mdio_rd_we | cont_rd_we; +assign bin_to_ascii_d_in = read_fifo_mux_sel ? mdio_rd : cont_rd; + +/* + * Input: MDIO writes + * Output: UART/I2C read FIFO + */ +bin_to_ascii bin_to_ascii_0( + .rstn( rstn ), + .clk( clk_10 ), + .width ( 1'b1 ), + // mdio interface + .we_i ( bin_to_ascii_we ), + .d_in( bin_to_ascii_d_in ), + // mdio controller interface + .run ( bin_to_ascii_run ), + .done (), + .busy( 1'b0 ), + // fifo port + .we_o ( read_fifo_we ), + .d_out( read_fifo_d_i ) +); + +/* + * Input: bin_to_ascii + * Output: I2C or UART read + */ +sync_fifo ext_sys_fifo_0( + .rstn( rstn ), + .clk ( clk_10 ), + // input + .we ( read_fifo_we ), + .d_in ( { 2'b0, read_fifo_d_i } ), + // output + .re ( i_cont_fifo_re ), + .d_out( fifo_r_d ), + .empty( cont_fifo_empty ), + .almost_full( ), + .reset_ptrs( 1'b0 ), + // debug + .active( ) +); + +always @(*) begin + case (mdio_mux_sel) + 2'b00: rx_cdr_lol = sgmii_rx_cdr_lol[0]; + 2'b01: rx_cdr_lol = sgmii_rx_cdr_lol[1]; + 2'b10: rx_cdr_lol = sgmii_rx_cdr_lol[2]; + 2'b11: rx_cdr_lol = 1'b1; + endcase +end + +always @(*) begin + case (mdio_mux_sel) + 2'b00: lsm_status = sgmii_lsm_status[0]; + 2'b01: lsm_status = sgmii_lsm_status[1]; + 2'b10: lsm_status = sgmii_lsm_status[2]; + 2'b11: lsm_status = 1'b1; + endcase +end + +always @(*) begin + case (mdio_mux_sel) + 2'b00: rx_los_low = sgmii_rx_los_low[0]; + 2'b01: rx_los_low = sgmii_rx_los_low[1]; + 2'b10: rx_los_low = sgmii_rx_los_low[2]; + 2'b11: rx_los_low = 1'b1; + endcase +end + +/* Debug and Arduino Expansion */ + +assign led[0] = 1'b1; +assign led[1] = phy_up[0]; +assign led[2] = phy_up[1]; + +`ifdef DEBUG_SPI + assign ard_scl = spi_clk; + assign ard_sda = spi_cs; + assign ard_rxd1 = spi_do_e ? spi_do : 1'bz; + assign ard_txd1 = spi_mosi; +`elsif DEBUG_MDIO + assign ard_scl = phy_mdc; + assign ard_sda = phy0_mdio; + assign ard_rxd1 = 1'bz; + assign ard_txd1 = refclko; +`elsif DEBUG_IC2 + assign ard_scl = i2c_scl; + assign ard_sda = sda_oe ? sda_o : i2c_sda; + assign ard_rxd1 = 1'bz; + assign ard_txd1 = sda_oe; +`else + assign ard_scl = rx_sop[0]; + assign ard_sda = 1'bz; +`endif + +`ifdef ARD_EXP_UART + assign ard_txd2 = uart_txd; + assign uart_rxd = ard_rxd2; + assign ftdi_tdi_rxd = 1'bz; +`else + + // assign uart_rxd = ftdi_tck_txd; +`endif + + assign ftdi_tdi_rxd = 1'bz; + + assign pe1 = pcs_error[2]; // RX data on SFP good + assign pe4 = ~sgmii_tx_k[2]; + assign pe5 = phy1_gpio[1]; + assign pg5 = 1'bz; + assign pe3 = fpga_gpio; + +`ifdef SHIELD_SFP_SMA + + // SFP UART testing + assign uart_rxd = ph3; + assign ph4 = uart_txd; + + // SFP LEDS + assign sfp_led1 = !sfp_pres_n; + assign sfp_led2 = !sfp_tx_fault; + assign sfp_led3 = !sfp_los; + assign sfp_led4 = !pcs_error[2]; + assign sfp_led5 = phy_up[0]; + assign sfp_led6 = !mac_tx_active[0]; +`endif + + assign fpga_int = pcs_error[2] | pcs_error[3]; + +`ifdef DARSENA_V02 + assign fpga_jtag_e =1'b1; +`endif + +endmodule |