summaryrefslogtreecommitdiffhomepage
diff options
context:
space:
mode:
authormindchasers <privateisland@mindchasers.com>2020-11-19 22:24:05 -0500
committermindchasers <privateisland@mindchasers.com>2020-11-19 22:24:05 -0500
commit9c58cebcab713f6fd959163d6bbf0e2b9b412b19 (patch)
tree770f3a29cea8480eac5a8f37b4b83af271ca18bd
parent39306b14e1a9b983ec0b566a209bebe7f5efcc14 (diff)
top: add support for custom packet and misc. cleanups
-rw-r--r--source/directives.v6
-rw-r--r--source/ethernet_params.v2
-rw-r--r--source/link_timer.v1
-rw-r--r--source/top.v585
4 files changed, 424 insertions, 170 deletions
diff --git a/source/directives.v b/source/directives.v
index da2f420..f34c3f0 100644
--- a/source/directives.v
+++ b/source/directives.v
@@ -30,6 +30,6 @@
//`define DARSENA_V03
// Shield Definition (PORTS 3 & 4)
-// `define SHIELD_SMA_SMA
-`define SHIELD_GIGE_SMA
-// `define SHIELD_SFP_SMA \ No newline at end of file
+`define SHIELD_SMA_SMA
+//`define SHIELD_GIGE_SMA
+//`define SHIELD_SFP_SMA \ No newline at end of file
diff --git a/source/ethernet_params.v b/source/ethernet_params.v
index 3238592..dcb7dba 100644
--- a/source/ethernet_params.v
+++ b/source/ethernet_params.v
@@ -30,7 +30,7 @@ localparam SZ_UDP_HEADER = 8;
localparam TX_MODE_AN = 3'b000,
TX_MODE_IDLE = 3'b001,
TX_MODE_XMT_PKT = 3'b010, // anything >= to this is a mode where a packet is transmitted
-TX_MODE_XMT_METRICS = 3'b011;
+TX_MODE_XMT_METRICS = 3'b011,
TX_MODE_XMT_CUSTOM = 3'b100;
// Note: The Length/Type field is transmitted and received with the high order octet first.
diff --git a/source/link_timer.v b/source/link_timer.v
index e467f25..7b501ff 100644
--- a/source/link_timer.v
+++ b/source/link_timer.v
@@ -26,7 +26,6 @@ module link_timer(
output pulse_10ms
);
- wire clk;
reg [13:0] cnt; // 0.1 ms counter
reg [3:0] cnt_1_6ms;
reg [6:0] cnt_10ms;
diff --git a/source/top.v b/source/top.v
index 23f667f..4944bae 100644
--- a/source/top.v
+++ b/source/top.v
@@ -1,7 +1,7 @@
/*
* top.v
*
- * Copyright (C) 2018, 2019 Mind Chasers Inc.
+ * Copyright (C) 2018, 2019, 2020 Mind Chasers Inc.
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
@@ -14,25 +14,18 @@
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
- *
+ *
+ * Private Island Top for Darsena / ECP5UM
+ *
*/
-`timescale 1ns /10ps
-
module top(
input rstn,
// REFCLK
input refclkp_d0, refclkn_d0,
input refclkp_d1, refclkn_d1,
-
- // PHY Control
- output phy0_resetn,
-
- output phy1_resetn,
-
- output phy2_resetn,
-
+
// SGMII0
input sgmii0_hdinp,
input sgmii0_hdinn,
@@ -57,26 +50,40 @@ module top(
output sgmii3_hdoutp,
output sgmii3_hdoutn,
- // MDIO ( management )
+ // PHYs
output phy_mdc,
+
+ output phy0_resetn,
inout phy0_mdio,
input [1:0] phy0_gpio,
+ input phy0_intn,
+ output phy1_resetn,
inout phy1_mdio,
input [1:0] phy1_gpio,
+ input phy1_intn,
+`ifdef SHIELD_GIGE_SMA
+ output phy2_resetn,
output phy2_mdc,
inout phy2_mdio,
-
- input phy0_intn,
- input phy1_intn,
+`elsif SHIELD_SFP_SMA
+ input sfp_tx_fault, // high indicates a laser fault of some kind.
+ output sfp_tx_disable, // high disables the transmitter
+ input sfp_pres_n, // (mod-def 0): grounded by the module to indicate that the module is present)
+ inout sfp_i2c_sda, // (mod-def 2)
+ output sfp_i2c_scl, // (mod-def 1)
+ input sfp_los, // Low indicates normal operation
+ output sfp_rate_select, // high for full bandwidth
+`endif
// Microcontroller SPI and bit banging
- input fpga_spics,
- input fpga_mclk,
- output fpga_miso,
- input fpga_mosi,
+ input spi_cs,
+ input spi_clk,
+ output spi_miso,
+ input spi_mosi,
output fpga_int,
+ input fpga_gpio,
// I2C
inout i2c_scl,
@@ -86,38 +93,51 @@ module top(
input uart_txd,
output uart_rxd,
+`ifdef DARSENA_V02
output fpga_jtag_e,
-
// FTDI UART signals muxed with JTAG
input ftdi_tck_txd,
output ftdi_tdi_rxd,
+`endif
output [2:0] led,
output ard_sda,
output ard_scl,
- output ard_txd1,
- output ard_rxd1,
- output ard_txd2,
- input ard_rxd2,
- output ard_txd3,
- input ard_rxd3,
-
- output pe0,
- output pe1,
+
+`ifdef SHIELD_SFP_SMA
+ output sfp_led1, // TXD3
+ output sfp_led2, // RXD3
+ output sfp_led3, // TXD2
+ output sfp_led4, // RXD2
+ output sfp_led5, // TXD1
+ output sfp_led6, // RXD1
+`endif
+
+ input pe0, //
+ output pe1, //
output pe3,
output pe4,
output pe5,
output pg5,
- output ph3,
- output ph4,
- inout [9:0] pa
-
+ input ph3, // UART RX for SFP Testing
+ output ph4, // UART TX for SFP Testing
+ inout [9:0] pa
);
-`include "sgmii_params.v"
`include "directives.v"
-
+`include "sgmii_params.v"
+`include "ethernet_params.v"
+
+`ifdef DARSENA_V01
+ wire fb_clk;
+ wire fb_ale;
+ wire fb_oen;
+ wire fb_rwn;
+ wire fb_csn;
+ wire fb_cregs_sel;
+ wire [9:0] fb_ad;
+`endif
/* PARAMS */
localparam MDIO_ROM_ADDR_SZ = 7;
@@ -129,6 +149,9 @@ wire clk_slow, clk_1_25, clk_10, clk_20;
wire clk_100;
wire refclko;
+// pulses
+wire pulse_10ms, pulse_1_6ms;
+
// misc resets
wire [3:0] phy_resetn; // bit[0] will get pruned out for now
wire [3:0] mac_reset;
@@ -169,8 +192,11 @@ wire [4:0] mdio_page_set;
wire sda_oe, scl_oe, sda_o, scl_o;
wire i2c_fifo_priority;
+// UART
+wire uart_rx_done;
wire read_fifo_we;
wire [8:0] fifo_r_d;
+wire [6:0] d_uart_rx;
// bin to ASCII
wire [15:0] bin_to_ascii_d_in;
@@ -187,6 +213,7 @@ wire [7:0] rx_data0, rx_data1, rx_data2, rx_data3;
wire [7:0] tx_data0, tx_data1, tx_data2, tx_data3;
wire [6:0] read_fifo_d_i;
wire [3:0] rx_sample;
+wire [3:0] pcs_error;
// ipv4
wire [3:0] ipv4_pkt_start;
@@ -194,7 +221,7 @@ wire [3:0] ipv4_pkt_complete;
reg cont_fifo_re_m1, cont_fifo_re_m2;
wire cont_fifo_empty;
-wire i2c_fifo_re;
+wire i2c_fifo_re, uart_fifo_re;
wire i2c_cont_we, i2c_cont_done;
wire i_cont_fifo_re;
wire bin_to_ascii_we, mdio_rd_we, cont_rd_we;
@@ -213,9 +240,12 @@ wire mem_we, mem_oe;
wire [4:0] mem_do_mux_sel;
// DPRAM
-wire [10:0] param_phy2_addr ;
-wire [8:0] param_phy2_din, param_phy2_dout;
-wire param_phy2_ce, param_phy2_we;
+wire [10:0] param_phy0_addr, param_phy1_addr, param_phy2_addr, param_phy3_addr;
+wire [8:0] param_phy0_din, param_phy1_din, param_phy2_din, param_phy3_din;
+wire [8:0] param_phy0_dout, param_phy1_dout, param_phy2_dout, param_phy3_dout;
+wire param_phy0_ce, param_phy1_ce, param_phy2_ce, param_phy3_ce;
+wire param_phy0_we, param_phy1_we, param_phy2_we, param_phy3_we;
+wire [8:0] param_ram_0_do, param_ram_1_do, param_ram_2_do, param_ram_3_do;
wire [7:0] i2c_d_o;
wire [8:0] micro_fifo_do;
@@ -299,13 +329,18 @@ wire tx_uc_fifo_re;
wire [3:0] tx_sw_fifo_empty;
wire tx_sw_fifo_we;
-wire [1:0] tx_sw_mode0, tx_sw_mode1, tx_sw_mode2, tx_sw_mode3;
+wire [2:0] tx_sw_mode0, tx_sw_mode1, tx_sw_mode2, tx_sw_mode3;
wire tx_sw_modeu;
wire [3:0] tx_sc_done;
// 100 Mbit
wire[3:0] mode_100Mbit;
+// Flexbus
+wire fb_ad_oe;
+wire[9:0] fb_ad_o;
+reg[9:0] fb_d;
+
wire pkt_filter_sel_01, pkt_filter_sel_02, pkt_filter_sel_03;
wire pkt_filter_sel_10, pkt_filter_sel_12, pkt_filter_sel_13;
wire pkt_filter_sel_20, pkt_filter_sel_21, pkt_filter_sel_23, pkt_filter_sel_2u;
@@ -331,11 +366,10 @@ wire[7:0] sci_rddata0, sci_rddata1 ;
wire[1:0] sci_int;
// Metrics
-wire tx_metrics, metrics_start;
+wire tx_custom, metrics_start;
wire [8:0] metrics_d;
// Network Debug & Metrics
-wire sample_enable;
reg [3:0] rx_active, tx_active;
wire [3:0] mac_rx_active;
wire [3:0] drop_rx0_active, drop_rx1_active, drop_rx2_active, drop_rx3_active;
@@ -344,7 +378,14 @@ wire [3:0] mac_tx_active;
wire [3:0] rx_sc_error;
wire [3:0] rx_eop, rx_sop;
wire [3:0] tx_eop, tx_sop;
+wire [10:0] rx0_byte_cnt, rx1_byte_cnt, rx2_byte_cnt, rx3_byte_cnt;
+wire [10:0] tx0_byte_cnt, tx1_byte_cnt, tx2_byte_cnt, tx3_byte_cnt;
+
+// Debug LEDs
+reg lsm_status, rx_cdr_lol, rx_los_low;
+// Misc Debug
+wire ext_sci_int;
/****************************
*
@@ -357,11 +398,18 @@ GSR GSR_INST(.GSR(rstn));
PUR PUR_INST(.PUR(1'b1));
assign phy_mdc = clk_10;
-assign phy2_mdc = clk_10;
assign phy0_resetn = phy_resetn[0];
assign phy1_resetn = phy_resetn[1];
-assign phy2_resetn = phy_resetn[2];
+
+`ifdef SHIELD_GIGE_SMA
+ assign phy2_resetn = phy_resetn[2];
+ assign phy2_mdc = clk_10;
+`elsif SHIELD_SFP_SMA
+ assign sfp_tx_disable = 1'b0;
+ assign sfp_i2c_scl = 1'b1;
+ assign sfp_rate_select = 1'b1;
+`endif
/*
@@ -381,7 +429,7 @@ clk_gen clk_gen_0(
* main controller
*
* controls worker blocks
-* interfaces with uC via I2C
+* interfaces with uC via I2C / UART
*
*/
controller #(.ADDR_SZ( MDIO_ROM_ADDR_SZ ))controller_0
@@ -391,10 +439,11 @@ controller #(.ADDR_SZ( MDIO_ROM_ADDR_SZ ))controller_0
.init(1'b1),
.pulse_100ms( 1'b0 ),
// PCS status lines
- .pcs_rx_error( mac_int ),
+ .pcs_rx_error( pcs_error ),
.pll_lol( pll_lol ),
// link status
.port_up( phy_up ),
+// .sfp_los(sfp_los),
// mdio_controller interface
.mdio_cont_start(mdio_cont_work_start),
.mdio_cont_done(mdio_cont_work_done),
@@ -427,7 +476,7 @@ controller #(.ADDR_SZ( MDIO_ROM_ADDR_SZ ))controller_0
.mdio_mux_sel( mdio_mux_sel ),
.i2c_fifo_priority( i2c_fifo_priority ),
// TX custom packet
- .tx_metrics( tx_metrics )
+ .tx_metrics( tx_custom )
);
@@ -485,6 +534,12 @@ switch switch_0(
.rx_fifo_empty_31( rx_sf_fifo_empty_31 ),
.rx_fifo_empty_32( rx_sf_fifo_empty_32 ),
.rx_fifo_empty_u2( rx_uc_fifo_empty_u2 ),
+ // RX Byte Count
+ .rx_wr_done(rx_sc_wr_done),
+ .rx0_byte_cnt(rx0_byte_cnt),
+ .rx1_byte_cnt(rx1_byte_cnt),
+ .rx2_byte_cnt(rx2_byte_cnt),
+ .rx3_byte_cnt(rx3_byte_cnt),
// TX FIFO output from internal muxes
.tx_d0( tx_sw_fifo_d0),
.tx_d1( tx_sw_fifo_d1 ),
@@ -502,10 +557,15 @@ switch switch_0(
.tx_mode2( tx_sw_mode2 ),
.tx_mode3( tx_sw_mode3 ),
.tx_modeu( tx_modeu ),
+ // TX byte cnt
+ .tx0_byte_cnt(tx0_byte_cnt),
+ .tx1_byte_cnt(tx1_byte_cnt),
+ .tx2_byte_cnt(tx2_byte_cnt),
+ .tx3_byte_cnt(tx3_byte_cnt),
// TX state machine done flag
.tx_f( tx_sc_done ),
// TX custom packet
- .tx_metrics ( tx_metrics )
+ .tx_custom ( tx_custom )
);
@@ -517,11 +577,12 @@ mac mac_0(
.phy_resetn ( phy_resetn[0] ),
.clk( pcs_pclk ),
.tap_port ( 1'b0 ),
- // SGMII AN
- .link_timer( 1'b0 ),
- .fixed_speed(SGMII_SPEED_AN),
+ // AN
+ .phy_type(2'b00), // SGMII=0
.an_disable( 1'b0 ),
- .an_link_up( ),
+ .pulse_1_6ms(pulse_1_6ms),
+ .pulse_10ms(pulse_10ms),
+ .fixed_speed(SGMII_SPEED_AN),
.an_duplex( ),
.mode_100Mbit( mode_100Mbit[0] ),
.phy_up( phy_up[0] ),
@@ -553,7 +614,9 @@ mac mac_0(
.rx_fifo_d( rx_sc_fifo_d0 ),
.rx_error( rx_sc_error[0] ),
.rx_wr_done( rx_sc_wr_done[0] ),
+ .rx_byte_cnt(rx0_byte_cnt),
// SGMII TX / FIFO Read
+ .tx_byte_cnt_i(tx0_byte_cnt),
.tx_fifo_re( tx_sc_fifo_re[0] ),
.tx_fifo_d( tx_sw_fifo_d0 ),
.tx_fifo_empty( tx_sw_fifo_empty[0] ),
@@ -572,11 +635,11 @@ mac mac_0(
.rx_data_m3( rx0_data_m3),
.rx_data_m4( rx0_data_m4 ),
// Param RAM
- .dpr_ad( ),
- .dpr_we( ),
- .dpr_ce( ),
- .dpr_di( 9'h0),
- .dpr_do( ),
+ .dpr_ad( param_phy0_addr ),
+ .dpr_we( param_phy0_we ),
+ .dpr_ce( param_phy0_ce ),
+ .dpr_di( param_phy0_din ),
+ .dpr_do( param_phy0_dout ),
// Metrics and Interrupts
.mac_int( mac_int[0] ),
.rx_sop( rx_sop[0] ),
@@ -682,12 +745,12 @@ pkt_filter pkt_filter_02(
// filter
.new_frame ( rx_sop[0] ),
.block( rx_sf_almost_full_02 ),
- .invert( 1'b1 ),
- .trigger( trigger[0] ),
+ .invert(1'b1),
+ .trigger(trigger[0]),
.keep( rx_pf_keep_02 )
);
-drop2_fifo drop_fifo_02(
+drop_fifo drop_fifo_02(
.rstn( rstn ),
.clk ( pcs_pclk ),
.enable( 1'b1 ),
@@ -785,17 +848,39 @@ fcs fcs_0(
.dout( fcs_dout0 )
);
+/*
+ * Param RAM
+ */
+dpram param_ram_0(
+ .rstn(rstn),
+ .a_clk(clk_10),
+ .a_clk_e(param_sel[0]),
+ .a_we(mem_we),
+ .a_oe(mem_oe),
+ .a_addr(mem_addr),
+ .a_din(mem_d_i[8:0]),
+ .a_dout(param_ram_0_do),
+ // port B
+ .b_clk( pcs_pclk),
+ .b_clk_e(param_phy0_ce),
+ .b_we(param_phy0_we),
+ .b_oe( 1'b1 ),
+ .b_addr( param_phy0_addr ),
+ .b_din( param_phy0_dout ),
+ .b_dout( param_phy0_din )
+ );
mac mac_1(
.rstn( ~mac_reset[1] ),
.phy_resetn ( phy_resetn[1] ),
.clk( pcs_pclk ),
.tap_port ( 1'b0 ),
- // SGMII AN
- .link_timer( 1'b0 ),
- .fixed_speed(SGMII_SPEED_AN),
+ // AN
+ .phy_type(2'b00), // SGMII==0
.an_disable( 1'b0 ),
- .an_link_up( ),
+ .pulse_1_6ms(pulse_1_6ms),
+ .pulse_10ms(pulse_10ms),
+ .fixed_speed(SGMII_SPEED_AN),
.an_duplex( ),
.mode_100Mbit( mode_100Mbit[1] ),
.phy_up( phy_up[1] ),
@@ -827,7 +912,9 @@ mac mac_1(
.rx_fifo_d( rx_sc_fifo_d1 ),
.rx_error( rx_sc_error[1] ),
.rx_wr_done( rx_sc_wr_done[1] ),
+ .rx_byte_cnt(rx1_byte_cnt),
// SGMII TX / FIFO Read
+ .tx_byte_cnt_i(tx1_byte_cnt),
.tx_fifo_re( tx_sc_fifo_re[1] ),
.tx_fifo_d( tx_sw_fifo_d1 ),
.tx_fifo_empty( tx_sw_fifo_empty[1] ),
@@ -846,11 +933,11 @@ mac mac_1(
.rx_data_m3( rx1_data_m3),
.rx_data_m4( rx1_data_m4 ),
// Param RAM
- .dpr_ad( ),
- .dpr_we( ),
- .dpr_ce( ),
- .dpr_di( 9'h0),
- .dpr_do( ),
+ .dpr_ad( param_phy1_addr ),
+ .dpr_we( param_phy1_we),
+ .dpr_ce(param_phy1_ce ),
+ .dpr_di(param_phy1_din),
+ .dpr_do(param_phy1_dout),
// Metrics and Interrupts
.mac_int( mac_int[1] ),
.rx_sop( rx_sop[1] ),
@@ -954,7 +1041,7 @@ pkt_filter pkt_filter_12(
// filter
.new_frame ( rx_sop[1] ),
.block( rx_sf_almost_full_12 ),
- .invert( 1'b0 ),
+ .invert( 1'b1 ),
.trigger( trigger[1] ),
.keep( rx_pf_keep_12 )
);
@@ -962,7 +1049,7 @@ pkt_filter pkt_filter_12(
drop_fifo drop_fifo_12(
.rstn( rstn ),
.clk ( pcs_pclk ),
- .enable( 1'b0 ),
+ .enable(1'b1),
// control
.keep ( rx_pf_keep_12 | rx_mac_keep[1] ),
.passthrough( 1'b0 ),
@@ -1009,7 +1096,7 @@ pkt_filter pkt_filter_13(
// filter
.new_frame ( rx_sop[1] ),
.block( 1'b0 ),
- .invert( 1'b1 ),
+ .invert( 1'b0 ),
.trigger( trigger[1] ),
.keep( rx_pf_keep_13 )
);
@@ -1017,7 +1104,7 @@ pkt_filter pkt_filter_13(
drop_fifo drop_fifo_13(
.rstn( rstn ),
.clk ( pcs_pclk ),
- .enable( 1'b1 ),
+ .enable( 1'b0 ),
// control
.keep ( rx_pf_keep_13 | rx_mac_keep[1] ),
.passthrough( 1'b0 ),
@@ -1058,6 +1145,29 @@ fcs fcs_1(
.dout( fcs_dout1 )
);
+/*
+ * Param RAM
+ */
+dpram param_ram_1(
+ .rstn(rstn),
+ .a_clk(clk_10),
+ .a_clk_e(param_sel[0]),
+ .a_we(mem_we),
+ .a_oe(mem_oe),
+ .a_addr(mem_addr),
+ .a_din(mem_d_i[8:0]),
+ .a_dout(param_ram_1_do),
+ // port B
+ .b_clk( pcs_pclk),
+ .b_clk_e(param_phy1_ce),
+ .b_we(param_phy1_we),
+ .b_oe( 1'b1 ),
+ .b_addr( param_phy1_addr ),
+ .b_din( param_phy1_dout ),
+ .b_dout( param_phy1_din )
+ );
+
+
metrics metrics_2(
.rstn( rstn ),
.clk( pcs_pclk ),
@@ -1082,16 +1192,18 @@ metrics metrics_2(
);
+// GEODSS MAC
mac mac_2(
- .rstn( ~mac_reset[2] & ~sgmii_rx_los_low[2] ),
+ .rstn(~mac_reset[2]),
.phy_resetn ( phy_resetn[2] ),
.clk( pcs_pclk ),
.tap_port ( 1'b0 ),
// SGMII AN
- .link_timer( 1'b0 ),
- .fixed_speed(SGMII_SPEED_1GBIT),
+ .phy_type(2'b01), // SX==1
.an_disable( 1'b1 ),
- .an_link_up( ),
+ .pulse_1_6ms(pulse_1_6ms),
+ .pulse_10ms(pulse_10ms),
+ .fixed_speed(SGMII_SPEED_1GBIT),
.an_duplex( ),
.mode_100Mbit( mode_100Mbit[2] ),
.phy_up( phy_up[2] ),
@@ -1099,7 +1211,7 @@ mac mac_2(
.tx_mode( tx_sw_mode2 ),
.tx_f( tx_sc_done[2] ),
// PCS / SERDES health
- .rx_lsm( sgmii_lsm_status[2] ),
+ .rx_lsm( 1'b1 ), // TODO: Fix LSM for SFP
.rx_cv_err ( sgmii_rx_cv_err[2] ),
.rx_disp_err( sgmii_rx_disp_err[2] ),
.rx_cdr_lol( sgmii_rx_cdr_lol[2] ),
@@ -1120,10 +1232,12 @@ mac mac_2(
.fcs_din( fcs_dout2 ),
// SGMII RX / FIFO Write
.rx_fifo_we( rx_sc_fifo_we[2] ),
- .rx_fifo_d( rx_sc_fifo_d2 ),
+ .rx_fifo_d(rx_sc_fifo_d2),
.rx_error( rx_sc_error[2] ),
.rx_wr_done( rx_sc_wr_done[2] ),
+ .rx_byte_cnt(rx2_byte_cnt),
// SGMII TX / FIFO Read
+ .tx_byte_cnt_i(tx2_byte_cnt),
.tx_fifo_re( tx_sc_fifo_re[2] ),
.tx_fifo_d( tx_sw_fifo_d2 ),
.tx_fifo_empty( tx_sw_fifo_empty[2]),
@@ -1197,7 +1311,7 @@ pkt_filter pkt_filter_20(
// filter
.new_frame ( rx_sop[2] ),
.block( rx_sf_almost_full_20 ),
- .invert( 1'b1 ),
+ .invert( 1'b0 ),
.trigger( trigger[2] ),
.keep( rx_pf_keep_20 )
);
@@ -1205,7 +1319,7 @@ pkt_filter pkt_filter_20(
drop_fifo drop_fifo_20(
.rstn( rstn ),
.clk ( pcs_pclk ),
- .enable( 1'b1 ),
+ .enable( 1'b0 ),
// control
.keep ( rx_pf_keep_20 | rx_mac_keep[2] ),
.passthrough( 1'b0 ),
@@ -1220,8 +1334,7 @@ drop_fifo drop_fifo_20(
.active( drop_rx2_active[0] )
);
-
-sync4_fifo sync_fifo_rx_20(
+sync_fifo sync_fifo_rx_20(
.rstn( rstn ),
.clk ( pcs_pclk ),
// input / RX
@@ -1331,6 +1444,7 @@ drop_fifo drop_fifo_2u(
.active( )
);
+// TODO: add a flag on we to keep UC from being overwritten
sync_fifo sync_fifo_rx_2u(
.rstn( rstn ),
.clk ( pcs_pclk ),
@@ -1357,16 +1471,18 @@ fcs fcs_2(
.dout( fcs_dout2 )
);
+// GEODSS SMA (MAC is bypassed)
mac mac_3(
.rstn( ~mac_reset[3] & ~sgmii_rx_los_low[3] ),
.phy_resetn ( phy_resetn[3] ),
.clk( pcs_pclk ),
.tap_port ( 1'b0 ),
- // SGMII AN
- .link_timer( 1'b0 ),
+ // SGMII AN
+ .phy_type(2'b11), // SMA=3
+ .an_disable(1'b1),
+ .pulse_1_6ms(pulse_1_6ms),
+ .pulse_10ms(pulse_10ms),
.fixed_speed(SGMII_SPEED_1GBIT),
- .an_disable( 1'b1 ),
- .an_link_up( ),
.an_duplex( ),
.mode_100Mbit( mode_100Mbit[3] ),
.phy_up( phy_up[3] ),
@@ -1398,7 +1514,9 @@ mac mac_3(
.rx_fifo_d( rx_sc_fifo_d3 ),
.rx_error( rx_sc_error[3] ),
.rx_wr_done( rx_sc_wr_done[3] ),
+ .rx_byte_cnt(rx3_byte_cnt),
// SGMII TX / FIFO Read
+ .tx_byte_cnt_i(tx3_byte_cnt),
.tx_fifo_re( tx_sc_fifo_re[3] ),
.tx_fifo_d( tx_sw_fifo_d3 ),
.tx_fifo_empty( tx_sw_fifo_empty[3] ),
@@ -1530,7 +1648,7 @@ pkt_filter pkt_filter_31(
// filter
.new_frame ( rx_sop[3] ),
.block( 1'b0 ),
- .invert( 1'b1 ),
+ .invert( 1'b0 ),
.trigger( trigger[3] ),
.keep( rx_pf_keep_31 )
);
@@ -1538,7 +1656,7 @@ pkt_filter pkt_filter_31(
drop_fifo drop_fifo_31(
.rstn( rstn ),
.clk ( pcs_pclk ),
- .enable( 1'b1 ),
+ .enable( 1'b0 ),
// control
.keep ( rx_pf_keep_31 | rx_mac_keep[3] ),
.passthrough( 1'b0 ),
@@ -1618,27 +1736,61 @@ half_fifo #(.DPRAM_DEPTH(9)) micro_fifo_0 (
* Param RAM
*/
dpram param_ram_2(
- .rstn( rstn ),
- .a_clk( fb_clk ),
- .a_clk_e( param_sel[2] ),
- .a_we( mem_we ),
- .a_oe( 1'b0 ),
- .a_addr( mem_addr ),
- .a_din( mem_d_i[8:0] ),
- .a_dout( ),
+ .rstn(rstn),
+ .a_clk(clk_10),
+ .a_clk_e(param_sel[2]),
+ .a_we(mem_we),
+ .a_oe(mem_oe),
+ .a_addr(mem_addr),
+ .a_din(mem_d_i[8:0]),
+ .a_dout(param_ram_2_do),
// port B
- .b_clk( pcs_pclk ),
- .b_clk_e( param_phy2_ce ),
- .b_we( param_phy2_we ),
+ .b_clk( pcs_pclk),
+ .b_clk_e(param_phy2_ce),
+ .b_we(param_phy2_we),
.b_oe( 1'b1 ),
.b_addr( param_phy2_addr ),
.b_din( param_phy2_dout ),
.b_dout( param_phy2_din )
);
+
+//defparam param_ram_2.dp16kd_inst.INITVAL_00 = "00000000000000000000000000000000000000000000000000000000000000000022E10069F00800";
+
+
+
+/*
+* PCS Notes:
+* All _c control signals are asynch in the SERDES/PCS
+* All _s control signals are asynch and should be clocked before being used
+* TxPLL provides system clock for FPGA logic
+* tx_full_clk uses wire name 'txclk' and feeds both txi_clk and rxi_clk, as shown in Figure 9-27
+* For SGMII, tx_pclk is fed back internally to rxi_clk and ebrd_clk
+* ebrd_clk: CTC FIFO Read Clock per Channel
+*
+*/
+
+assign ext_sci_int = sci_int[0];
+
+/*
+PCSCLKDIV pcsclkdiv0 (
+ .RST( ~rstn ),
+ .CLKI( refclko ),
+ .SEL2( 1'b1 ), // 101 is div by 8
+ .SEL1( 1'b0 ),
+ .SEL0( 1'b1 ),
+ .CDIV1( ),
+ .CDIVX( )
+);
+*/
/*
* PCS block that encapsulates two DCUs and the SCI block
*/
+ assign pcs_error[0] = sgmii_rx_cv_err[0] | sgmii_rx_cdr_lol[0] | !sgmii_lsm_status[0] | sgmii_rx_los_low[0];
+ assign pcs_error[1] = sgmii_rx_cv_err[1] | sgmii_rx_cdr_lol[1] | !sgmii_lsm_status[1] | sgmii_rx_los_low[1];
+ assign pcs_error[2] = sgmii_rx_cv_err[2] | sgmii_rx_cdr_lol[2] | sgmii_rx_los_low[2];
+ assign pcs_error[3] = sgmii_rx_cv_err[3] | sgmii_rx_cdr_lol[3] | sgmii_rx_los_low[3];
+
pcs pcs_0 (
.refclk0_refclkn(refclkp_d0),
@@ -1655,7 +1807,7 @@ pcs pcs_0 (
.sgmii0_hdoutp(sgmii0_hdoutp),
// DCU resets
- .sgmii0_tx_serdes_rst_c( tx_serdes_rst[0] ), // rset LOL signal in PLL
+ .sgmii0_tx_serdes_rst_c( tx_serdes_rst[0] ), // rset LOL signal in PLL TODO: change this
.sgmii0_rst_dual_c( pcs_rst_dual[0] ), // resets all serdes channels including aux and PCS
.sgmii0_serdes_rst_dual_c( serdes_rst_dual[0] ), // resets serdes dual gated by fpga_reset_enable
@@ -1678,7 +1830,7 @@ pcs pcs_0 (
.sgmii0_tx_disp_correct(sgmii_tx_disp_correct[0]),
.sgmii0_tx_k(sgmii_tx_k[0]),
.sgmii0_txdata( tx_data0 ),
- .sgmii0_xmit(1'b0),
+ .sgmii0_xmit(1'b0), //TODO: Auto Neg state machine
.sgmii0_signal_detect_c(1'b1),
.sgmii0_rx_cv_err( sgmii_rx_cv_err[0] ), // code violation with associated data, PCS will drive 0xEE and K=1 (Table 9-4)
.sgmii0_rx_disp_err( sgmii_rx_disp_err[0] ),
@@ -1724,7 +1876,7 @@ pcs pcs_0 (
.sgmii1_tx_disp_correct( sgmii_tx_disp_correct[1] ),
.sgmii1_tx_k( sgmii_tx_k[1] ),
.sgmii1_txdata( tx_data1 ),
- .sgmii1_xmit( 1'b0 ),
+ .sgmii1_xmit( 1'b0 ), // TODO: Auto Negotiation Bit
.sgmii1_signal_detect_c( 1'b1 ),
@@ -1769,7 +1921,7 @@ pcs pcs_0 (
.sgmii2_rxdata( rx_data2 ),
.sgmii2_tx_disp_correct( sgmii_tx_disp_correct[2] ),
.sgmii2_tx_k( sgmii_tx_k[2] ),
- .sgmii2_txdata( tx_data2 ),
+ .sgmii2_txdata( tx_data2 ),
.sgmii2_xmit( 1'b0 ),
.sgmii2_signal_detect_c( 1'b1 ),
@@ -1812,10 +1964,14 @@ pcs pcs_0 (
.sgmii3_rx_k( sgmii_rx_k[3] ),
.sgmii3_rxdata( rx_data3 ),
.sgmii3_tx_disp_correct( sgmii_tx_disp_correct[3] ),
+`ifdef SHIELD_SFP_SMA
+ .sgmii3_tx_k(rx2_k_m1), // MAC 2 RX k
+ .sgmii3_txdata(rx2_data_m1), // MAC 2 RX data
+`else
.sgmii3_tx_k( sgmii_tx_k[3] ),
- .sgmii3_txdata( tx_data3 ),
- .sgmii3_xmit( 1'b0 ),
-
+ .sgmii3_txdata( tx_data3 ),
+`endif
+ .sgmii3_xmit( 1'b0 ), // TODO: Auto Negotiation Bit
.sgmii3_signal_detect_c( 1'b1 ),
.sgmii3_ctc_del_s(),
@@ -1864,7 +2020,13 @@ pcs pcs_0 (
);
-
+// Link Timer for AN
+link_timer link_timer_0(
+ .rstn(rstn),
+ .clk(pcs_pclk),
+ .pulse_1_6ms(pulse_1_6ms),
+ .pulse_10ms(pulse_10ms)
+);
mdio_controller #(.ADDR_SZ( MDIO_ROM_ADDR_SZ )) mdio_controller_0
(
@@ -1883,6 +2045,18 @@ mdio_controller #(.ADDR_SZ( MDIO_ROM_ADDR_SZ )) mdio_controller_0
.rwn(mdio_rwn),
.done(mdio_done)
);
+
+`ifdef PHY_MARVELL
+mdio_data_mvl #(.ADDR_SZ( MDIO_ROM_ADDR_SZ )) mdio_data_mvl_0(
+ .ad( rom_a ),
+ .page( mdio_page_set ),
+ .reg_addr( mdio_reg_addr_set ),
+ .data_in_h( mdio_w_data_h_set ),
+ .data_in_l( mdio_w_data_l_set ),
+ .d( rom_d ),
+ .oe( ~mdio_mux_sel[1] )
+);
+`endif
mdio_data_ti #(.ADDR_SZ( MDIO_ROM_ADDR_SZ )) mdio_data_ti_0(
.ad( rom_a ),
@@ -1900,7 +2074,7 @@ always @(*) begin
case (mdio_mux_sel)
2'b00: mdi = phy0_mdio;
2'b01: mdi = phy1_mdio;
- 2'b10: mdi = phy2_mdio;
+ 2'b10: mdi = phy2_mdio; // compile as 0 if GIGE_SHIELD isn't defined
2'b11: mdi = 1'b1;
endcase
end
@@ -1934,9 +2108,9 @@ spi spi_0 (
.rstn(rstn),
.clk(clk_10),
// spi signals
- .spi_cs( fpga_spics ),
- .spi_clk( fpga_mclk ),
- .spi_d_in( fpga_mosi),
+ .spi_cs( spi_cs ),
+ .spi_clk( spi_clk ),
+ .spi_d_in( spi_mosi),
.spi_d_o( spi_do ),
.spi_d_oe(spi_do_e ),
// internal FPGA memory
@@ -1970,7 +2144,7 @@ spi spi_0 (
.sci_sel_ch( sci_sel_ch )
);
-assign fpga_miso = spi_do_e ? spi_do : 1'bz;
+assign spi_miso = spi_do_e ? spi_do : 1'bz;
/* data mux out of internal memories */
always@(*)
@@ -1981,11 +2155,74 @@ begin
5'b00010: mem_d_o = { 1'b0, micro_fifo_do };
5'b00011: mem_d_o = { 1'b0, micro_fifo_do };
5'b00100: mem_d_o = { 1'b0, micro_fifo_do };
+ 5'b01000: mem_d_o = param_ram_0_do;
+ 5'b01001: mem_d_o = param_ram_1_do;
+ 5'b01010: mem_d_o = param_ram_2_do;
+ 5'b01011: mem_d_o = param_ram_3_do;
5'b10000: mem_d_o = { 2'b0, int_do };
default: mem_d_o = 9'h0;
endcase
end
+`ifdef DARSENA_V01
+
+// only drive the FB AD bus when OE is asserted
+assign fb_ad = fb_ad_oe ? fb_d : 10'bz;
+
+
+always@(*)
+ begin
+ case({fb_cregs_sel,mem_do_mux_sel})
+ 6'b000000: fb_d = { 2'b0, sci_rddata1 };
+ 6'b000001: fb_d = { 2'b0, sci_rddata0 };
+ 6'b000010: fb_d = { 1'b0, micro_fifo_do };
+ 6'b000011: fb_d = { 1'b0, micro_fifo_do };
+ 6'b000100: fb_d = { 1'b0, micro_fifo_do };
+ 6'b010000: fb_d = { 2'b0, int_do };
+ default: fb_d = fb_ad_o;
+ endcase
+ end
+
+
+flexbus flexbus_0(
+ .clk( fb_clk ),
+ .rstn( rstn ),
+ // strobes
+ .fb_ale( fb_ale ),
+ .fb_oen( fb_oen ),
+ .fb_rwn( fb_rwn ),
+ .fb_csn( fb_csn ),
+ // control
+ .cregs_sel( fb_cregs_sel ),
+ // muxed addr and data
+ .fb_ad_i( fb_ad ),
+ .fb_ad_o( fb_ad_o ),
+ .fb_ad_oe( fb_ad_oe ),
+ // sys mem
+ .mem_addr( mem_addr ),
+ .mux_sel ( mem_do_mux_sel ),
+ // dpram controls
+ .dpram_we( mem_we ),
+ .dpram_oe( mem_oe ),
+ .dpram_tx_sel( dpram_tx_sel ),
+ .dpram_rx_sel( dpram_rx_sel ),
+ .dpram_ptrs_sel( dpram_ptrs_sel ),
+ .param_sel( param_sel ),
+ .pkt_filter_sel_01( pkt_filter_sel_01 ),
+ .pkt_filter_sel_02( pkt_filter_sel_02 ),
+ .pkt_filter_sel_10( pkt_filter_sel_10 ),
+ .pkt_filter_sel_12( pkt_filter_sel_12 ),
+ .pkt_filter_sel_20( pkt_filter_sel_20 ),
+ .pkt_filter_sel_21( pkt_filter_sel_21 ),
+ .pkt_filter_sel_23( pkt_filter_sel_23 ),
+ .interrupts_sel( int_sel ),
+ // SCI I/F
+ .sci_sel_dual( sci_sel_dual ),
+ .sci_sel_ch( sci_sel_ch )
+);
+
+`endif
+
interrupts interrupts_0(
.rstn( rstn ),
.clk( pcs_pclk ),
@@ -2000,7 +2237,7 @@ interrupts interrupts_0(
.cont_int( micro_fifo_int ),
.phy_int ( { 2'b0, phy1_intn, phy0_intn }),
.mac_int ( { mac_int[3], mac_int[2], mac_int[1], mac_int[0] } ),
- .int_o( fpga_int )
+ .int_o( )
);
@@ -2036,7 +2273,8 @@ i2c i2c_0(
/*
* ext_sys_fifo delays and enables:
-* we need the re delay since we need to generate a re pulse from the
+* we need the re delay since we need to generate a re pulse from the
+* uart block, which is clocked at a slower rate.
* we need the mdio_we delay since the fifo is clocked twice: high and low data
*
*/
@@ -2049,12 +2287,12 @@ always@ ( posedge clk_10 or negedge rstn )
end
else
begin
- cont_fifo_re_m1 <= i2c_fifo_re;
+ cont_fifo_re_m1 <= uart_fifo_re | i2c_fifo_re;
cont_fifo_re_m2 <= cont_fifo_re_m1;
end
end
-// create a single re pulse since i2c runs slow.
+// create a single re pulse since uart runs slow.
assign i_cont_fifo_re = cont_fifo_re_m1 & ~cont_fifo_re_m2;
assign bin_to_ascii_we = mdio_rd_we | cont_rd_we;
@@ -2062,7 +2300,7 @@ assign bin_to_ascii_d_in = read_fifo_mux_sel ? mdio_rd : cont_rd;
/*
* Input: MDIO writes
- * Output: I2C read FIFO
+ * Output: UART/I2C read FIFO
*/
bin_to_ascii bin_to_ascii_0(
.rstn( rstn ),
@@ -2082,7 +2320,7 @@ bin_to_ascii bin_to_ascii_0(
/*
* Input: bin_to_ascii
- * Output: I2C read
+ * Output: I2C or UART read
*/
sync_fifo ext_sys_fifo_0(
.rstn( rstn ),
@@ -2100,78 +2338,95 @@ sync_fifo ext_sys_fifo_0(
.active( )
);
+always @(*) begin
+ case (mdio_mux_sel)
+ 2'b00: rx_cdr_lol = sgmii_rx_cdr_lol[0];
+ 2'b01: rx_cdr_lol = sgmii_rx_cdr_lol[1];
+ 2'b10: rx_cdr_lol = sgmii_rx_cdr_lol[2];
+ 2'b11: rx_cdr_lol = 1'b1;
+ endcase
+end
-/* JTAG Enable for 2-bit external buffer */
-assign fpga_jtag_e =1'bz;
+always @(*) begin
+ case (mdio_mux_sel)
+ 2'b00: lsm_status = sgmii_lsm_status[0];
+ 2'b01: lsm_status = sgmii_lsm_status[1];
+ 2'b10: lsm_status = sgmii_lsm_status[2];
+ 2'b11: lsm_status = 1'b1;
+ endcase
+end
+always @(*) begin
+ case (mdio_mux_sel)
+ 2'b00: rx_los_low = sgmii_rx_los_low[0];
+ 2'b01: rx_los_low = sgmii_rx_los_low[1];
+ 2'b10: rx_los_low = sgmii_rx_los_low[2];
+ 2'b11: rx_los_low = 1'b1;
+ endcase
+end
+
+/* Debug and Arduino Expansion */
-/* LED Assignment */
assign led[0] = 1'b1;
assign led[1] = phy_up[0];
assign led[2] = phy_up[1];
-
-
-/* Debug: rx_active and tx_active
- * Intention is to use these as sample enables in Reveal or
- * external triggering
- */
-always @(posedge pcs_pclk or negedge rstn)
- if ( !rstn )
- rx_active[2] <= 1'b0;
- else if (mac_rx_active[2] || drop_rx2_active[0] || sync_rx2_active[0] )
- rx_active[2] <= 1'b1;
- else
- rx_active[2] <= 1'b0;
-
-always @(posedge pcs_pclk or negedge rstn)
- if ( !rstn )
- tx_active[0] <= 1'b0;
- else if (mac_tx_active[0])
- tx_active[0] <= 1'b1;
- else
- tx_active[0] <= 1'b0;
-
-assign sample_enable = rx_active[2] | tx_active[0];
-
-
-/* Debug and Arduino Expansion, see definitions.v */
+
`ifdef DEBUG_SPI
- assign ard_scl = fpga_mclk;
- assign ard_sda = fpga_spics;
+ assign ard_scl = spi_clk;
+ assign ard_sda = spi_cs;
assign ard_rxd1 = spi_do_e ? spi_do : 1'bz;
- assign ard_txd1 = fpga_mosi;
+ assign ard_txd1 = spi_mosi;
`elsif DEBUG_MDIO
assign ard_scl = phy_mdc;
assign ard_sda = phy0_mdio;
assign ard_rxd1 = 1'bz;
assign ard_txd1 = refclko;
-`elsif DEBUG_I2C
+`elsif DEBUG_IC2
assign ard_scl = i2c_scl;
assign ard_sda = sda_oe ? sda_o : i2c_sda;
assign ard_rxd1 = 1'bz;
assign ard_txd1 = sda_oe;
`else
- assign ard_scl = fpga_int;
+ assign ard_scl = rx_sop[0];
assign ard_sda = 1'bz;
- assign ard_rxd1 = 1'bz;
- assign ard_txd1 = 1'bz;
`endif
`ifdef ARD_EXP_UART
assign ard_txd2 = uart_txd;
assign uart_rxd = ard_rxd2;
+ assign ftdi_tdi_rxd = 1'bz;
`else
- assign ftdi_tdi_rxd = uart_txd;
- assign uart_rxd = ftdi_tck_txd;
+
+ // assign uart_rxd = ftdi_tck_txd;
`endif
- assign pe0 = 1'bz;
- assign pe1 = 1'bz;
- assign pe3 = 1'bz;
- assign pe4 = 1'bz;
- assign pe5 = 1'bz;
+ assign ftdi_tdi_rxd = 1'bz;
+
+ assign pe1 = pcs_error[2]; // RX data on SFP good
+ assign pe4 = ~sgmii_tx_k[2];
+ assign pe5 = phy1_gpio[1];
assign pg5 = 1'bz;
- assign ph3 = 1'bz;
- assign ph4 = 1'bz;
+ assign pe3 = fpga_gpio;
+
+`ifdef SHIELD_SFP_SMA
+
+ // SFP UART testing
+ assign uart_rxd = ph3;
+ assign ph4 = uart_txd;
+
+ // SFP LEDS
+ assign sfp_led1 = !sfp_pres_n;
+ assign sfp_led2 = !sfp_tx_fault;
+ assign sfp_led3 = !sfp_los;
+ assign sfp_led4 = !pcs_error[2];
+ assign sfp_led5 = phy_up[0];
+ assign sfp_led6 = !mac_tx_active[0];
+`endif
+
+ assign fpga_int = pcs_error[2] | pcs_error[3];
+`ifdef DARSENA_V02
+ assign fpga_jtag_e =1'b1;
+`endif
+
endmodule



X-ray Engineering Services