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authormindchasers <privateisland@mindchasers.com>2020-11-26 16:49:13 -0500
committermindchasers <privateisland@mindchasers.com>2020-11-26 16:49:13 -0500
commit447c51f54516832e72eb71dd3b21b4cb549c4aff (patch)
treebf27b23b634d27aa115d2636fa4614ee9d09ee9b
parent418d6a06c539854c326a7099208080a92ae8ddb1 (diff)
project: remove DARSENA_V01 support and minor cleanup
-rw-r--r--manufacturer/lattice/ecp5um/privateisland.ldf5
-rw-r--r--manufacturer/lattice/ecp5um/source/top.v73
-rw-r--r--source/directives.v1
3 files changed, 7 insertions, 72 deletions
diff --git a/manufacturer/lattice/ecp5um/privateisland.ldf b/manufacturer/lattice/ecp5um/privateisland.ldf
index 1968d1b..ede192c 100644
--- a/manufacturer/lattice/ecp5um/privateisland.ldf
+++ b/manufacturer/lattice/ecp5um/privateisland.ldf
@@ -6,12 +6,13 @@
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="darsena">
<Options>
<Option name="HDL type" value="Verilog"/>
- <Option name="include path" value="remote_files/include"/>
+ <Option name="def_top" value="top"/>
+ <Option name="include path" value="../../../source"/>
<Option name="lib" value="work"/>
<Option name="top" value="top"/>
</Options>
<Source name="source/top.v" type="Verilog" type_short="Verilog">
- <Options/>
+ <Options top_module="top"/>
</Source>
<Source name="../../../source/bin_to_ascii.v" type="Verilog" type_short="Verilog">
<Options/>
diff --git a/manufacturer/lattice/ecp5um/source/top.v b/manufacturer/lattice/ecp5um/source/top.v
index 4944bae..5ef9727 100644
--- a/manufacturer/lattice/ecp5um/source/top.v
+++ b/manufacturer/lattice/ecp5um/source/top.v
@@ -18,6 +18,8 @@
* Private Island Top for Darsena / ECP5UM
*
*/
+
+ `include "directives.v"
module top(
input rstn,
@@ -125,20 +127,11 @@ module top(
inout [9:0] pa
);
-`include "directives.v"
+
+
`include "sgmii_params.v"
`include "ethernet_params.v"
-`ifdef DARSENA_V01
- wire fb_clk;
- wire fb_ale;
- wire fb_oen;
- wire fb_rwn;
- wire fb_csn;
- wire fb_cregs_sel;
- wire [9:0] fb_ad;
-`endif
-
/* PARAMS */
localparam MDIO_ROM_ADDR_SZ = 7;
@@ -2164,64 +2157,6 @@ begin
endcase
end
-`ifdef DARSENA_V01
-
-// only drive the FB AD bus when OE is asserted
-assign fb_ad = fb_ad_oe ? fb_d : 10'bz;
-
-
-always@(*)
- begin
- case({fb_cregs_sel,mem_do_mux_sel})
- 6'b000000: fb_d = { 2'b0, sci_rddata1 };
- 6'b000001: fb_d = { 2'b0, sci_rddata0 };
- 6'b000010: fb_d = { 1'b0, micro_fifo_do };
- 6'b000011: fb_d = { 1'b0, micro_fifo_do };
- 6'b000100: fb_d = { 1'b0, micro_fifo_do };
- 6'b010000: fb_d = { 2'b0, int_do };
- default: fb_d = fb_ad_o;
- endcase
- end
-
-
-flexbus flexbus_0(
- .clk( fb_clk ),
- .rstn( rstn ),
- // strobes
- .fb_ale( fb_ale ),
- .fb_oen( fb_oen ),
- .fb_rwn( fb_rwn ),
- .fb_csn( fb_csn ),
- // control
- .cregs_sel( fb_cregs_sel ),
- // muxed addr and data
- .fb_ad_i( fb_ad ),
- .fb_ad_o( fb_ad_o ),
- .fb_ad_oe( fb_ad_oe ),
- // sys mem
- .mem_addr( mem_addr ),
- .mux_sel ( mem_do_mux_sel ),
- // dpram controls
- .dpram_we( mem_we ),
- .dpram_oe( mem_oe ),
- .dpram_tx_sel( dpram_tx_sel ),
- .dpram_rx_sel( dpram_rx_sel ),
- .dpram_ptrs_sel( dpram_ptrs_sel ),
- .param_sel( param_sel ),
- .pkt_filter_sel_01( pkt_filter_sel_01 ),
- .pkt_filter_sel_02( pkt_filter_sel_02 ),
- .pkt_filter_sel_10( pkt_filter_sel_10 ),
- .pkt_filter_sel_12( pkt_filter_sel_12 ),
- .pkt_filter_sel_20( pkt_filter_sel_20 ),
- .pkt_filter_sel_21( pkt_filter_sel_21 ),
- .pkt_filter_sel_23( pkt_filter_sel_23 ),
- .interrupts_sel( int_sel ),
- // SCI I/F
- .sci_sel_dual( sci_sel_dual ),
- .sci_sel_ch( sci_sel_ch )
-);
-
-`endif
interrupts interrupts_0(
.rstn( rstn ),
diff --git a/source/directives.v b/source/directives.v
index f34c3f0..97e6458 100644
--- a/source/directives.v
+++ b/source/directives.v
@@ -25,7 +25,6 @@
//`define DEBUG_SPI
// `define ARD_EXP_UART
-//`define DARSENA_V01
`define DARSENA_V02
//`define DARSENA_V03



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