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authormindchasers <privateisland@mindchasers.com>2020-11-19 22:25:59 -0500
committermindchasers <privateisland@mindchasers.com>2020-11-19 22:25:59 -0500
commit0b2b931a6324c03b9a38fb4926cb7e64e6ebf6f2 (patch)
treea9182c5d8701dff22bd65180819d060c69fb05ac
parent9c58cebcab713f6fd959163d6bbf0e2b9b412b19 (diff)
fifos: remove specific sized fifos
-rw-r--r--source/drop2_fifo.v255
-rw-r--r--source/sync2_fifo.v141
-rw-r--r--source/sync4_fifo.v206
3 files changed, 0 insertions, 602 deletions
diff --git a/source/drop2_fifo.v b/source/drop2_fifo.v
deleted file mode 100644
index dcadd92..0000000
--- a/source/drop2_fifo.v
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
- * drop2_fifo.v
- *
- * Copyright (C) 2018, 2019 Mind Chasers Inc.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * function: Double buffered side-by-side FIFO
- * Uses 2 DPRAMs with additional logic for paths involving 1G to 100Mbit
- *
- */
-
-`timescale 1ns /10ps
-
-module drop2_fifo(
- input rstn,
- input clk,
- input enable,
-
- // control (drop, keep, and done are asserted for one clock )
- input keep, // this packet won't be dropped, start transferring it (KEEPS ARE AND'ED)
- input passthrough, // don't store data, write through instead
-
- // input
- input we_in,
- input wr_done,
- input [8:0] d_in,
-
- // output
- output we_out,
- output reg [8:0] d_out,
-
- // debug
- output reg active
-);
-
-// local parameters and includes
-
-
-// nets and registers
-
-// the msbit of the ptr selects the DPRAM
-reg [11:0] wr_ptr;
-reg [11:0] rd_ptr;
-
-wire [8:0] d_out_0, d_out_1, d_out_internal;
-
-reg read_run, read_run_m1; // read continues while read_run is set
-reg i_we_out, i_we_out_m1; // internal we_out
-wire re; // read enable for dpram
-reg rd_done_p1, rd_done;
-wire i_keep;
-reg kept;
-
-assign i_keep = keep & enable;
-
-wire dpram0_a_clk_e, dpram1_a_clk_e;
-wire dpram0_b_clk_e, dpram1_b_clk_e;
-
-/*
- * kept: assert for length of write duration after keep asserts
- */
-always @(posedge clk, negedge rstn)
- if( !rstn )
- kept <= 1'b0;
- else if ( wr_done )
- kept <= 1'b0;
- else if ( i_keep )
- kept <= 1'b1;
-
-/*
- * read_run logic
- * read starts after wr_done
- * continues until the FIFO is empty
- */
-always @(posedge clk, negedge rstn)
- if( !rstn )
- begin
- read_run <= 1'b0;
- read_run_m1 <= 1'b0;
- end
- else if ( rd_done_p1 )
- begin
- read_run <= 1'b0;
- read_run_m1 <= 1'b0;
- end
- else if ( kept && wr_done )
- begin
- read_run <= 1'b1;
- end
- else
- read_run_m1 <= read_run;
-
-assign re = read_run;
-
-/*
- * we_out logic
- * delayed version of re
- */
-always @(posedge clk, negedge rstn)
- if( !rstn )
- i_we_out <= 1'b0;
- else if ( read_run && read_run_m1 )
- i_we_out <= 1'b1;
- else
- i_we_out <= 1'b0;
-
-always @(posedge clk, negedge rstn)
- if( !rstn )
- i_we_out_m1 <= 1'b0;
- else
- i_we_out_m1 <= i_we_out;
-
-// OR these two signals to stretch we_out to the last byte from FIFO
-assign we_out = i_we_out | i_we_out_m1;
-
-/*
- * upper / lower half DPRAM logic
- * directs upper or lower write buffer in FIFO
- * toggle on each done event (rx_data is complete)
- * don't toggle on a drop event (reuse buffer)
- */
-always @(posedge clk, negedge rstn)
- if ( !rstn )
- wr_ptr[11] <= 1'b0; // init to the lower bank
- else if ( wr_done && kept )
- wr_ptr[11] <= ~wr_ptr[11];
-
-/*
- * wr_ptr logic excluding msbit
- * reset pointer when wr_done
- */
-always @(posedge clk, negedge rstn)
- if( !rstn )
- wr_ptr[10:0] <= 'd0;
- else if ( wr_done )
- wr_ptr[10:0] <= 'd0;
- else if ( we_in )
- wr_ptr[10:0] <= wr_ptr[10:0] + 1;
-
-/*
- * each time the FIFO is empty, set rd_ptr[11] to wr_ptr[11]
- * FIFO becomes empty through reading
- */
-always @(posedge clk, negedge rstn)
- if ( !rstn )
- rd_ptr[11] <= 1'b0; // init to the lower bank
- else if ( rd_done )
- rd_ptr[11] <= wr_ptr[11];
-
-/*
- * rd_ptr logic excluding msbit
- */
-always @(posedge clk, negedge rstn)
- if( !rstn )
- rd_ptr[10:0] <= 'd0;
- else if ( rd_done )
- rd_ptr[10:0] <= 'd0;
- else if ( re )
- rd_ptr[10:0] <= rd_ptr[10:0] + 1;
-
-/*
- * d_out register
- *
- */
-always @(posedge clk, negedge rstn)
- if( !rstn )
- d_out <= 'd0;
- else
- d_out <= d_out_internal;
-
-
-/*
-* rd_done logic
-*/
-always @(posedge clk, negedge rstn)
- if( !rstn )
- begin
- rd_done_p1 <= 1'b0;
- rd_done <= 1'b0;
- end
- else
- begin
- rd_done_p1 <= d_out_internal[8];
- rd_done <= rd_done_p1;
- end
-
-// debug
-always @(posedge clk, negedge rstn)
- if( !rstn )
- active <= 1'b0;
- else if ( we_in || we_out )
- active <= 1'b1;
- else
- active <= 1'b0;
-
-assign dpram0_a_clk_e = ~wr_ptr[11];
-assign dpram1_a_clk_e = wr_ptr[11];
-
-assign dpram0_b_clk_e = ~rd_ptr[11];
-assign dpram1_b_clk_e = rd_ptr[11];
-
-assign d_out_internal = dpram0_b_clk_e ? d_out_0 : d_out_1;
-
-
-dpram dpram_0(
-.rstn( rstn ),
-.a_clk( clk ),
-.a_clk_e( dpram0_a_clk_e ),
-.a_we( we_in ),
-.a_oe( 1'b0 ),
-.a_addr( wr_ptr[10:0] ),
-.a_din( d_in ),
-.a_dout( ),
-// port B
-.b_clk( clk ),
-.b_clk_e( dpram0_b_clk_e ),
-.b_we( 1'b0 ),
-.b_oe( re ),
-.b_addr( rd_ptr[10:0] ),
-.b_din( 9'h0 ),
-.b_dout( d_out_0 )
-);
-
-dpram dpram_1(
- .rstn( rstn ),
- .a_clk( clk ),
- .a_clk_e( dpram1_a_clk_e ),
- .a_we( we_in ),
- .a_oe( 1'b0 ),
- .a_addr( wr_ptr[10:0] ),
- .a_din( d_in ),
- .a_dout( ),
- // port B
- .b_clk( clk ),
- .b_clk_e( dpram1_b_clk_e ),
- .b_we( 1'b0 ),
- .b_oe( re ),
- .b_addr( rd_ptr[10:0] ),
- .b_din( 9'h0 ),
- .b_dout( d_out_1 )
-);
-
-
-endmodule
diff --git a/source/sync2_fifo.v b/source/sync2_fifo.v
deleted file mode 100644
index 029cfce..0000000
--- a/source/sync2_fifo.v
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * sync2_fifo.v
- *
- * Copyright (C) 2018, 2019 Mind Chasers Inc.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * function: Multi Buffered Sync FIFO suitable for rate conversion from 1G to 100 Mbit
- *
- *
- */
-
-
-`timescale 1ns /10ps
-
-module sync2_fifo #(parameter FIFO_PTR = 12,
- FIFO_WIDTH = 9,
- FIFO_DEPTH = 4096 )
-(
- input rstn,
- input clk,
-
-
- // input
- input we,
- input [FIFO_WIDTH-1:0] d_in,
-
- // output
- input re,
- output [FIFO_WIDTH-1:0] d_out,
- output empty,
- output almost_full,
-
- // fifo_control
- input reset_ptrs
-
-);
-
-`include "ethernet_params.v"
-
-
-reg [FIFO_PTR-1:0] wr_ptr;
-reg [FIFO_PTR-1:0] rd_ptr;
-reg [FIFO_PTR:0] bytes; // use for size calculation below
-
-wire [FIFO_WIDTH-1:0] d_out_0, d_out_1, d_out_internal;
-
-wire dpram0_a_clk_e, dpram1_a_clk_e;
-wire dpram0_b_clk_e, dpram1_b_clk_e;
-
-
-always @(posedge clk, negedge rstn)
- if( !rstn )
- wr_ptr <= 'd0;
- else if ( reset_ptrs )
- wr_ptr <= 'd0;
- else if ( we )
- wr_ptr <= wr_ptr + 1;
-
-/*
- * rd_ptr
- * use empty flat to make sure rd_ptr doesn't advance when empty ( error condition )
- */
-always @(posedge clk, negedge rstn)
- if( !rstn )
- rd_ptr <= 'd0;
- else if ( reset_ptrs )
- rd_ptr <= 'd0;
- else if ( re && !empty )
- rd_ptr <= rd_ptr + 1;
-
-assign empty = ( rd_ptr == wr_ptr ) ? 1'b1 : 1'b0;
-
-// leave room for a MTU frame
-assign almost_full = bytes > FIFO_DEPTH-MTU ? 1'b1 : 1'b0;
-
-always @(posedge clk, negedge rstn)
- if( !rstn )
- bytes <= 'd0;
- else if ( wr_ptr >= rd_ptr )
- bytes <= wr_ptr - rd_ptr;
- else
- bytes <= (wr_ptr - rd_ptr)+FIFO_DEPTH;
-
- assign dpram0_a_clk_e = ~wr_ptr[FIFO_PTR-1];
- assign dpram1_a_clk_e = wr_ptr[FIFO_PTR-1];
-
- assign dpram0_b_clk_e = ~rd_ptr[FIFO_PTR-1];
- assign dpram1_b_clk_e = rd_ptr[FIFO_PTR-1];
-
- assign d_out = dpram0_b_clk_e ? d_out_0 : d_out_1;
-
-dpram dpram_fifo0(
- .rstn( rstn ),
- .a_clk( clk ),
- .a_clk_e( dpram0_a_clk_e ),
- .a_we( we ),
- .a_oe( 1'b0 ),
- .a_addr( wr_ptr[10:0] ),
- .a_din( d_in ),
- .a_dout( ),
- // port B
- .b_clk( clk ),
- .b_clk_e( dpram0_b_clk_e ),
- .b_we( 1'b0 ),
- .b_oe( 1'b1 ),
- .b_addr( rd_ptr[10:0] ),
- .b_din( 9'h0 ),
- .b_dout( d_out_0 )
-);
-
-dpram dpram_fifo1(
- .rstn( rstn ),
- .a_clk( clk ),
- .a_clk_e( dpram1_a_clk_e ),
- .a_we( we ),
- .a_oe( 1'b0 ),
- .a_addr( wr_ptr[10:0] ),
- .a_din( d_in ),
- .a_dout( ),
- // port B
- .b_clk( clk ),
- .b_clk_e( dpram1_b_clk_e ),
- .b_we( 1'b0 ),
- .b_oe( 1'b1 ),
- .b_addr( rd_ptr[10:0] ),
- .b_din( 9'h0 ),
- .b_dout( d_out_1 )
- );
-
-endmodule
diff --git a/source/sync4_fifo.v b/source/sync4_fifo.v
deleted file mode 100644
index c7c1fb6..0000000
--- a/source/sync4_fifo.v
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
- * sync4_fifo.v
- *
- * Copyright (C) 2018, 2019 Mind Chasers Inc.
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- * function: FIFO / data store between RX and TX for each path
- *
- */
-
-`timescale 1ns /10ps
-
-module sync4_fifo #(parameter FIFO_PTR = 13,
- FIFO_WIDTH = 9,
- FIFO_DEPTH = 8192 )
-(
- input rstn,
- input clk,
-
- // input
- input we,
- input [FIFO_WIDTH-1:0] d_in,
-
- // output
- input re,
- output reg [FIFO_WIDTH-1:0] d_out,
- output empty,
- output almost_full,
-
- // fifo_control
- input reset_ptrs,
-
- // debug
- output active
-
-);
-
-`include "ethernet_params.v"
-
-reg [FIFO_PTR-1:0] wr_ptr;
-reg [FIFO_PTR-1:0] rd_ptr;
-reg [FIFO_PTR-1:0] wr_bytes_available; // use for size calculation below
-
-wire [FIFO_WIDTH-1:0] d_out_0, d_out_1, d_out_2, d_out_3;
-
-wire dpram0_a_clk_e, dpram1_a_clk_e, dpram2_a_clk_e, dpram3_a_clk_e;
-wire dpram0_b_clk_e, dpram1_b_clk_e, dpram2_b_clk_e, dpram3_b_clk_e;
-reg dpram0_b_clk_e_m1, dpram1_b_clk_e_m1, dpram2_b_clk_e_m1, dpram3_b_clk_e_m1;
-
-
-always @(posedge clk, negedge rstn)
- if( !rstn ) begin
- dpram0_b_clk_e_m1 <= 1'b0;
- dpram1_b_clk_e_m1 <= 1'b0;
- dpram2_b_clk_e_m1 <= 1'b0;
- dpram3_b_clk_e_m1 <= 1'b0;
- end
- else begin
- dpram0_b_clk_e_m1 <= dpram0_b_clk_e;
- dpram1_b_clk_e_m1 <= dpram1_b_clk_e;
- dpram2_b_clk_e_m1 <= dpram2_b_clk_e;
- dpram3_b_clk_e_m1 <= dpram3_b_clk_e;
- end
-
-always @(posedge clk, negedge rstn)
- if( !rstn )
- wr_ptr <= 'd0;
- else if ( reset_ptrs )
- wr_ptr <= 'd0;
- else if ( we )
- wr_ptr <= wr_ptr + 1;
-
-/*
- * rd_ptr
- * use empty flag to make sure rd_ptr doesn't advance when empty ( error condition )
- */
-always @(posedge clk, negedge rstn)
- if( !rstn )
- rd_ptr <= 'd0;
- else if ( reset_ptrs )
- rd_ptr <= 'd0;
- else if ( re && !empty )
- rd_ptr <= rd_ptr + 1;
-
-assign empty = ( rd_ptr == wr_ptr ) ? 1'b1 : 1'b0;
-assign almost_full = wr_bytes_available < MTU ? 1'b1 : 1'b0;
-
-always @(posedge clk, negedge rstn)
- if( !rstn )
- wr_bytes_available <= FIFO_DEPTH-1;
- else if ( wr_ptr >= rd_ptr )
- wr_bytes_available <= FIFO_DEPTH-1 - (wr_ptr - rd_ptr);
- else
- wr_bytes_available <= rd_ptr - wr_ptr;
-
-assign dpram0_a_clk_e = wr_ptr[FIFO_PTR-1:FIFO_PTR-2] == 2'b00 ? 1'b1 : 1'b0;
-assign dpram1_a_clk_e = wr_ptr[FIFO_PTR-1:FIFO_PTR-2] == 2'b01 ? 1'b1 : 1'b0;
-assign dpram2_a_clk_e = wr_ptr[FIFO_PTR-1:FIFO_PTR-2] == 2'b10 ? 1'b1 : 1'b0;
-assign dpram3_a_clk_e = wr_ptr[FIFO_PTR-1:FIFO_PTR-2] == 2'b11 ? 1'b1 : 1'b0;
-
-assign dpram0_b_clk_e = rd_ptr[FIFO_PTR-1:FIFO_PTR-2] == 2'b00 ? 1'b1 : 1'b0;
-assign dpram1_b_clk_e = rd_ptr[FIFO_PTR-1:FIFO_PTR-2] == 2'b01 ? 1'b1 : 1'b0;
-assign dpram2_b_clk_e = rd_ptr[FIFO_PTR-1:FIFO_PTR-2] == 2'b10 ? 1'b1 : 1'b0;
-assign dpram3_b_clk_e = rd_ptr[FIFO_PTR-1:FIFO_PTR-2] == 2'b11 ? 1'b1 : 1'b0;
-
-// we have to delay the mux one bit for when the DPRAM switches. Otherwise, we read from the wrong DPRAM for one time slot
-always @(*)
- if (dpram0_b_clk_e_m1)
- d_out = d_out_0;
- else if (dpram1_b_clk_e_m1)
- d_out = d_out_1;
- else if (dpram2_b_clk_e_m1)
- d_out = d_out_2;
- else if (dpram3_b_clk_e_m1)
- d_out = d_out_3;
-
-assign active = ~empty;
-
-dpram dpram_fifo0(
- .rstn( rstn ),
- .a_clk( clk ),
- .a_clk_e( dpram0_a_clk_e ),
- .a_we( we ),
- .a_oe( 1'b0 ),
- .a_addr( wr_ptr[10:0] ),
- .a_din( d_in ),
- .a_dout( ),
- // port B
- .b_clk( clk ),
- .b_clk_e( dpram0_b_clk_e ),
- .b_we( 1'b0 ),
- .b_oe( 1'b1 ),
- .b_addr( rd_ptr[10:0] ),
- .b_din( 9'h0 ),
- .b_dout( d_out_0 )
-);
-
-dpram dpram_fifo1(
- .rstn( rstn ),
- .a_clk( clk ),
- .a_clk_e( dpram1_a_clk_e ),
- .a_we( we ),
- .a_oe( 1'b0 ),
- .a_addr( wr_ptr[10:0] ),
- .a_din( d_in ),
- .a_dout( ),
- // port B
- .b_clk( clk ),
- .b_clk_e( dpram1_b_clk_e ),
- .b_we( 1'b0 ),
- .b_oe( 1'b1 ),
- .b_addr( rd_ptr[10:0] ),
- .b_din( 9'h0 ),
- .b_dout( d_out_1 )
- );
-
-dpram dpram_fifo2(
- .rstn( rstn ),
- .a_clk( clk ),
- .a_clk_e( dpram2_a_clk_e ),
- .a_we( we ),
- .a_oe( 1'b0 ),
- .a_addr( wr_ptr[10:0] ),
- .a_din( d_in ),
- .a_dout( ),
- // port B
- .b_clk( clk ),
- .b_clk_e( dpram2_b_clk_e ),
- .b_we( 1'b0 ),
- .b_oe( 1'b1 ),
- .b_addr( rd_ptr[10:0] ),
- .b_din( 9'h0 ),
- .b_dout( d_out_2 )
- );
-
-dpram dpram_fifo3(
- .rstn( rstn ),
- .a_clk( clk ),
- .a_clk_e( dpram3_a_clk_e ),
- .a_we( we ),
- .a_oe( 1'b0 ),
- .a_addr( wr_ptr[10:0] ),
- .a_din( d_in ),
- .a_dout( ),
- // port B
- .b_clk( clk ),
- .b_clk_e( dpram3_b_clk_e ),
- .b_we( 1'b0 ),
- .b_oe( 1'b1 ),
- .b_addr( rd_ptr[10:0] ),
- .b_din( 9'h0 ),
- .b_dout( d_out_3 )
- );
-
-endmodule



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