/*
 *       spi.c
 *
 *       Copyright (C) 2018, 2019 Mind Chasers Inc.
 *
 *   Licensed under the Apache License, Version 2.0 (the "License");
 *   you may not use this file except in compliance with the License.
 *   You may obtain a copy of the License at
 *
 *       http://www.apache.org/licenses/LICENSE-2.0
 *
 *   Unless required by applicable law or agreed to in writing, software
 *   distributed under the License is distributed on an "AS IS" BASIS,
 *   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 *   See the License for the specific language governing permissions and
 *   limitations under the License.
 *
 */


#include "fsl_debug_console.h"
#include "fsl_dspi.h"
#include "stdint.h"
#include "spi.h"

int spi_init(dspi_master_config_t spi_masterConfig) {
    uint32_t srcClock_Hz;
    spi_masterConfig.whichCtar = kDSPI_Ctar0;
    spi_masterConfig.ctarConfig.baudRate = DSPI_TRANSFER_BAUDRATE;
    spi_masterConfig.ctarConfig.bitsPerFrame = 9U;
    spi_masterConfig.ctarConfig.cpol = kDSPI_ClockPolarityActiveHigh;
    spi_masterConfig.ctarConfig.cpha = kDSPI_ClockPhaseFirstEdge;
    spi_masterConfig.ctarConfig.direction = kDSPI_MsbFirst;
    spi_masterConfig.ctarConfig.pcsToSckDelayInNanoSec = 1000000000U / DSPI_TRANSFER_BAUDRATE;
    spi_masterConfig.ctarConfig.lastSckToPcsDelayInNanoSec = 1000000000U / DSPI_TRANSFER_BAUDRATE;
    spi_masterConfig.ctarConfig.betweenTransferDelayInNanoSec = 1000000000U / DSPI_TRANSFER_BAUDRATE;

    spi_masterConfig.whichPcs = kDSPI_Pcs0;
    spi_masterConfig.pcsActiveHighOrLow = kDSPI_PcsActiveHigh;

    spi_masterConfig.enableContinuousSCK = false;
    spi_masterConfig.enableRxFifoOverWrite = false;
    spi_masterConfig.enableModifiedTimingFormat = false;
    spi_masterConfig.samplePoint = kDSPI_SckToSin0Clock;

    srcClock_Hz = DSPI_MASTER_CLK_FREQ;
    DSPI_MasterInit(DSPI_MASTER_BASEADDR, &spi_masterConfig, srcClock_Hz);

	return(0);
}

int write_spi(uint8_t dev_ad, uint8_t addr, uint8_t* pBuff, uint8_t sz) {
	uint16_t transfer_cnt = (sz+2)*2;
    uint16_t masterRxData[256] = {0U};
    uint16_t masterTxData[256] = {0U};
    dspi_transfer_t masterXfer;

    // SPI_RWN = 0 for write, so no operation is required
    masterTxData[0] = (dev_ad<<1);
    masterTxData[1] = addr;			// addr

    for (int i = 2; i < sz+2; i++ ) {
    	masterTxData[i] = *pBuff++;
    }

	/* Start master transfer, send data to slave */
	masterXfer.txData = (uint8_t*) masterTxData;
	masterXfer.rxData = (uint8_t*) masterRxData;
	masterXfer.dataSize = transfer_cnt;
	masterXfer.configFlags = kDSPI_MasterCtar0 | kDSPI_MasterPcs0 | kDSPI_MasterPcsContinuous;
	DSPI_MasterTransferBlocking(DSPI_MASTER_BASEADDR, &masterXfer);

	return(0);

}

int read_spi(uint8_t dev_ad, uint8_t addr, uint8_t* pBuff, uint8_t sz) {
	uint16_t transfer_cnt = (sz+2)*2;
    uint16_t masterRxData[256] = {0U};
    uint16_t masterTxData[256] = {0U};
    dspi_transfer_t masterXfer;

    masterTxData[0] = (dev_ad<<1) | SPI_READ;
    masterTxData[1] = addr;

	/* Start master transfer, send data to slave */
	masterXfer.txData = (uint8_t*) masterTxData;
	masterXfer.rxData = (uint8_t*) masterRxData;
	masterXfer.dataSize = transfer_cnt;
	masterXfer.configFlags = kDSPI_MasterCtar0 | kDSPI_MasterPcs0 | kDSPI_MasterPcsContinuous;
	DSPI_MasterTransferBlocking(DSPI_MASTER_BASEADDR, &masterXfer);

	return(0);

}


int test_spi(uint8_t rwn, uint8_t dev_ad) {

	volatile static int i = 0;
	uint16_t transfer_cnt = 10;
    uint16_t masterRxData[256] = {0U};
    uint16_t masterTxData[256] = {0U};
    dspi_transfer_t masterXfer;

    if (!rwn) {
		// write TX buffer
		/* Set up the transfer data */
		masterTxData[0] = (dev_ad<<1) | rwn;	// dev_ad|RWN
		masterTxData[1] = 0x01;			// addr
		masterTxData[2] = 0x77;			// data
		masterTxData[3] = 0x33;			// data
		masterTxData[4] = 0xaa;			// data
    }
    else {
    	// read TX buffer
    	masterTxData[0] = (dev_ad<<1) | rwn;	// dev_ad|RWN
    	masterTxData[1] = 0x01;			// addr
    	masterTxData[2] = 0x00;			// data
    	masterTxData[3] = 0x00;			// data
    	masterTxData[4] = 0x00;			// data
    }

	/* Print out transmit buffer */
	PRINTF("\r\n Master transmit:\r\n");
	for (i = 0U; i < transfer_cnt; i++)
	{
		/* Print 16 numbers in a line */
		if ((i & 0x0FU) == 0U)
		{
			PRINTF("\r\n");
		}
		PRINTF(" %02X", masterTxData[i]);
	}
	PRINTF("\r\n");

	/* Start master transfer, send data to slave */
	masterXfer.txData = (uint8_t*) masterTxData;
	masterXfer.rxData = (uint8_t*) masterRxData;
	masterXfer.dataSize = transfer_cnt;
	masterXfer.configFlags = kDSPI_MasterCtar0 | kDSPI_MasterPcs0 | kDSPI_MasterPcsContinuous;
	DSPI_MasterTransferBlocking(DSPI_MASTER_BASEADDR, &masterXfer);

	/* Print out receive buffer */
	PRINTF("\r\n Master transmit:\r\n");
	for (i = 0U; i < transfer_cnt; i++)
	{
		/* Print 16 numbers in a line */
		if ((i & 0x0FU) == 0U)
		{
			PRINTF("\r\n");
		}
		PRINTF(" %02X", masterRxData[i]);
	}
	PRINTF("\r\n");

    return(0);

}