From ed46e1a38ae2de97b55c1843bad8b813bd4936e3 Mon Sep 17 00:00:00 2001 From: mindchasers Date: Sun, 7 Jul 2019 17:58:07 -0400 Subject: initial commit of private island ARM test suite --- board/pin_mux.c | 235 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 235 insertions(+) create mode 100755 board/pin_mux.c (limited to 'board/pin_mux.c') diff --git a/board/pin_mux.c b/board/pin_mux.c new file mode 100755 index 0000000..b3862ea --- /dev/null +++ b/board/pin_mux.c @@ -0,0 +1,235 @@ +/*********************************************************************************************************************** + * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file + * will be overwritten if the respective MCUXpresso Config Tools is used to update this file. + **********************************************************************************************************************/ + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +!!GlobalInfo +product: Pins v4.1 +processor: MK02FN128xxx10 +package_id: MK02FN128VFM10 +mcu_data: ksdk2_0 +processor_version: 4.0.0 +pin_labels: +- {pin_num: '6', pin_signal: ADC0_SE7a/ADC0_DM2/PTE19/SPI0_SIN/UART1_RTS_b/I2C0_SCL, label: I2C_SCL, identifier: I2C_SCL} +- {pin_num: '16', pin_signal: PTA4/LLWU_P3/FTM0_CH1/NMI_b, label: PMIC_INTN, identifier: PMIC_INTN} +- {pin_num: '11', pin_signal: ADC0_SE18/PTE25/I2C0_SDA/EWM_IN, label: PB6, identifier: PB6} +- {pin_num: '29', pin_signal: PTD4/LLWU_P14/SPI0_PCS1/UART0_RTS_b/FTM0_CH4/EWM_IN, label: FPGA_RESETN, identifier: FPGA_RESETN} +- {pin_num: '17', pin_signal: EXTAL0/PTA18/FTM0_FLT2/FTM_CLKIN0, label: PMIC_DCDC_E, identifier: PMIC_DCDC_E} +- {pin_num: '22', pin_signal: ADC0_SE15/PTC1/LLWU_P6/SPI0_PCS3/UART1_RTS_b/FTM0_CH0, label: FPGA_GPIO, identifier: FPGA_GPIO} +- {pin_num: '19', pin_signal: RESET_b, label: UC_RESETN, identifier: UC_RESETN} +- {pin_num: '20', pin_signal: ADC0_SE8/PTB0/LLWU_P5/I2C0_SCL/FTM1_CH0/FTM1_QD_PHA, label: FCFG_PGMN, identifier: FCFG_PGMN} +- {pin_num: '21', pin_signal: ADC0_SE9/PTB1/I2C0_SDA/FTM1_CH1/FTM1_QD_PHB, label: FCFG_DONE, identifier: FCFG_DONE} +- {pin_num: '25', pin_signal: PTC4/LLWU_P8/SPI0_PCS0/UART1_TX/FTM0_CH3/CMP1_OUT, label: SPI0_PCS, identifier: SPI_PCS} +- {pin_num: '26', pin_signal: PTC5/LLWU_P9/SPI0_SCK/LPTMR0_ALT2/CMP0_OUT/FTM0_CH2, label: SPI_SCLK, identifier: SPI_SCLK} +- {pin_num: '27', pin_signal: CMP0_IN0/PTC6/LLWU_P10/SPI0_SOUT/PDB0_EXTRG, label: SPI_MOSI, identifier: SPI_MOSI} +- {pin_num: '28', pin_signal: CMP0_IN1/PTC7/SPI0_SIN, label: SPI_MISO, identifier: SPI_MISO} +- {pin_num: '30', pin_signal: ADC0_SE6b/PTD5/SPI0_PCS2/UART0_CTS_b/FTM0_CH5/EWM_OUT_b, label: FPGA_INT, identifier: FPGA_INT} +- {pin_num: '31', pin_signal: ADC0_SE7b/PTD6/LLWU_P15/SPI0_PCS3/UART0_RX/FTM0_CH0/FTM0_FLT0, label: UART_RX, identifier: UART_RX} +- {pin_num: '32', pin_signal: PTD7/UART0_TX/FTM0_CH1/FTM0_FLT1, label: UART_TX, identifier: UART_TX} +- {pin_num: '5', pin_signal: ADC0_SE6a/ADC0_DP2/PTE18/SPI0_SOUT/UART1_CTS_b/I2C0_SDA, label: I2C_SDA, identifier: I2C_SDA} +- {pin_num: '10', pin_signal: ADC0_SE17/PTE24/I2C0_SCL/EWM_OUT_b, label: PB7, identifier: PB7} +- {pin_num: '18', pin_signal: XTAL0/PTA19/FTM1_FLT0/FTM_CLKIN1/LPTMR0_ALT1, label: PMIC_LDO_E, identifier: PMIC_LDO_E} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +#include "fsl_common.h" +#include "fsl_port.h" +#include "fsl_gpio.h" +#include "pin_mux.h" + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitBootPins + * Description : Calls initialization functions. + * + * END ****************************************************************************************************************/ +void BOARD_InitBootPins(void) +{ + BOARD_InitPins(); +} + +/* clang-format off */ +/* + * TEXT BELOW IS USED AS SETTING FOR TOOLS ************************************* +BOARD_InitPins: +- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'} +- pin_list: + - {pin_num: '15', peripheral: JTAG, signal: JTAG_TMS_SWD_DIO, pin_signal: PTA3/UART0_RTS_b/FTM0_CH0/JTAG_TMS/SWD_DIO} + - {pin_num: '12', peripheral: JTAG, signal: JTAG_TCLK_SWD_CLK, pin_signal: PTA0/UART0_CTS_b/FTM0_CH5/JTAG_TCLK/SWD_CLK} + - {pin_num: '14', peripheral: JTAG, signal: TDO, pin_signal: PTA2/UART0_TX/JTAG_TDO/TRACE_SWO} + - {pin_num: '13', peripheral: JTAG, signal: TDI, pin_signal: PTA1/UART0_RX/JTAG_TDI} + - {pin_num: '11', peripheral: GPIOE, signal: 'GPIO, 25', pin_signal: ADC0_SE18/PTE25/I2C0_SDA/EWM_IN, direction: OUTPUT, gpio_init_state: 'false'} + - {pin_num: '32', peripheral: UART0, signal: TX, pin_signal: PTD7/UART0_TX/FTM0_CH1/FTM0_FLT1} + - {pin_num: '31', peripheral: UART0, signal: RX, pin_signal: ADC0_SE7b/PTD6/LLWU_P15/SPI0_PCS3/UART0_RX/FTM0_CH0/FTM0_FLT0} + - {pin_num: '1', peripheral: SUPPLY, signal: 'VDD, 0', pin_signal: VDD1} + - {pin_num: '2', peripheral: SUPPLY, signal: 'VSS, 0', pin_signal: VSS2} + - {pin_num: '3', peripheral: ADC0, signal: 'DP, 1', pin_signal: ADC0_SE4a/ADC0_DP1/PTE16/SPI0_PCS0/UART1_TX/FTM_CLKIN0/FTM0_FLT3} + - {pin_num: '4', peripheral: ADC0, signal: 'DM, 1', pin_signal: ADC0_SE5a/ADC0_DM1/PTE17/SPI0_SCK/UART1_RX/FTM_CLKIN1/LPTMR0_ALT3} + - {pin_num: '7', peripheral: SUPPLY, signal: 'VDDA, 1', pin_signal: VDDA/VREFH} + - {pin_num: '8', peripheral: SUPPLY, signal: 'pwr_vssa, 1', pin_signal: VSSA/VREFL} + - {pin_num: '9', peripheral: DAC0, signal: OUT, pin_signal: DAC0_OUT/CMP1_IN3/ADC0_SE23} + - {pin_num: '16', peripheral: SystemControl, signal: NMI, pin_signal: PTA4/LLWU_P3/FTM0_CH1/NMI_b} + - {pin_num: '17', peripheral: GPIOA, signal: 'GPIO, 18', pin_signal: EXTAL0/PTA18/FTM0_FLT2/FTM_CLKIN0} + - {pin_num: '19', peripheral: RCM, signal: RESET, pin_signal: RESET_b} + - {pin_num: '20', peripheral: GPIOB, signal: 'GPIO, 0', pin_signal: ADC0_SE8/PTB0/LLWU_P5/I2C0_SCL/FTM1_CH0/FTM1_QD_PHA} + - {pin_num: '21', peripheral: GPIOB, signal: 'GPIO, 1', pin_signal: ADC0_SE9/PTB1/I2C0_SDA/FTM1_CH1/FTM1_QD_PHB} + - {pin_num: '25', peripheral: SPI0, signal: PCS0_SS, pin_signal: PTC4/LLWU_P8/SPI0_PCS0/UART1_TX/FTM0_CH3/CMP1_OUT, direction: OUTPUT} + - {pin_num: '29', peripheral: GPIOD, signal: 'GPIO, 4', pin_signal: PTD4/LLWU_P14/SPI0_PCS1/UART0_RTS_b/FTM0_CH4/EWM_IN, direction: OUTPUT} + - {pin_num: '30', peripheral: GPIOD, signal: 'GPIO, 5', pin_signal: ADC0_SE6b/PTD5/SPI0_PCS2/UART0_CTS_b/FTM0_CH5/EWM_OUT_b, direction: INPUT, gpio_interrupt: kPORT_InterruptLogicOne} + - {pin_num: '26', peripheral: SPI0, signal: SCK, pin_signal: PTC5/LLWU_P9/SPI0_SCK/LPTMR0_ALT2/CMP0_OUT/FTM0_CH2} + - {pin_num: '27', peripheral: SPI0, signal: SOUT, pin_signal: CMP0_IN0/PTC6/LLWU_P10/SPI0_SOUT/PDB0_EXTRG} + - {pin_num: '28', peripheral: SPI0, signal: SIN, pin_signal: CMP0_IN1/PTC7/SPI0_SIN} + - {pin_num: '6', peripheral: I2C0, signal: SCL, pin_signal: ADC0_SE7a/ADC0_DM2/PTE19/SPI0_SIN/UART1_RTS_b/I2C0_SCL} + - {pin_num: '5', peripheral: I2C0, signal: SDA, pin_signal: ADC0_SE6a/ADC0_DP2/PTE18/SPI0_SOUT/UART1_CTS_b/I2C0_SDA, identifier: '', open_drain: enable} + - {pin_num: '10', peripheral: GPIOE, signal: 'GPIO, 24', pin_signal: ADC0_SE17/PTE24/I2C0_SCL/EWM_OUT_b} + - {pin_num: '23', peripheral: CMP1, signal: 'IN, 0', pin_signal: ADC0_SE4b/CMP1_IN0/PTC2/SPI0_PCS2/UART1_CTS_b/FTM0_CH1} + - {pin_num: '24', peripheral: CMP1, signal: 'IN, 1', pin_signal: CMP1_IN1/PTC3/LLWU_P7/SPI0_PCS1/UART1_RX/FTM0_CH2/CLKOUT} + - {pin_num: '18', peripheral: GPIOA, signal: 'GPIO, 19', pin_signal: XTAL0/PTA19/FTM1_FLT0/FTM_CLKIN1/LPTMR0_ALT1} + - {pin_num: '22', peripheral: GPIOC, signal: 'GPIO, 1', pin_signal: ADC0_SE15/PTC1/LLWU_P6/SPI0_PCS3/UART1_RTS_b/FTM0_CH0} + * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS *********** + */ +/* clang-format on */ + +/* FUNCTION ************************************************************************************************************ + * + * Function Name : BOARD_InitPins + * Description : Configures pin routing and optionally pin electrical features. + * + * END ****************************************************************************************************************/ +void BOARD_InitPins(void) +{ + /* Port A Clock Gate Control: Clock enabled */ + CLOCK_EnableClock(kCLOCK_PortA); + /* Port B Clock Gate Control: Clock enabled */ + CLOCK_EnableClock(kCLOCK_PortB); + /* Port C Clock Gate Control: Clock enabled */ + CLOCK_EnableClock(kCLOCK_PortC); + /* Port D Clock Gate Control: Clock enabled */ + CLOCK_EnableClock(kCLOCK_PortD); + /* Port E Clock Gate Control: Clock enabled */ + CLOCK_EnableClock(kCLOCK_PortE); + + gpio_pin_config_t FPGA_RESETN_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PTD4 (pin 29) */ + GPIO_PinInit(BOARD_INITPINS_FPGA_RESETN_GPIO, BOARD_INITPINS_FPGA_RESETN_PIN, &FPGA_RESETN_config); + + gpio_pin_config_t FPGA_INT_config = { + .pinDirection = kGPIO_DigitalInput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PTD5 (pin 30) */ + GPIO_PinInit(BOARD_INITPINS_FPGA_INT_GPIO, BOARD_INITPINS_FPGA_INT_PIN, &FPGA_INT_config); + + gpio_pin_config_t PB6_config = { + .pinDirection = kGPIO_DigitalOutput, + .outputLogic = 0U + }; + /* Initialize GPIO functionality on pin PTE25 (pin 11) */ + GPIO_PinInit(BOARD_INITPINS_PB6_GPIO, BOARD_INITPINS_PB6_PIN, &PB6_config); + + /* PORTA0 (pin 12) is configured as JTAG_TCLK */ + PORT_SetPinMux(PORTA, 0U, kPORT_MuxAlt7); + + /* PORTA1 (pin 13) is configured as JTAG_TDI */ + PORT_SetPinMux(PORTA, 1U, kPORT_MuxAlt7); + + /* PORTA18 (pin 17) is configured as PTA18 */ + PORT_SetPinMux(BOARD_INITPINS_PMIC_DCDC_E_PORT, BOARD_INITPINS_PMIC_DCDC_E_PIN, kPORT_MuxAsGpio); + + /* PORTA19 (pin 18) is configured as PTA19 */ + PORT_SetPinMux(BOARD_INITPINS_PMIC_LDO_E_PORT, BOARD_INITPINS_PMIC_LDO_E_PIN, kPORT_MuxAsGpio); + + /* PORTA2 (pin 14) is configured as JTAG_TDO */ + PORT_SetPinMux(PORTA, 2U, kPORT_MuxAlt7); + + /* PORTA3 (pin 15) is configured as JTAG_TMS */ + PORT_SetPinMux(PORTA, 3U, kPORT_MuxAlt7); + + /* PORTA4 (pin 16) is configured as NMI_b */ + PORT_SetPinMux(BOARD_INITPINS_PMIC_INTN_PORT, BOARD_INITPINS_PMIC_INTN_PIN, kPORT_MuxAlt7); + + /* PORTB0 (pin 20) is configured as PTB0 */ + PORT_SetPinMux(BOARD_INITPINS_FCFG_PGMN_PORT, BOARD_INITPINS_FCFG_PGMN_PIN, kPORT_MuxAsGpio); + + /* PORTB1 (pin 21) is configured as PTB1 */ + PORT_SetPinMux(BOARD_INITPINS_FCFG_DONE_PORT, BOARD_INITPINS_FCFG_DONE_PIN, kPORT_MuxAsGpio); + + /* PORTC1 (pin 22) is configured as PTC1 */ + PORT_SetPinMux(BOARD_INITPINS_FPGA_GPIO_PORT, BOARD_INITPINS_FPGA_GPIO_PIN, kPORT_MuxAsGpio); + + /* PORTC2 (pin 23) is configured as CMP1_IN0 */ + PORT_SetPinMux(PORTC, 2U, kPORT_PinDisabledOrAnalog); + + /* PORTC3 (pin 24) is configured as CMP1_IN1 */ + PORT_SetPinMux(PORTC, 3U, kPORT_PinDisabledOrAnalog); + + /* PORTC4 (pin 25) is configured as SPI0_PCS0 */ + PORT_SetPinMux(BOARD_INITPINS_SPI_PCS_PORT, BOARD_INITPINS_SPI_PCS_PIN, kPORT_MuxAlt2); + + /* PORTC5 (pin 26) is configured as SPI0_SCK */ + PORT_SetPinMux(BOARD_INITPINS_SPI_SCLK_PORT, BOARD_INITPINS_SPI_SCLK_PIN, kPORT_MuxAlt2); + + /* PORTC6 (pin 27) is configured as SPI0_SOUT */ + PORT_SetPinMux(BOARD_INITPINS_SPI_MOSI_PORT, BOARD_INITPINS_SPI_MOSI_PIN, kPORT_MuxAlt2); + + /* PORTC7 (pin 28) is configured as SPI0_SIN */ + PORT_SetPinMux(BOARD_INITPINS_SPI_MISO_PORT, BOARD_INITPINS_SPI_MISO_PIN, kPORT_MuxAlt2); + + /* PORTD4 (pin 29) is configured as PTD4 */ + PORT_SetPinMux(BOARD_INITPINS_FPGA_RESETN_PORT, BOARD_INITPINS_FPGA_RESETN_PIN, kPORT_MuxAsGpio); + + /* PORTD5 (pin 30) is configured as PTD5 */ + PORT_SetPinMux(BOARD_INITPINS_FPGA_INT_PORT, BOARD_INITPINS_FPGA_INT_PIN, kPORT_MuxAsGpio); + + /* Interrupt configuration on PORTD5 (pin 30): Interrupt when logic one */ + PORT_SetPinInterruptConfig(BOARD_INITPINS_FPGA_INT_PORT, BOARD_INITPINS_FPGA_INT_PIN, kPORT_InterruptLogicOne); + + /* PORTD6 (pin 31) is configured as UART0_RX */ + PORT_SetPinMux(BOARD_INITPINS_UART_RX_PORT, BOARD_INITPINS_UART_RX_PIN, kPORT_MuxAlt3); + + /* PORTD7 (pin 32) is configured as UART0_TX */ + PORT_SetPinMux(BOARD_INITPINS_UART_TX_PORT, BOARD_INITPINS_UART_TX_PIN, kPORT_MuxAlt3); + + /* PORTE16 (pin 3) is configured as ADC0_DP1 */ + PORT_SetPinMux(PORTE, 16U, kPORT_PinDisabledOrAnalog); + + /* PORTE17 (pin 4) is configured as ADC0_DM1 */ + PORT_SetPinMux(PORTE, 17U, kPORT_PinDisabledOrAnalog); + + /* PORTE18 (pin 5) is configured as I2C0_SDA */ + PORT_SetPinMux(PORTE, 18U, kPORT_MuxAlt4); + + PORTE->PCR[18] = ((PORTE->PCR[18] & + /* Mask bits to zero which are setting */ + (~(PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK))) + + /* Open Drain Enable: Open drain output is enabled on the corresponding pin, if the pin is + * configured as a digital output. */ + | PORT_PCR_ODE(kPORT_OpenDrainEnable)); + + /* PORTE19 (pin 6) is configured as I2C0_SCL */ + PORT_SetPinMux(BOARD_INITPINS_I2C_SCL_PORT, BOARD_INITPINS_I2C_SCL_PIN, kPORT_MuxAlt4); + + /* PORTE24 (pin 10) is configured as PTE24 */ + PORT_SetPinMux(BOARD_INITPINS_PB7_PORT, BOARD_INITPINS_PB7_PIN, kPORT_MuxAsGpio); + + /* PORTE25 (pin 11) is configured as PTE25 */ + PORT_SetPinMux(BOARD_INITPINS_PB6_PORT, BOARD_INITPINS_PB6_PIN, kPORT_MuxAsGpio); + + SIM->SOPT5 = ((SIM->SOPT5 & + /* Mask bits to zero which are setting */ + (~(SIM_SOPT5_UART0TXSRC_MASK))) + + /* UART 0 transmit data source select: UART0_TX pin. */ + | SIM_SOPT5_UART0TXSRC(SOPT5_UART0TXSRC_UART_TX)); +} +/*********************************************************************************************************************** + * EOF + **********************************************************************************************************************/ -- cgit v1.2.3-8-gadcc