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-rw-r--r--board/board.c49
-rw-r--r--board/board.h76
-rw-r--r--board/clock_config.c165
-rw-r--r--board/clock_config.h69
-rw-r--r--board/peripherals.c50
-rw-r--r--board/peripherals.h56
-rwxr-xr-xboard/pin_mux.c235
-rwxr-xr-xboard/pin_mux.h162
8 files changed, 862 insertions, 0 deletions
diff --git a/board/board.c b/board/board.c
new file mode 100644
index 0000000..2689053
--- /dev/null
+++ b/board/board.c
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2016-2018 NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of NXP Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file board.c
+ * @brief Board initialization file.
+ */
+
+/* This is a template for board specific configuration created by MCUXpresso IDE Project Wizard.*/
+
+#include <stdint.h>
+#include "board.h"
+#include "fsl_debug_console.h"
+
+/**
+ * @brief Set up and initialize all required blocks and functions related to the board hardware.
+ */
+void BOARD_InitDebugConsole(void) {
+ uint32_t uartClkSrcFreq = BOARD_DEBUG_UART_CLK_FREQ;
+
+ DbgConsole_Init(BOARD_DEBUG_UART_BASEADDR, BOARD_DEBUG_UART_BAUDRATE, BOARD_DEBUG_UART_TYPE, uartClkSrcFreq);
+}
diff --git a/board/board.h b/board/board.h
new file mode 100644
index 0000000..4d4811b
--- /dev/null
+++ b/board/board.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright 2016-2018 NXP Semiconductor, Inc.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of NXP Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file board.h
+ * @brief Board initialization header file.
+ */
+
+/* This is a template for board specific configuration created by MCUXpresso IDE Project Wizard.*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+#include "fsl_common.h"
+
+/**
+ * @brief The board name
+ */
+#define BOARD_NAME "darsena"
+
+/*! @brief The UART to use for debug messages. */
+#define BOARD_USE_UART
+#define BOARD_DEBUG_UART_TYPE DEBUG_CONSOLE_DEVICE_TYPE_UART
+#define BOARD_DEBUG_UART_BASEADDR (uint32_t) UART0
+#define BOARD_DEBUG_UART_CLKSRC SYS_CLK
+#define BOARD_DEBUG_UART_CLK_FREQ CLOCK_GetCoreSysClkFreq()
+#define BOARD_UART_IRQ UART0_RX_TX_IRQn
+#define BOARD_UART_IRQ_HANDLER UART0_RX_TX_IRQHandler
+
+#ifndef BOARD_DEBUG_UART_BAUDRATE
+#define BOARD_DEBUG_UART_BAUDRATE 115200
+#endif /* BOARD_DEBUG_UART_BAUDRATE */
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @brief Initialize board specific settings.
+ */
+void BOARD_InitDebugConsole(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _BOARD_H_ */
+
+
diff --git a/board/clock_config.c b/board/clock_config.c
new file mode 100644
index 0000000..0f332c4
--- /dev/null
+++ b/board/clock_config.c
@@ -0,0 +1,165 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+/*
+ * How to setup clock using clock driver functions:
+ *
+ * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
+ * and flash clock are in allowed range during clock mode switch.
+ *
+ * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
+ *
+ * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
+ * internal reference clock(MCGIRCLK). Follow the steps to setup:
+ *
+ * 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
+ *
+ * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
+ * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
+ * explicitly to setup MCGIRCLK.
+ *
+ * 3). Don't need to configure FLL explicitly, because if target mode is FLL
+ * mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
+ * if the target mode is not FLL mode, the FLL is disabled.
+ *
+ * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
+ * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
+ * be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
+ *
+ * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
+ */
+
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Clocks v4.1
+processor: MK02FN128xxx10
+package_id: MK02FN128VFM10
+mcu_data: ksdk2_0
+processor_version: 4.0.0
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+#include "clock_config.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+#define MCG_IRCLK_DISABLE 0U /*!< MCGIRCLK disabled */
+#define OSC_CAP0P 0U /*!< Oscillator 0pF capacitor load */
+#define OSC_ER_CLK_DISABLE 0U /*!< Disable external reference clock */
+#define SIM_OSC32KSEL_OSC32KCLK_CLK 0U /*!< OSC32KSEL select: OSC32KCLK clock */
+#define SIM_PLLFLLSEL_MCGFLLCLK_CLK 0U /*!< PLLFLL select: MCGFLLCLK clock */
+
+/*******************************************************************************
+ * Variables
+ ******************************************************************************/
+/* System clock frequency. */
+extern uint32_t SystemCoreClock;
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+/*FUNCTION**********************************************************************
+ *
+ * Function Name : CLOCK_CONFIG_FllStableDelay
+ * Description : This function is used to delay for FLL stable.
+ *
+ *END**************************************************************************/
+static void CLOCK_CONFIG_FllStableDelay(void)
+{
+ uint32_t i = 30000U;
+ while (i--)
+ {
+ __NOP();
+ }
+}
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+void BOARD_InitBootClocks(void)
+{
+ BOARD_BootClockRUN();
+}
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/* clang-format off */
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockRUN
+called_from_default_init: true
+outputs:
+- {id: Bus_clock.outFreq, value: 41.94304 MHz}
+- {id: Core_clock.outFreq, value: 41.94304 MHz}
+- {id: Flash_clock.outFreq, value: 20.97152 MHz}
+- {id: LPO_clock.outFreq, value: 1 kHz}
+- {id: MCGFFCLK.outFreq, value: 32.768 kHz}
+- {id: PLLFLLCLK.outFreq, value: 41.94304 MHz}
+- {id: System_clock.outFreq, value: 41.94304 MHz}
+settings:
+- {id: MCG.FLL_mul.scale, value: '1280', locked: true}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+/* clang-format on */
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+const mcg_config_t mcgConfig_BOARD_BootClockRUN =
+ {
+ .mcgMode = kMCG_ModeFEI, /* FEI - FLL Engaged Internal */
+ .irclkEnableMode = MCG_IRCLK_DISABLE, /* MCGIRCLK disabled */
+ .ircs = kMCG_IrcSlow, /* Slow internal reference clock selected */
+ .fcrdiv = 0x1U, /* Fast IRC divider: divided by 2 */
+ .frdiv = 0x0U, /* FLL reference clock divider: divided by 1 */
+ .drs = kMCG_DrsMid, /* Mid frequency range */
+ .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25% */
+ .oscsel = kMCG_OscselOsc, /* Selects System Oscillator (OSCCLK) */
+ };
+const sim_clock_config_t simConfig_BOARD_BootClockRUN =
+ {
+ .pllFllSel = SIM_PLLFLLSEL_MCGFLLCLK_CLK, /* PLLFLL select: MCGFLLCLK clock */
+ .er32kSrc = SIM_OSC32KSEL_OSC32KCLK_CLK, /* OSC32KSEL select: OSC32KCLK clock */
+ .clkdiv1 = 0x10000U, /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /1, OUTDIV4: /2 */
+ };
+const osc_config_t oscConfig_BOARD_BootClockRUN =
+ {
+ .freq = 0U, /* Oscillator frequency: 0Hz */
+ .capLoad = (OSC_CAP0P), /* Oscillator capacity load: 0pF */
+ .workMode = kOSC_ModeExt, /* Use external clock */
+ .oscerConfig =
+ {
+ .enableMode = OSC_ER_CLK_DISABLE, /* Disable external reference clock */
+ .erclkDiv = 0, /* Divider for OSCERCLK: divided by 1 */
+ }
+ };
+
+/*******************************************************************************
+ * Code for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+void BOARD_BootClockRUN(void)
+{
+ /* Set the system clock dividers in SIM to safe value. */
+ CLOCK_SetSimSafeDivs();
+ /* Set MCG to FEI mode. */
+#if FSL_CLOCK_DRIVER_VERSION >= MAKE_VERSION(2, 2, 0)
+ CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockRUN.dmx32,
+ mcgConfig_BOARD_BootClockRUN.drs,
+ CLOCK_CONFIG_FllStableDelay);
+#else
+ CLOCK_BootToFeiMode(mcgConfig_BOARD_BootClockRUN.drs,
+ CLOCK_CONFIG_FllStableDelay);
+#endif
+ /* Configure the Internal Reference clock (MCGIRCLK). */
+ CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockRUN.irclkEnableMode,
+ mcgConfig_BOARD_BootClockRUN.ircs,
+ mcgConfig_BOARD_BootClockRUN.fcrdiv);
+ /* Set the clock configuration in SIM module. */
+ CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
+ /* Set SystemCoreClock variable. */
+ SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
+}
+
diff --git a/board/clock_config.h b/board/clock_config.h
new file mode 100644
index 0000000..eb0f8be
--- /dev/null
+++ b/board/clock_config.h
@@ -0,0 +1,69 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _CLOCK_CONFIG_H_
+#define _CLOCK_CONFIG_H_
+
+#include "fsl_common.h"
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*******************************************************************************
+ ************************ BOARD_InitBootClocks function ************************
+ ******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes default configuration of clocks.
+ *
+ */
+void BOARD_InitBootClocks(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ********************** Configuration BOARD_BootClockRUN ***********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 41943040U /*!< Core clock frequency: 41943040Hz */
+
+/*! @brief MCG set for BOARD_BootClockRUN configuration.
+ */
+extern const mcg_config_t mcgConfig_BOARD_BootClockRUN;
+/*! @brief SIM module set for BOARD_BootClockRUN configuration.
+ */
+extern const sim_clock_config_t simConfig_BOARD_BootClockRUN;
+/*! @brief OSC set for BOARD_BootClockRUN configuration.
+ */
+extern const osc_config_t oscConfig_BOARD_BootClockRUN;
+
+/*******************************************************************************
+ * API for BOARD_BootClockRUN configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockRUN(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
+#endif /* _CLOCK_CONFIG_H_ */
+
diff --git a/board/peripherals.c b/board/peripherals.c
new file mode 100644
index 0000000..c3d271d
--- /dev/null
+++ b/board/peripherals.c
@@ -0,0 +1,50 @@
+/*
+ * Copyright 2017-2018 NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of NXP Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Peripherals v1.0
+* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/**
+ * @file peripherals.c
+ * @brief Peripherals initialization file.
+ */
+
+/* This is a template for board specific configuration created by MCUXpresso IDE Project Wizard.*/
+
+#include "peripherals.h"
+
+/**
+ * @brief Set up and initialize all required blocks and functions related to the peripherals hardware.
+ */
+void BOARD_InitBootPeripherals(void) {
+ /* The user initialization should be placed here */
+}
diff --git a/board/peripherals.h b/board/peripherals.h
new file mode 100644
index 0000000..cfc3b4f
--- /dev/null
+++ b/board/peripherals.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright 2017-2018 NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of NXP Semiconductor, Inc. nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+/**
+ * @file peripherals.h
+ * @brief Peripherals initialization header file.
+ */
+
+/* This is a template for board specific configuration created by MCUXpresso IDE Project Wizard.*/
+
+#ifndef _PERIPHERALS_H_
+#define _PERIPHERALS_H_
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @brief Initialize peripherals specific settings.
+ */
+void BOARD_InitBootPeripherals(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+#endif /* _PERIPHERALS_H_ */
+
+
diff --git a/board/pin_mux.c b/board/pin_mux.c
new file mode 100755
index 0000000..b3862ea
--- /dev/null
+++ b/board/pin_mux.c
@@ -0,0 +1,235 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!GlobalInfo
+product: Pins v4.1
+processor: MK02FN128xxx10
+package_id: MK02FN128VFM10
+mcu_data: ksdk2_0
+processor_version: 4.0.0
+pin_labels:
+- {pin_num: '6', pin_signal: ADC0_SE7a/ADC0_DM2/PTE19/SPI0_SIN/UART1_RTS_b/I2C0_SCL, label: I2C_SCL, identifier: I2C_SCL}
+- {pin_num: '16', pin_signal: PTA4/LLWU_P3/FTM0_CH1/NMI_b, label: PMIC_INTN, identifier: PMIC_INTN}
+- {pin_num: '11', pin_signal: ADC0_SE18/PTE25/I2C0_SDA/EWM_IN, label: PB6, identifier: PB6}
+- {pin_num: '29', pin_signal: PTD4/LLWU_P14/SPI0_PCS1/UART0_RTS_b/FTM0_CH4/EWM_IN, label: FPGA_RESETN, identifier: FPGA_RESETN}
+- {pin_num: '17', pin_signal: EXTAL0/PTA18/FTM0_FLT2/FTM_CLKIN0, label: PMIC_DCDC_E, identifier: PMIC_DCDC_E}
+- {pin_num: '22', pin_signal: ADC0_SE15/PTC1/LLWU_P6/SPI0_PCS3/UART1_RTS_b/FTM0_CH0, label: FPGA_GPIO, identifier: FPGA_GPIO}
+- {pin_num: '19', pin_signal: RESET_b, label: UC_RESETN, identifier: UC_RESETN}
+- {pin_num: '20', pin_signal: ADC0_SE8/PTB0/LLWU_P5/I2C0_SCL/FTM1_CH0/FTM1_QD_PHA, label: FCFG_PGMN, identifier: FCFG_PGMN}
+- {pin_num: '21', pin_signal: ADC0_SE9/PTB1/I2C0_SDA/FTM1_CH1/FTM1_QD_PHB, label: FCFG_DONE, identifier: FCFG_DONE}
+- {pin_num: '25', pin_signal: PTC4/LLWU_P8/SPI0_PCS0/UART1_TX/FTM0_CH3/CMP1_OUT, label: SPI0_PCS, identifier: SPI_PCS}
+- {pin_num: '26', pin_signal: PTC5/LLWU_P9/SPI0_SCK/LPTMR0_ALT2/CMP0_OUT/FTM0_CH2, label: SPI_SCLK, identifier: SPI_SCLK}
+- {pin_num: '27', pin_signal: CMP0_IN0/PTC6/LLWU_P10/SPI0_SOUT/PDB0_EXTRG, label: SPI_MOSI, identifier: SPI_MOSI}
+- {pin_num: '28', pin_signal: CMP0_IN1/PTC7/SPI0_SIN, label: SPI_MISO, identifier: SPI_MISO}
+- {pin_num: '30', pin_signal: ADC0_SE6b/PTD5/SPI0_PCS2/UART0_CTS_b/FTM0_CH5/EWM_OUT_b, label: FPGA_INT, identifier: FPGA_INT}
+- {pin_num: '31', pin_signal: ADC0_SE7b/PTD6/LLWU_P15/SPI0_PCS3/UART0_RX/FTM0_CH0/FTM0_FLT0, label: UART_RX, identifier: UART_RX}
+- {pin_num: '32', pin_signal: PTD7/UART0_TX/FTM0_CH1/FTM0_FLT1, label: UART_TX, identifier: UART_TX}
+- {pin_num: '5', pin_signal: ADC0_SE6a/ADC0_DP2/PTE18/SPI0_SOUT/UART1_CTS_b/I2C0_SDA, label: I2C_SDA, identifier: I2C_SDA}
+- {pin_num: '10', pin_signal: ADC0_SE17/PTE24/I2C0_SCL/EWM_OUT_b, label: PB7, identifier: PB7}
+- {pin_num: '18', pin_signal: XTAL0/PTA19/FTM1_FLT0/FTM_CLKIN1/LPTMR0_ALT1, label: PMIC_LDO_E, identifier: PMIC_LDO_E}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+#include "fsl_common.h"
+#include "fsl_port.h"
+#include "fsl_gpio.h"
+#include "pin_mux.h"
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitBootPins
+ * Description : Calls initialization functions.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitBootPins(void)
+{
+ BOARD_InitPins();
+}
+
+/* clang-format off */
+/*
+ * TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+BOARD_InitPins:
+- options: {callFromInitBoot: 'true', coreID: core0, enableClock: 'true'}
+- pin_list:
+ - {pin_num: '15', peripheral: JTAG, signal: JTAG_TMS_SWD_DIO, pin_signal: PTA3/UART0_RTS_b/FTM0_CH0/JTAG_TMS/SWD_DIO}
+ - {pin_num: '12', peripheral: JTAG, signal: JTAG_TCLK_SWD_CLK, pin_signal: PTA0/UART0_CTS_b/FTM0_CH5/JTAG_TCLK/SWD_CLK}
+ - {pin_num: '14', peripheral: JTAG, signal: TDO, pin_signal: PTA2/UART0_TX/JTAG_TDO/TRACE_SWO}
+ - {pin_num: '13', peripheral: JTAG, signal: TDI, pin_signal: PTA1/UART0_RX/JTAG_TDI}
+ - {pin_num: '11', peripheral: GPIOE, signal: 'GPIO, 25', pin_signal: ADC0_SE18/PTE25/I2C0_SDA/EWM_IN, direction: OUTPUT, gpio_init_state: 'false'}
+ - {pin_num: '32', peripheral: UART0, signal: TX, pin_signal: PTD7/UART0_TX/FTM0_CH1/FTM0_FLT1}
+ - {pin_num: '31', peripheral: UART0, signal: RX, pin_signal: ADC0_SE7b/PTD6/LLWU_P15/SPI0_PCS3/UART0_RX/FTM0_CH0/FTM0_FLT0}
+ - {pin_num: '1', peripheral: SUPPLY, signal: 'VDD, 0', pin_signal: VDD1}
+ - {pin_num: '2', peripheral: SUPPLY, signal: 'VSS, 0', pin_signal: VSS2}
+ - {pin_num: '3', peripheral: ADC0, signal: 'DP, 1', pin_signal: ADC0_SE4a/ADC0_DP1/PTE16/SPI0_PCS0/UART1_TX/FTM_CLKIN0/FTM0_FLT3}
+ - {pin_num: '4', peripheral: ADC0, signal: 'DM, 1', pin_signal: ADC0_SE5a/ADC0_DM1/PTE17/SPI0_SCK/UART1_RX/FTM_CLKIN1/LPTMR0_ALT3}
+ - {pin_num: '7', peripheral: SUPPLY, signal: 'VDDA, 1', pin_signal: VDDA/VREFH}
+ - {pin_num: '8', peripheral: SUPPLY, signal: 'pwr_vssa, 1', pin_signal: VSSA/VREFL}
+ - {pin_num: '9', peripheral: DAC0, signal: OUT, pin_signal: DAC0_OUT/CMP1_IN3/ADC0_SE23}
+ - {pin_num: '16', peripheral: SystemControl, signal: NMI, pin_signal: PTA4/LLWU_P3/FTM0_CH1/NMI_b}
+ - {pin_num: '17', peripheral: GPIOA, signal: 'GPIO, 18', pin_signal: EXTAL0/PTA18/FTM0_FLT2/FTM_CLKIN0}
+ - {pin_num: '19', peripheral: RCM, signal: RESET, pin_signal: RESET_b}
+ - {pin_num: '20', peripheral: GPIOB, signal: 'GPIO, 0', pin_signal: ADC0_SE8/PTB0/LLWU_P5/I2C0_SCL/FTM1_CH0/FTM1_QD_PHA}
+ - {pin_num: '21', peripheral: GPIOB, signal: 'GPIO, 1', pin_signal: ADC0_SE9/PTB1/I2C0_SDA/FTM1_CH1/FTM1_QD_PHB}
+ - {pin_num: '25', peripheral: SPI0, signal: PCS0_SS, pin_signal: PTC4/LLWU_P8/SPI0_PCS0/UART1_TX/FTM0_CH3/CMP1_OUT, direction: OUTPUT}
+ - {pin_num: '29', peripheral: GPIOD, signal: 'GPIO, 4', pin_signal: PTD4/LLWU_P14/SPI0_PCS1/UART0_RTS_b/FTM0_CH4/EWM_IN, direction: OUTPUT}
+ - {pin_num: '30', peripheral: GPIOD, signal: 'GPIO, 5', pin_signal: ADC0_SE6b/PTD5/SPI0_PCS2/UART0_CTS_b/FTM0_CH5/EWM_OUT_b, direction: INPUT, gpio_interrupt: kPORT_InterruptLogicOne}
+ - {pin_num: '26', peripheral: SPI0, signal: SCK, pin_signal: PTC5/LLWU_P9/SPI0_SCK/LPTMR0_ALT2/CMP0_OUT/FTM0_CH2}
+ - {pin_num: '27', peripheral: SPI0, signal: SOUT, pin_signal: CMP0_IN0/PTC6/LLWU_P10/SPI0_SOUT/PDB0_EXTRG}
+ - {pin_num: '28', peripheral: SPI0, signal: SIN, pin_signal: CMP0_IN1/PTC7/SPI0_SIN}
+ - {pin_num: '6', peripheral: I2C0, signal: SCL, pin_signal: ADC0_SE7a/ADC0_DM2/PTE19/SPI0_SIN/UART1_RTS_b/I2C0_SCL}
+ - {pin_num: '5', peripheral: I2C0, signal: SDA, pin_signal: ADC0_SE6a/ADC0_DP2/PTE18/SPI0_SOUT/UART1_CTS_b/I2C0_SDA, identifier: '', open_drain: enable}
+ - {pin_num: '10', peripheral: GPIOE, signal: 'GPIO, 24', pin_signal: ADC0_SE17/PTE24/I2C0_SCL/EWM_OUT_b}
+ - {pin_num: '23', peripheral: CMP1, signal: 'IN, 0', pin_signal: ADC0_SE4b/CMP1_IN0/PTC2/SPI0_PCS2/UART1_CTS_b/FTM0_CH1}
+ - {pin_num: '24', peripheral: CMP1, signal: 'IN, 1', pin_signal: CMP1_IN1/PTC3/LLWU_P7/SPI0_PCS1/UART1_RX/FTM0_CH2/CLKOUT}
+ - {pin_num: '18', peripheral: GPIOA, signal: 'GPIO, 19', pin_signal: XTAL0/PTA19/FTM1_FLT0/FTM_CLKIN1/LPTMR0_ALT1}
+ - {pin_num: '22', peripheral: GPIOC, signal: 'GPIO, 1', pin_signal: ADC0_SE15/PTC1/LLWU_P6/SPI0_PCS3/UART1_RTS_b/FTM0_CH0}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS ***********
+ */
+/* clang-format on */
+
+/* FUNCTION ************************************************************************************************************
+ *
+ * Function Name : BOARD_InitPins
+ * Description : Configures pin routing and optionally pin electrical features.
+ *
+ * END ****************************************************************************************************************/
+void BOARD_InitPins(void)
+{
+ /* Port A Clock Gate Control: Clock enabled */
+ CLOCK_EnableClock(kCLOCK_PortA);
+ /* Port B Clock Gate Control: Clock enabled */
+ CLOCK_EnableClock(kCLOCK_PortB);
+ /* Port C Clock Gate Control: Clock enabled */
+ CLOCK_EnableClock(kCLOCK_PortC);
+ /* Port D Clock Gate Control: Clock enabled */
+ CLOCK_EnableClock(kCLOCK_PortD);
+ /* Port E Clock Gate Control: Clock enabled */
+ CLOCK_EnableClock(kCLOCK_PortE);
+
+ gpio_pin_config_t FPGA_RESETN_config = {
+ .pinDirection = kGPIO_DigitalOutput,
+ .outputLogic = 0U
+ };
+ /* Initialize GPIO functionality on pin PTD4 (pin 29) */
+ GPIO_PinInit(BOARD_INITPINS_FPGA_RESETN_GPIO, BOARD_INITPINS_FPGA_RESETN_PIN, &FPGA_RESETN_config);
+
+ gpio_pin_config_t FPGA_INT_config = {
+ .pinDirection = kGPIO_DigitalInput,
+ .outputLogic = 0U
+ };
+ /* Initialize GPIO functionality on pin PTD5 (pin 30) */
+ GPIO_PinInit(BOARD_INITPINS_FPGA_INT_GPIO, BOARD_INITPINS_FPGA_INT_PIN, &FPGA_INT_config);
+
+ gpio_pin_config_t PB6_config = {
+ .pinDirection = kGPIO_DigitalOutput,
+ .outputLogic = 0U
+ };
+ /* Initialize GPIO functionality on pin PTE25 (pin 11) */
+ GPIO_PinInit(BOARD_INITPINS_PB6_GPIO, BOARD_INITPINS_PB6_PIN, &PB6_config);
+
+ /* PORTA0 (pin 12) is configured as JTAG_TCLK */
+ PORT_SetPinMux(PORTA, 0U, kPORT_MuxAlt7);
+
+ /* PORTA1 (pin 13) is configured as JTAG_TDI */
+ PORT_SetPinMux(PORTA, 1U, kPORT_MuxAlt7);
+
+ /* PORTA18 (pin 17) is configured as PTA18 */
+ PORT_SetPinMux(BOARD_INITPINS_PMIC_DCDC_E_PORT, BOARD_INITPINS_PMIC_DCDC_E_PIN, kPORT_MuxAsGpio);
+
+ /* PORTA19 (pin 18) is configured as PTA19 */
+ PORT_SetPinMux(BOARD_INITPINS_PMIC_LDO_E_PORT, BOARD_INITPINS_PMIC_LDO_E_PIN, kPORT_MuxAsGpio);
+
+ /* PORTA2 (pin 14) is configured as JTAG_TDO */
+ PORT_SetPinMux(PORTA, 2U, kPORT_MuxAlt7);
+
+ /* PORTA3 (pin 15) is configured as JTAG_TMS */
+ PORT_SetPinMux(PORTA, 3U, kPORT_MuxAlt7);
+
+ /* PORTA4 (pin 16) is configured as NMI_b */
+ PORT_SetPinMux(BOARD_INITPINS_PMIC_INTN_PORT, BOARD_INITPINS_PMIC_INTN_PIN, kPORT_MuxAlt7);
+
+ /* PORTB0 (pin 20) is configured as PTB0 */
+ PORT_SetPinMux(BOARD_INITPINS_FCFG_PGMN_PORT, BOARD_INITPINS_FCFG_PGMN_PIN, kPORT_MuxAsGpio);
+
+ /* PORTB1 (pin 21) is configured as PTB1 */
+ PORT_SetPinMux(BOARD_INITPINS_FCFG_DONE_PORT, BOARD_INITPINS_FCFG_DONE_PIN, kPORT_MuxAsGpio);
+
+ /* PORTC1 (pin 22) is configured as PTC1 */
+ PORT_SetPinMux(BOARD_INITPINS_FPGA_GPIO_PORT, BOARD_INITPINS_FPGA_GPIO_PIN, kPORT_MuxAsGpio);
+
+ /* PORTC2 (pin 23) is configured as CMP1_IN0 */
+ PORT_SetPinMux(PORTC, 2U, kPORT_PinDisabledOrAnalog);
+
+ /* PORTC3 (pin 24) is configured as CMP1_IN1 */
+ PORT_SetPinMux(PORTC, 3U, kPORT_PinDisabledOrAnalog);
+
+ /* PORTC4 (pin 25) is configured as SPI0_PCS0 */
+ PORT_SetPinMux(BOARD_INITPINS_SPI_PCS_PORT, BOARD_INITPINS_SPI_PCS_PIN, kPORT_MuxAlt2);
+
+ /* PORTC5 (pin 26) is configured as SPI0_SCK */
+ PORT_SetPinMux(BOARD_INITPINS_SPI_SCLK_PORT, BOARD_INITPINS_SPI_SCLK_PIN, kPORT_MuxAlt2);
+
+ /* PORTC6 (pin 27) is configured as SPI0_SOUT */
+ PORT_SetPinMux(BOARD_INITPINS_SPI_MOSI_PORT, BOARD_INITPINS_SPI_MOSI_PIN, kPORT_MuxAlt2);
+
+ /* PORTC7 (pin 28) is configured as SPI0_SIN */
+ PORT_SetPinMux(BOARD_INITPINS_SPI_MISO_PORT, BOARD_INITPINS_SPI_MISO_PIN, kPORT_MuxAlt2);
+
+ /* PORTD4 (pin 29) is configured as PTD4 */
+ PORT_SetPinMux(BOARD_INITPINS_FPGA_RESETN_PORT, BOARD_INITPINS_FPGA_RESETN_PIN, kPORT_MuxAsGpio);
+
+ /* PORTD5 (pin 30) is configured as PTD5 */
+ PORT_SetPinMux(BOARD_INITPINS_FPGA_INT_PORT, BOARD_INITPINS_FPGA_INT_PIN, kPORT_MuxAsGpio);
+
+ /* Interrupt configuration on PORTD5 (pin 30): Interrupt when logic one */
+ PORT_SetPinInterruptConfig(BOARD_INITPINS_FPGA_INT_PORT, BOARD_INITPINS_FPGA_INT_PIN, kPORT_InterruptLogicOne);
+
+ /* PORTD6 (pin 31) is configured as UART0_RX */
+ PORT_SetPinMux(BOARD_INITPINS_UART_RX_PORT, BOARD_INITPINS_UART_RX_PIN, kPORT_MuxAlt3);
+
+ /* PORTD7 (pin 32) is configured as UART0_TX */
+ PORT_SetPinMux(BOARD_INITPINS_UART_TX_PORT, BOARD_INITPINS_UART_TX_PIN, kPORT_MuxAlt3);
+
+ /* PORTE16 (pin 3) is configured as ADC0_DP1 */
+ PORT_SetPinMux(PORTE, 16U, kPORT_PinDisabledOrAnalog);
+
+ /* PORTE17 (pin 4) is configured as ADC0_DM1 */
+ PORT_SetPinMux(PORTE, 17U, kPORT_PinDisabledOrAnalog);
+
+ /* PORTE18 (pin 5) is configured as I2C0_SDA */
+ PORT_SetPinMux(PORTE, 18U, kPORT_MuxAlt4);
+
+ PORTE->PCR[18] = ((PORTE->PCR[18] &
+ /* Mask bits to zero which are setting */
+ (~(PORT_PCR_ODE_MASK | PORT_PCR_ISF_MASK)))
+
+ /* Open Drain Enable: Open drain output is enabled on the corresponding pin, if the pin is
+ * configured as a digital output. */
+ | PORT_PCR_ODE(kPORT_OpenDrainEnable));
+
+ /* PORTE19 (pin 6) is configured as I2C0_SCL */
+ PORT_SetPinMux(BOARD_INITPINS_I2C_SCL_PORT, BOARD_INITPINS_I2C_SCL_PIN, kPORT_MuxAlt4);
+
+ /* PORTE24 (pin 10) is configured as PTE24 */
+ PORT_SetPinMux(BOARD_INITPINS_PB7_PORT, BOARD_INITPINS_PB7_PIN, kPORT_MuxAsGpio);
+
+ /* PORTE25 (pin 11) is configured as PTE25 */
+ PORT_SetPinMux(BOARD_INITPINS_PB6_PORT, BOARD_INITPINS_PB6_PIN, kPORT_MuxAsGpio);
+
+ SIM->SOPT5 = ((SIM->SOPT5 &
+ /* Mask bits to zero which are setting */
+ (~(SIM_SOPT5_UART0TXSRC_MASK)))
+
+ /* UART 0 transmit data source select: UART0_TX pin. */
+ | SIM_SOPT5_UART0TXSRC(SOPT5_UART0TXSRC_UART_TX));
+}
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/
diff --git a/board/pin_mux.h b/board/pin_mux.h
new file mode 100755
index 0000000..9a4cf79
--- /dev/null
+++ b/board/pin_mux.h
@@ -0,0 +1,162 @@
+/***********************************************************************************************************************
+ * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
+ * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
+ **********************************************************************************************************************/
+
+#ifndef _PIN_MUX_H_
+#define _PIN_MUX_H_
+
+/*!
+ * @addtogroup pin_mux
+ * @{
+ */
+
+/***********************************************************************************************************************
+ * API
+ **********************************************************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif
+
+/*!
+ * @brief Calls initialization functions.
+ *
+ */
+void BOARD_InitBootPins(void);
+
+#define SOPT5_UART0TXSRC_UART_TX 0x00u /*!<@brief UART 0 transmit data source select: UART0_TX pin */
+
+/*! @name PORTE25 (number 11), PB6
+ @{ */
+#define BOARD_INITPINS_PB6_GPIO GPIOE /*!<@brief GPIO device name: GPIOE */
+#define BOARD_INITPINS_PB6_PORT PORTE /*!<@brief PORT device name: PORTE */
+#define BOARD_INITPINS_PB6_PIN 25U /*!<@brief PORTE pin index: 25 */
+ /* @} */
+
+/*! @name PORTD7 (number 32), UART_TX
+ @{ */
+#define BOARD_INITPINS_UART_TX_PORT PORTD /*!<@brief PORT device name: PORTD */
+#define BOARD_INITPINS_UART_TX_PIN 7U /*!<@brief PORTD pin index: 7 */
+ /* @} */
+
+/*! @name PORTD6 (number 31), UART_RX
+ @{ */
+#define BOARD_INITPINS_UART_RX_PORT PORTD /*!<@brief PORT device name: PORTD */
+#define BOARD_INITPINS_UART_RX_PIN 6U /*!<@brief PORTD pin index: 6 */
+ /* @} */
+
+/*! @name PORTA4 (number 16), PMIC_INTN
+ @{ */
+#define BOARD_INITPINS_PMIC_INTN_PORT PORTA /*!<@brief PORT device name: PORTA */
+#define BOARD_INITPINS_PMIC_INTN_PIN 4U /*!<@brief PORTA pin index: 4 */
+ /* @} */
+
+/*! @name PORTA18 (number 17), PMIC_DCDC_E
+ @{ */
+#define BOARD_INITPINS_PMIC_DCDC_E_GPIO GPIOA /*!<@brief GPIO device name: GPIOA */
+#define BOARD_INITPINS_PMIC_DCDC_E_PORT PORTA /*!<@brief PORT device name: PORTA */
+#define BOARD_INITPINS_PMIC_DCDC_E_PIN 18U /*!<@brief PORTA pin index: 18 */
+ /* @} */
+
+/*! @name RESET_b (number 19), UC_RESETN
+ @{ */
+/* @} */
+
+/*! @name PORTB0 (number 20), FCFG_PGMN
+ @{ */
+#define BOARD_INITPINS_FCFG_PGMN_GPIO GPIOB /*!<@brief GPIO device name: GPIOB */
+#define BOARD_INITPINS_FCFG_PGMN_PORT PORTB /*!<@brief PORT device name: PORTB */
+#define BOARD_INITPINS_FCFG_PGMN_PIN 0U /*!<@brief PORTB pin index: 0 */
+ /* @} */
+
+/*! @name PORTB1 (number 21), FCFG_DONE
+ @{ */
+#define BOARD_INITPINS_FCFG_DONE_GPIO GPIOB /*!<@brief GPIO device name: GPIOB */
+#define BOARD_INITPINS_FCFG_DONE_PORT PORTB /*!<@brief PORT device name: PORTB */
+#define BOARD_INITPINS_FCFG_DONE_PIN 1U /*!<@brief PORTB pin index: 1 */
+ /* @} */
+
+/*! @name PORTC4 (number 25), SPI0_PCS
+ @{ */
+#define BOARD_INITPINS_SPI_PCS_PORT PORTC /*!<@brief PORT device name: PORTC */
+#define BOARD_INITPINS_SPI_PCS_PIN 4U /*!<@brief PORTC pin index: 4 */
+ /* @} */
+
+/*! @name PORTD4 (number 29), FPGA_RESETN
+ @{ */
+#define BOARD_INITPINS_FPGA_RESETN_GPIO GPIOD /*!<@brief GPIO device name: GPIOD */
+#define BOARD_INITPINS_FPGA_RESETN_PORT PORTD /*!<@brief PORT device name: PORTD */
+#define BOARD_INITPINS_FPGA_RESETN_PIN 4U /*!<@brief PORTD pin index: 4 */
+ /* @} */
+
+/*! @name PORTD5 (number 30), FPGA_INT
+ @{ */
+#define BOARD_INITPINS_FPGA_INT_GPIO GPIOD /*!<@brief GPIO device name: GPIOD */
+#define BOARD_INITPINS_FPGA_INT_PORT PORTD /*!<@brief PORT device name: PORTD */
+#define BOARD_INITPINS_FPGA_INT_PIN 5U /*!<@brief PORTD pin index: 5 */
+ /* @} */
+
+/*! @name PORTC5 (number 26), SPI_SCLK
+ @{ */
+#define BOARD_INITPINS_SPI_SCLK_PORT PORTC /*!<@brief PORT device name: PORTC */
+#define BOARD_INITPINS_SPI_SCLK_PIN 5U /*!<@brief PORTC pin index: 5 */
+ /* @} */
+
+/*! @name PORTC6 (number 27), SPI_MOSI
+ @{ */
+#define BOARD_INITPINS_SPI_MOSI_PORT PORTC /*!<@brief PORT device name: PORTC */
+#define BOARD_INITPINS_SPI_MOSI_PIN 6U /*!<@brief PORTC pin index: 6 */
+ /* @} */
+
+/*! @name PORTC7 (number 28), SPI_MISO
+ @{ */
+#define BOARD_INITPINS_SPI_MISO_PORT PORTC /*!<@brief PORT device name: PORTC */
+#define BOARD_INITPINS_SPI_MISO_PIN 7U /*!<@brief PORTC pin index: 7 */
+ /* @} */
+
+/*! @name PORTE19 (number 6), I2C_SCL
+ @{ */
+#define BOARD_INITPINS_I2C_SCL_PORT PORTE /*!<@brief PORT device name: PORTE */
+#define BOARD_INITPINS_I2C_SCL_PIN 19U /*!<@brief PORTE pin index: 19 */
+ /* @} */
+
+/*! @name PORTE24 (number 10), PB7
+ @{ */
+#define BOARD_INITPINS_PB7_GPIO GPIOE /*!<@brief GPIO device name: GPIOE */
+#define BOARD_INITPINS_PB7_PORT PORTE /*!<@brief PORT device name: PORTE */
+#define BOARD_INITPINS_PB7_PIN 24U /*!<@brief PORTE pin index: 24 */
+ /* @} */
+
+/*! @name PORTA19 (number 18), PMIC_LDO_E
+ @{ */
+#define BOARD_INITPINS_PMIC_LDO_E_GPIO GPIOA /*!<@brief GPIO device name: GPIOA */
+#define BOARD_INITPINS_PMIC_LDO_E_PORT PORTA /*!<@brief PORT device name: PORTA */
+#define BOARD_INITPINS_PMIC_LDO_E_PIN 19U /*!<@brief PORTA pin index: 19 */
+ /* @} */
+
+/*! @name PORTC1 (number 22), FPGA_GPIO
+ @{ */
+#define BOARD_INITPINS_FPGA_GPIO_GPIO GPIOC /*!<@brief GPIO device name: GPIOC */
+#define BOARD_INITPINS_FPGA_GPIO_PORT PORTC /*!<@brief PORT device name: PORTC */
+#define BOARD_INITPINS_FPGA_GPIO_PIN 1U /*!<@brief PORTC pin index: 1 */
+ /* @} */
+
+/*!
+ * @brief Configures pin routing and optionally pin electrical features.
+ *
+ */
+void BOARD_InitPins(void);
+
+#if defined(__cplusplus)
+}
+#endif
+
+/*!
+ * @}
+ */
+#endif /* _PIN_MUX_H_ */
+
+/***********************************************************************************************************************
+ * EOF
+ **********************************************************************************************************************/



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