diff options
| author | mindchasers <repos@mindchasers.com> | 2019-07-07 17:58:07 -0400 |
|---|---|---|
| committer | mindchasers <repos@mindchasers.com> | 2019-07-07 17:58:07 -0400 |
| commit | ed46e1a38ae2de97b55c1843bad8b813bd4936e3 (patch) | |
| tree | a19986996b97fb8daf5887eec41e5da5724dc11d /source/spi.h | |
Diffstat (limited to 'source/spi.h')
| -rw-r--r-- | source/spi.h | 71 |
1 files changed, 71 insertions, 0 deletions
diff --git a/source/spi.h b/source/spi.h new file mode 100644 index 0000000..100a73c --- /dev/null +++ b/source/spi.h @@ -0,0 +1,71 @@ +/* + * spi.h + * + * Copyright (C) 2018, 2019 Mind Chasers Inc. + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + */ + +#ifndef SPI_H_ +#define SPI_H_ + +/******************************************************************************* +* SPI Definitions +******************************************************************************/ +#define DSPI_MASTER_BASEADDR SPI0 +#define DSPI_MASTER_CLK_SRC DSPI0_CLK_SRC +#define DSPI_MASTER_CLK_FREQ CLOCK_GetFreq(DSPI0_CLK_SRC) +#define DSPI_TRANSFER_BAUDRATE 1000000U /*! Transfer baudrate - 1M */ + +/* Memory Address Map + * 9-bit words are transferred + * DEV_AD, RWN + * MEM_AD + */ + +#define SPI_READ 1 +#define SPI_WRITE 0 + +#define SPI_DEV_AD_SCI_SEL_CH_0 0x00 +#define SPI_DEV_AD_SCI_SEL_CH_1 0x01 +#define SPI_DEV_AD_DUAL_0 0x02 +#define SPI_DEV_AD_SCI_SEL_CH_2 0x04 +#define SPI_DEV_AD_SCI_SEL_CH_3 0x05 +#define SPI_DEV_AD_DUAL_1 0x06 +#define SPI_DEV_AD_DPRAM_RX 0x08 +#define SPI_DEV_AD_DPRAM_TX 0x0c +#define SPI_DEV_AD_DPRAM_PTRS 0x10 +#define SPI_DEV_AD_INT_SEL 0X11 +#define SPI_DEV_AD_PARAM_0 0x20 +#define SPI_DEV_AD_PARAM_1 0x24 +#define SPI_DEV_AD_PARAM_2 0x28 +#define SPI_DEV_AD_PARAM_2 0x2C +#define SPI_DEV_AD_PKT_FILTER_01 0X41 +#define SPI_DEV_AD_PKT_FILTER_02 0X42 +#define SPI_DEV_AD_PKT_FILTER_03 0X43 +#define SPI_DEV_AD_PKT_FILTER_10 0X48 +#define SPI_DEV_AD_PKT_FILTER_12 0X4a +#define SPI_DEV_AD_PKT_FILTER_13 0X4b +#define SPI_DEV_AD_PKT_FILTER_20 0x50 +#define SPI_DEV_AD_PKT_FILTER_21 0X51 +#define SPI_DEV_AD_PKT_FILTER_23 0X53 + + + +int spi_init(dspi_master_config_t); +int test_spi(uint8_t, uint8_t); +int write_spi(uint8_t, uint8_t, uint8_t*, uint8_t); +int read_spi(uint8_t, uint8_t, uint8_t*, uint8_t); + +#endif /* SPI_H_ */ |