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Lattice Diamond Clarity: Invert PCS / SERDES RX & TX polarity has no effect

Nov 13, 2018 asked by anonymous
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Question / Issue:

When using Diamond 3.10.2.115 and Clarity to configure a PCS IP block, the selection of inverting the RX and TX polarity bits (see attached figure) seems to have no effect. Therefore, data transmit and receive will not operate if the SERDES differential pair P and N wires are swapped.

Responses:

Date: Nov. 13, 2018

Author: Mind Chasers

Comment:

It appears that the Verilog file that is produced inadvertently sets defparam DCU0_inst.CH0_SB_BYPASS = "0b1"; defparam DCU0_inst.CH0_RX_SB_BYPASS = "0b1"; in addition to setting the following: defparam DCU0_inst.CH0_INVERT_RX = "0b1"; defparam DCU0_inst.CH0_INVERT_TX = "0b1"; Lattice's TN1261 shows (e.g., Figure 4) that an inverter is inside the SERDES bridge. Therefore, we are assuming that having the bridge bypassed also bypasses the inverter. Our work around is to manually modify the Verilog file and leave the INVERT_RX and INVERT_TX params set but clear the SB_BYPASS params. defparam DCU0_inst.CH0_SB_BYPASS = "0b0"; defparam DCU0_inst.CH0_RX_SB_BYPASS = "0b0"; defparam DCU0_inst.CH0_INVERT_RX = "0b1"; defparam DCU0_inst.CH0_INVERT_TX = "0b1";

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