Mind Chasers Inc.
Mind Chasers Inc.

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how about using open source FPGA tools to generate a bitstream for your board

May 25, 2019 asked by Edmund
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Question / Issue:

I think you know https://github.com/SymbiFlow/prjtrellis Yosys can be used to generate a netlist for ECP5. and nextpnr also supports ECP5. https://github.com/YosysHQ/nextpnr But it is definitely not yet as performant as Diamond. But we really would love to get your feedback to improve our software. We have people working fulltime to improve the ECP5 tools. yours

Responses:

Date: May 25, 2019

Author: Mind Chasers

Comment:

Yes, we're very supportive of the idea and have had people looking at it. However, we have been told that a bad bit stream can potentially damage the device. Our boards have two Gigabit Ethernet PHYs, a micrcrontroller, and an FT2232H, so they're not cheap. We can’t afford to get into a situation where people send us boards back because they burned the I/O on their ECP5. What are your thoughts on us building and supplying a stripped down Darsena that only has power, debug, and the ECPUM at a lower cost point for open source tools development? Once we know that developers can build a typical image (including driving the SERDES) without damaging the board, we would be very happy to join your effort.

Date: May 26, 2019

Author: Edmund

Comment:

I would sponsor you a board for your open source experiments. Having a stripped down version does not make any sense as we have enough ECP5 boards for our tool development. I would also buy a board to be able to run your designs ourself.

Date: May 26, 2019

Author: Mind Chasers

Comment:

Thank you. We're considering how to best move forward. Please give us a few days. Some questions for you: As you know, we're mindful of privacy and security issues. How does an open source toolchain help make a system more secure for a commercial FPGA? Is it conceivable that a company like Xilinx or Synopsys would start introducing back doors into a sea of synthesized gates? Can malware be injected into closed tools that impacts the security of the FPGA image? Are developers questioning the security of IP blocks (soft and hard)? Obviously, it’s important that an open source toolchain can be built from source and be analyzed and trusted as being secure. Do you think this is the state of Yosys and related? Does Yosys still depend on Boost? Try running "sudo apt install libboost-all-dev." There are dozens of dependencies. Do these all need to be secure for Yosys to be secure? Lastly, what's the end game for the open source toolchain? From our perspective, the next step would be to create an open FPGA. Has this been revealed yet? We would like to be involved in it.

Date: May 26, 2019

Author: Edmund

Comment:

I think this paper (from our CTO) answers your question: https://dc-cpps.tuwien.ac.at/news/news_detail/article/9188/ http://jantsch.se/AxelJantsch/papers/2016/ChristianKrieg-ICCAD.pdf It also won the best paper award :-) Darpa is currently funding two open source architectures of FPGA. But this is still early. One of them is https://osda.gitlab.io/19/index.html#3.1 BTW, the OSDA conference was organised by us :-) Concerning security: "Obviously, it’s important that an open source toolchain can be built from source and be analyzed and trusted as being secure. Do you think this is the state of Yosys and related?" Its not so much about the toolchain beeing trusted, but the Design being correct. For this you use formal verification. With formal verification, we found bugs in all RISC-V CPUs we looked at. SymbiYosys is a formal verification tool. https://github.com/YosysHQ/SymbiYosys You want to learn about formal verification at https://zipcpu.com/formal/formal.html Google Research is investing heavily in how to build secure hardware infrastructure. Mainly Ben_Laurie and Rizzo Dominic and Royal Hansen. I am looking forward to what you will come up. Ed

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