This article documents the Gigabit Ethernet demonstration that was shown at the Bay Area Maker Faire May 2019, in the booth of Samtec Corporation. The demo showcased open source, FPGA-based end-to-end Gigabit networking using the following open source software and low cost, maker hardware:
- The Private Island FPGA-based open source project for Gigabit Ethernet Networking
- Darsena, the FPGA development board for Private Island combined with a Gigabit-rate SMA shield
- Various Samtec connectors and cable assemblies suitable for maker projects, such as Arduino form-factor cards
Figures 1 through 4 below depict the demo system. Referring to Figure 1, you can see that the system is comprised of two identical Darsena / SMA shield assemblies connected together via Samtec SMA / RF cables. The system is used to transmit / switch HD video between a web camera and a Windows 10 laptop.
Each Darsena card has two Gigabit Ethernet PHYs & RJ-45 connectors; however this demonstration only makes use of one of these Ethernet PHYs per board. The data is transferred between the two cards using the passive shields and SMA / RF cables, which are transmitting and receiving data at the rate of 1.25 Gbps.
Block Diagram and Components
Figure 3 shows a block diagram of the core components involved in the demonstration. Note that only one Ethernet PHY / RJ-45 is shown since the other is not connected / utilized for the demo.
The most interesting & relevant aspects of this demo related to the show are listed below:
- A 1.25 Gbps data rate can be achieved over multiple layers of connectors and cables with low cost hardware.
- Ethernet MAC, packet filtering, and switching are all performed by a soft & open FPGA implementation.
- The FPGA transmits and receives data using 1.25 Gbps SERDES pairs that are routed to the shields (daughter cards) over standard 100 mil posts and sockets. These are the style of connectors that are commonly found on maker cards (e.g., Arduino & Raspberry Pi).
- The 1.25 Gbps data is reliably transmitted and received across two pairs of socket / post connectors, SMA connectors, and a 10" SMA / RF cable assembly.
- The boards are low cost, four layer PCBs and do not use HDI technology or controlled impedance.
- Although the ECP5UM FPGA offers equalization and de-emphassis for the SERDES transceivers, no effort was made to fine tune these features for this demo other than to adjust the voltage and termination impedance.
Explanation of Data Path
Figure 4 depicts the data path for the demo. Video is captured by a low cost HD Ethernet Web camera and transmitted to the demo system over a standard CAT5 Ethernet cable. The data is received by Darsena's Ethernet PHY0 and then transmitted to the FPGA using SGMII signaling.
The FPGA performs Ethernet MAC, packet filtering, and switching. The packet filtering is configured to pass all traffic received on PHY0 to SMA PHY2 (and PHY1 to SMA PHY3).
The (left) FPGA transmits the web camera traffic onto the SMA shield for the SMA PHY2 connectors. This path then has a hard connection to the SMA PHY3 connectors on the right Darsena system via the RF316 SMA cables.
The Ethernet data received by the SMA PHY3 connectors is transmitted to the (right) FPGA, and the FPGA Ethernet switch transmits this data to the Windows 10 laptop via PHY1. The Windows 10 laptop connects to PHY1 on (right) Darsena via a standard CAT5 Ethernet cable.
The Windows 10 laptop controls the web camera by the reverse data path. All Ethernet connectivity and data transfer uses standard TCP and UDP protocols. The IPv4 addresses for the camera and laptop are configured as static addresses.
Refer to the Private Island documentation for more information on the architecture of the open source code base for Ethernet MAC, filtering and switching.
Also, you may want to check out Samtec's related blog post: Samtec to Attend Maker Faire Bay Area 2019