Mind Chasers Inc.
Mind Chasers Inc.

A new FPGA Family: Getting Started with the Efinix Efinity Toolchain and Trion T20 on Ubuntu Linux 18.04

We document our findings while ramping up with the Efinix Efinity FPGA toolchain for their Trion architecture using a Trion T20 BGA256 Development Kit on Ubuntu Linux 18.04

Creating the United States
  • Update: We are working hard here on a follow-on to our Darsena system for Private Island and plan to announce a new maker platform in the second quarter of this year (2021). We're very excited about it!
  • We will be posting more information soon.


This article documents some of our findings while ramping up with the Efinix Efinity FPGA toolchain & IDE for their Trion architecture using a Trion T20 BGA256 Development Kit on Ubuntu Linux 18.04.

Efinix boasts a 4X Power-Performance-Area advantage over traditional FPGA technologies based on their Quantum core fabric technology and integrates hardened IP blocks that include an SDRAM controller and MIPI D-PHY.

One of the key drivers for our interest in the Efinix FPGA family is the range of device densities they offer utilizing the same Trion architecture and toolchain. The Trion T4 starts at ~4K LEs, and it ranges up to the recently announced T120. Range within a single family is important to us in order to deploy a common mission-critical networking platform that can address different applications, challenges, and price points.

Also notable is that Efinix is a relatively new, private company with various significant investors, and Xilinx is one of them.

Our first impression with Efinity and Trion is very favorable, and here's a summary of why:

  • The IDE and tools look & run great on Ubuntu Linux 18.04.
  • Lots of support for Python scripting and command line tool flow
  • XML / ASCII based project & ouput files, which are great for understanding project & technology specifics and developing projects under revision control (e.g., Git)
  • Programming a Trion project bitstream on their Dev Kit worked great on Ubuntu.
  • Development board is captured in Altium

Note that since we're new to Trion and Efinity, it's likely we have some things wrong in this article. If so, please use the comment box at the bottom of this page to let us know.

Installation on Linux

On Ubuntu 18.04, we download and extract the Efinity toolchain:

$ cd /opt
$ tar xvjf efinity-2019.2.192-ubuntu-x64.tar.bz2
$ tree -d -L 2 /opt/efinity/2019.2/
├── arch
│   ├── pgm
│   └── timing_models
├── bin
├── debugger
│   ├── bin
│   ├── demo
│   ├── doc
│   └── rtl
├── doc
│   ├── fonts
│   └── images
├── lib
│   ├── plugins
│   ├── python3.5
│   ├── tcl8.6
│   └── tk8.6
├── pgm
│   ├── bin
│   ├── doc
│   └── log
├── project
│   ├── fir
│   ├── helloworld
│   ├── pt_demo
│   └── r4000
├── pt
│   ├── bin
│   ├── db
│   ├── doc
│   └── sim_models
├── scripts
│   └── __pycache__
├── sim_models
│   ├── maplib
│   ├── verilog
│   └── vhdl
└── tcl_packages
    ├── efinity
    ├── efx_map
    └── tcllib

From their included readme:

arch/           : Architecture description files
bin/            : Executable binaries for synthesis, place & route, etc.
doc/            : Documentation
lib/            : Dynamic libraries
log/            : GUI output logs
pgm/		: Programmer Python libraries
project/        : Example projects
pt/             : Interface Designer Python libraries
scripts/        : Helper scripts for running different FPGA flows
sim_models/     : Functional simulation models for Efinity primitives
tcl_packages/   : Tcl library files, init scripts

What's included

The toolchain and Efinix website include the following:

  • Synthesis, MAP, Place & Route, and Bitstream generation
  • Interface Designer to constrain logic and assign interfaces
  • Floorplan Editor
  • Support for Synopsys Design Constraints (SDC)
  • Static timing analysis
  • A nice looking but basic code editor with syntax highlighting
  • Programmer
  • Tcl Command Console
  • Example designs for their various parts
  • Altium Schematic and Layout files for their Dev Kits
  • Orcad schematic and footprint symbols
  • User forum

What's not included

Trion seems to be missing an internal logic analyzer to debug logic in-system via JTAG. For us, this is notable.

Also, the Efinity toolchain does not bundle a Verilog simulator but instead recommends the following:

By default, the Python simulation scripts assume the developer has iVerilog installed, so let's perform a basic install of iVerilog and GTKWave on our Ubuntu machine:

$ sudo apt install iverilog
$ sudo apt install gtkwave

Launching and Using Efinity IDE

Let's launch the IDE from an X11 SSH shell into our Ubuntu machine (using XQuartz on macOS):

$ source /opt/efinity/2019.2/bin/setup.sh 


$ efinity_sh.sh

The figure below shows the Efinity IDE and is taken from the Efinity Software User Guide:

Efinity IDE
Efinity IDE

The IDE is very clean and intuitive. Plus, support for working from the command line via Python scripts is provided. Therefore, we have the choice of either using the IDE or we can run the flow using efx_run.py (we show this below).

Trion T20

Efinix states that their Trion FPGAs have a power-performance-area advantage over traditional FPGAs. They tout their Quantum routing fabric technology, which is the core of the T20. They blend the routing fabric with memory and multiplier blocks and wrap it with various interfaces including LVDS, an SDRAM controller, and even a hardened, multi-lane MIPI D-PHY.

Trion Block Diagram
Trion Block Diagram

The T20 has the following features:

  • ~20K Logic Elements
  • Up to 16 global clocks
  • 36 multipliers
  • ~1Mb of embedded memory.
  • The price for quantity one is ~$15 on Digi-key.

Trion T20 BGA256 Development Kit

We just received the T20 Dev Kit and we were so happy to discover that Efinix makes available the Altium design files for it including the PCB layout. For us, this makes it very easy to dig in and understand the board.

The T20 Dev Kit has the following features (pic shown below):

  • 256 Mb SDR SDRAM (16Mx16)
  • 32 Mb serial FLASH
  • Differential I/O headers
  • Lots of LEDs and single-ended GPIO posts
  • USB to FTDI programming / JTAG support
  • Clocks, switches, etc.

Example Project for T20 Dev Kit

Below we show parts of the toolchain flow using an Efinix provided design example: "Trion T20 Double Data Input/Output (ddio.xml)". This is a simple project that shows the use of their integrated PLL and DDR I/O.

Let's first use the command line to run the flow of synthesis, place & route, and bitstream generation:

$ efx_run.py ddio.xml --flow compile
Running: efx_run_map.py ddio --family Trion --device T20F256 -v ddio_top.v,t:verilog_2k --output_dir outflow --opt root=ddio_top --opt veri_options=verilog_mode=verilog_2k,vhdl_mode=vhdl_2008 work-dir=work_syn write_efx_verilog=on syn_options=mode=speed
   map :	PASS 
Running: efx_run_pt.py ddio Trion T20F256
   interface :	PASS 
Running: efx_run_pnr.py ddio --prj --family Trion --device T20F256 --timing_model C4 --sim --output_dir outflow --opt sdc_file=ddio.sdc --opt work_dir=work_pnr
   pnr :	PASS 
Running: efx_run_pgm.py ddio --family Trion --device T20F256 --output_dir outflow --opt mode=active width=1 enable_roms=on spi_low_power_mode=on io_weak_pullup=on oscillator_clock_divider=DIV8 enable_crc_check=off
   pgm :	PASS 

Let's return to the IDE and take a look at the Efinity Interface Designer for the PLL configuration. We can use this tool to change our I/O & configuration and write our changes out to a constraints file.

Interface Designer
Efinity Interface Designer

The picture below is from our lab bench probing two GPIO header posts on the Trion T20 Dev Kit when working with their DDR example project.

Trion T20 Dev Board
Trion T20 Dev Kit

The scope screenshot below is the result of probing the 150 MHz PLL output (lower probe, yellow trace) and the DDR output.

T20 DDR Scope Plot
Scope Screenshot of the T20 DDR Example

Under the hood

Below we show some snippets of the console output when compiling the example project within the IDE.

[EFX-0000 INFO] Efinix FPGA Synthesis.
[EFX-0000 INFO] Version: 2019.2.192
[EFX-0000 INFO] Compiled: Aug 21 2019.
[EFX-0000 INFO] 
[EFX-0000 INFO] Copyright (C) 2013 - 2019 Efinix Inc. All rights reserved.
Efinix FPGA Placement and Routing.
Version: 2019.2.192 
Compiled: Aug 21 2019.
Copyright (C) 2013 - 2019 Efinix Inc. All rights reserved.

The Tool Is Based on VPR of University of Toronto,
a free open source code under MIT license.

Next, let's start with a fresh example project and compile it using the command line while examining the outputs and folder structure:

$ source /opt/efinity/2019.2/bin/setup.sh

$ efx_run.py --help
usage: efx_run.py [-h] [--prj]
                  [-f {map,interface,pnr,pgm,compile,program,rtlsim,mapsim,pnrsim,full}]
                  [--family FAMILY] [-d DEVICE] [--timing_model TIMING_MODEL]
                  [-v EXTRA_FILES [EXTRA_FILES ...] | --flist FLIST]
                  [--tb TB_EXTRA_FILES] [--tb_top TB_TOP] [--dir SOURCE_DIR]
                  [--map_opts MAP_OPTS [MAP_OPTS ...]]
                  [--pnr_opts VPR_OPTS [VPR_OPTS ...]]
                  [--pgm_opts PGM_OPTS [PGM_OPTS ...]] [-m] [--ncsim]
                  [--map_compare] [--sim_if] [--output_dir OUTPUT_DIR]
                  [--work_dir WORK_DIR] [--cleanup_work_dir CLEANUP_WORK_DIR]

# Unfortunately, efx_run.py doesn't seem to have a verbose flag.

$ cd ~/Projects/efinix/ddio-t20-2018.4-v1.0
$ tree
├── abc.history
├── ddio.peri.xml
├── ddio.sdc
├── ddio_top.v
├── ddio.vdb
├── ddio.xml
├── outflow
│   ├── ddio.err.log
│   ├── ddio.hex
│   ├── ddio.info.log
│   ├── ddio.interface.csv
│   ├── ddio.interface.io
│   ├── ddio.lpf
│   ├── ddio.map.out
│   ├── ddio.map.rpt
│   ├── ddio.map.rpt.xml
│   ├── ddio.map.v
│   ├── ddio.pgm.out
│   ├── ddio.pinout.csv
│   ├── ddio.place
│   ├── ddio.place.out
│   ├── ddio.place.rpt
│   ├── ddio.pt.rpt
│   ├── ddio.pt.sdc
│   ├── ddio.pt_timing.rpt
│   ├── ddio.qplace
│   ├── ddio.route
│   ├── ddio.route.out
│   ├── ddio.route.rpt
│   ├── ddio.route.rpt.xml
│   ├── ddio_template.v
│   ├── ddio.timing.rpt
│   └── ddio.warn.log
├── profile_groups.txt
├── tcl_stacktrace.txt
├── work_pnr
│   ├── ddio.io_place
│   ├── ddio.lbf
│   ├── ddio.net_proto
│   ├── ddio.prevpr.vdb
│   ├── ddio.qchip
│   ├── ddio.qlib
│   ├── ddio.qnet
│   ├── run_efx_pgm.sh
│   └── run_efx_pnr.sh
└── work_syn
    └── run_efx_map.sh

The folder structure shown above is our starting point when unzipping the example project archive. Evidently the example project ships already built. It would be nice here to have the ability to clean the project and get rid of all intermediate files.

Let's work to recompile the project step-by-step:

# synthesize / map
$ efx_run.py ddio.xml --flow map
Running: efx_run_map.py ddio --family Trion --device T20F256 -v ddio_top.v --output_dir outflow --opt root=ddio_top --opt work-dir=work_syn write_efx_verilog=on syn_options=mode=speed
   map :	PASS 
# place and route
$ efx_run.py ddio.xml --flow pnr
Running: efx_run_pnr.py ddio --prj --family Trion --device T20F256 --timing_model C4 --sim --output_dir outflow --opt sdc_file=ddio.sdc --opt work_dir=work_pnr

   pnr :	PASS 

# create a bitstream hex file
$ efx_run.py ddio.xml --flow pgm
Running: efx_run_pgm.py ddio --family Trion --device T20F256 --output_dir outflow --opt mode=active width=1 enable_roms=on spi_low_power_mode=on io_weak_pullup=on oscillator_clock_divider=DIV8 enable_crc_check=off
   pgm :	PASS 

Let's take a look at what other scripts are available to us:

$ cd /opt/efinity/2019.2/scripts/
$ ls *.py
efinity_pgm_tk.py         efx_run_map.py  efx_run_pnr.py  efx_run.py      qp_vpr_sdc_verification.py
efx_generate_if_files.py  efx_run_pgm.py  efx_run_pt.py   efx_run_sim.py

From using the tools and peeking inside the scripts, it appears that efx_run.py calls the other scripts depending on the task / flow required.

Suggestions for Improvement

  • An internal logic analyzer similar to Intel's SignalTap and Lattice's Reveal is needed, and we understand that debug features are coming to the toolchain.
  • Enhance the Code Editor to include auto formating, printing, and linting
  • Add a project clean as an option under Menu -> FLow

Next Steps

We're just getting started with Trion & Efinity and we plan to periodically update and expand this article as we learn and do more with this exciting new FPGA family.

Some of our next steps include simulating primitives, configuration of IP, and evaluating time to compile a complex design.

We're also investigating a port of Private Island ® to Trion utilizing RGMII PHYs.

Additional References

Didn't find an answer to your question? Post your issue below or in our new FORUM, and we'll try our best to help you find a solution.

And please note that we update our site daily with new content related to our open source approach to network security and system design. If you would like to be notified about these changes, then please follow us on Twitter and join our mailing list.

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